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bp_mod.c
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1 /******************************************************************************/
2 /* */
3 /* Bypass Control utility, Copyright (c) 2005-20011 Silicom */
4 /* */
5 /* This program is free software; you can redistribute it and/or modify */
6 /* it under the terms of the GNU General Public License as published by */
7 /* the Free Software Foundation, located in the file LICENSE. */
8 /* Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved. */
9 /* */
10 /* */
11 /******************************************************************************/
12 #include <linux/version.h>
13 
14 #include <linux/kernel.h> /* We're doing kernel work */
15 #include <linux/module.h> /* Specifically, a module */
16 #include <linux/fs.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/netdevice.h>
20 #include <linux/rtnetlink.h>
21 #include <linux/rcupdate.h>
22 #include <linux/etherdevice.h>
23 
24 #include <linux/uaccess.h> /* for get_user and put_user */
25 #include <linux/sched.h>
26 #include <linux/ethtool.h>
27 #include <linux/proc_fs.h>
28 
29 #include "bp_ioctl.h"
30 #include "bp_mod.h"
31 #include "bypass.h"
32 #include "libbp_sd.h"
33 
34 #define SUCCESS 0
35 #define BP_MOD_VER "9.0.4"
36 #define BP_MOD_DESCR "Silicom Bypass-SD Control driver"
37 #define BP_SYNC_FLAG 1
38 
39 static int Device_Open = 0;
40 static int major_num = 0;
41 
42 MODULE_AUTHOR("Anna Lukin, [email protected]");
43 MODULE_LICENSE("GPL");
44 MODULE_DESCRIPTION(BP_MOD_DESCR);
45 MODULE_VERSION(BP_MOD_VER);
46 spinlock_t bpvm_lock;
47 
48 #define lock_bpctl() \
49 if (down_interruptible(&bpctl_sema)) { \
50  return -ERESTARTSYS; \
51 } \
52 
53 #define unlock_bpctl() \
54  up(&bpctl_sema);
55 
56 /* Media Types */
57 typedef enum {
58  bp_copper = 0,
59  bp_fiber,
60  bp_cx4,
61  bp_none,
62 } bp_media_type;
63 
64 struct pfs_unit_sd {
65  struct proc_dir_entry *proc_entry;
66  char proc_name[32];
67 };
68 
69 struct bypass_pfs_sd {
70  char dir_name[32];
71  struct proc_dir_entry *bypass_entry;
72  struct pfs_unit_sd bypass_info;
73  struct pfs_unit_sd bypass_slave;
74  struct pfs_unit_sd bypass_caps;
75  struct pfs_unit_sd wd_set_caps;
76  struct pfs_unit_sd bypass;
77  struct pfs_unit_sd bypass_change;
78  struct pfs_unit_sd bypass_wd;
79  struct pfs_unit_sd wd_expire_time;
80  struct pfs_unit_sd reset_bypass_wd;
81  struct pfs_unit_sd dis_bypass;
82  struct pfs_unit_sd bypass_pwup;
83  struct pfs_unit_sd bypass_pwoff;
84  struct pfs_unit_sd std_nic;
85  struct pfs_unit_sd tap;
86  struct pfs_unit_sd dis_tap;
87  struct pfs_unit_sd tap_pwup;
88  struct pfs_unit_sd tap_change;
89  struct pfs_unit_sd wd_exp_mode;
90  struct pfs_unit_sd wd_autoreset;
91  struct pfs_unit_sd tpl;
92 
93 };
94 
95 typedef struct _bpctl_dev {
96  char *name;
97  char *desc;
98  struct pci_dev *pdev; /* PCI device */
99  struct net_device *ndev; /* net device */
100  unsigned long mem_map;
101  uint8_t bus;
102  uint8_t slot;
103  uint8_t func;
104  u_int32_t device;
105  u_int32_t vendor;
106  u_int32_t subvendor;
107  u_int32_t subdevice;
108  int ifindex;
109  uint32_t bp_caps;
110  uint32_t bp_caps_ex;
111  uint8_t bp_fw_ver;
112  int bp_ext_ver;
113  int wdt_status;
114  unsigned long bypass_wdt_on_time;
115  uint32_t bypass_timer_interval;
116  struct timer_list bp_timer;
117  uint32_t reset_time;
118  uint8_t bp_status_un;
119  atomic_t wdt_busy;
120  bp_media_type media_type;
121  int bp_tpl_flag;
122  struct timer_list bp_tpl_timer;
123  spinlock_t bypass_wr_lock;
124  int bp_10g;
125  int bp_10gb;
126  int bp_fiber5;
127  int bp_10g9;
128  int bp_i80;
129  int bp_540;
130  int (*hard_start_xmit_save) (struct sk_buff *skb,
131  struct net_device *dev);
132  const struct net_device_ops *old_ops;
133  struct net_device_ops new_ops;
134  int bp_self_test_flag;
135  char *bp_tx_data;
136  struct bypass_pfs_sd bypass_pfs_set;
137 
138 } bpctl_dev_t;
139 
140 static bpctl_dev_t *bpctl_dev_arr;
141 
142 static struct semaphore bpctl_sema;
143 static int device_num = 0;
144 
145 static int get_dev_idx(int ifindex);
146 static bpctl_dev_t *get_master_port_fn(bpctl_dev_t *pbpctl_dev);
147 static int disc_status(bpctl_dev_t *pbpctl_dev);
148 static int bypass_status(bpctl_dev_t *pbpctl_dev);
149 static int wdt_timer(bpctl_dev_t *pbpctl_dev, int *time_left);
150 static bpctl_dev_t *get_status_port_fn(bpctl_dev_t *pbpctl_dev);
151 static void if_scan_init(void);
152 
153 int bypass_proc_create_dev_sd(bpctl_dev_t *pbp_device_block);
154 int bypass_proc_remove_dev_sd(bpctl_dev_t *pbp_device_block);
155 int bp_proc_create(void);
156 
157 int is_bypass_fn(bpctl_dev_t *pbpctl_dev);
158 int get_dev_idx_bsf(int bus, int slot, int func);
159 
160 static unsigned long str_to_hex(char *p);
161 static int bp_device_event(struct notifier_block *unused,
162  unsigned long event, void *ptr)
163 {
164  struct net_device *dev = ptr;
165  static bpctl_dev_t *pbpctl_dev = NULL, *pbpctl_dev_m = NULL;
166  int dev_num = 0, ret = 0, ret_d = 0, time_left = 0;
167  /* printk("BP_PROC_SUPPORT event =%d %s %d\n", event,dev->name, dev->ifindex ); */
168  /* return NOTIFY_DONE; */
169  if (!dev)
170  return NOTIFY_DONE;
171  if (event == NETDEV_REGISTER) {
172  {
173  struct ethtool_drvinfo drvinfo;
174  char cbuf[32];
175  char *buf = NULL;
176  char res[10];
177  int i = 0, ifindex, idx_dev = 0;
178  int bus = 0, slot = 0, func = 0;
179  ifindex = dev->ifindex;
180 
181  memset(res, 0, 10);
182  memset(&drvinfo, 0, sizeof(struct ethtool_drvinfo));
183 
184  if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
185  memset(&drvinfo, 0, sizeof(drvinfo));
186  dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
187  } else
188  return NOTIFY_DONE;
189  if (!drvinfo.bus_info)
190  return NOTIFY_DONE;
191  if (!strcmp(drvinfo.bus_info, "N/A"))
192  return NOTIFY_DONE;
193  memcpy(&cbuf, drvinfo.bus_info, 32);
194  buf = &cbuf[0];
195 
196  while (*buf++ != ':') ;
197  for (i = 0; i < 10; i++, buf++) {
198  if (*buf == ':')
199  break;
200  res[i] = *buf;
201 
202  }
203  buf++;
204  bus = str_to_hex(res);
205  memset(res, 0, 10);
206 
207  for (i = 0; i < 10; i++, buf++) {
208  if (*buf == '.')
209  break;
210  res[i] = *buf;
211 
212  }
213  buf++;
214  slot = str_to_hex(res);
215  func = str_to_hex(buf);
216  idx_dev = get_dev_idx_bsf(bus, slot, func);
217 
218  if (idx_dev != -1) {
219 
220  bpctl_dev_arr[idx_dev].ifindex = ifindex;
221  bpctl_dev_arr[idx_dev].ndev = dev;
222 
223  bypass_proc_remove_dev_sd(&bpctl_dev_arr
224  [idx_dev]);
225  bypass_proc_create_dev_sd(&bpctl_dev_arr
226  [idx_dev]);
227 
228  }
229 
230  }
231  return NOTIFY_DONE;
232 
233  }
234  if (event == NETDEV_UNREGISTER) {
235  int idx_dev = 0;
236  for (idx_dev = 0;
237  ((bpctl_dev_arr[idx_dev].pdev != NULL)
238  && (idx_dev < device_num)); idx_dev++) {
239  if (bpctl_dev_arr[idx_dev].ndev == dev) {
240  bypass_proc_remove_dev_sd(&bpctl_dev_arr
241  [idx_dev]);
242  bpctl_dev_arr[idx_dev].ndev = NULL;
243 
244  return NOTIFY_DONE;
245 
246  }
247 
248  }
249  return NOTIFY_DONE;
250  }
251  if (event == NETDEV_CHANGENAME) {
252  int idx_dev = 0;
253  for (idx_dev = 0;
254  ((bpctl_dev_arr[idx_dev].pdev != NULL)
255  && (idx_dev < device_num)); idx_dev++) {
256  if (bpctl_dev_arr[idx_dev].ndev == dev) {
257  bypass_proc_remove_dev_sd(&bpctl_dev_arr
258  [idx_dev]);
259  bypass_proc_create_dev_sd(&bpctl_dev_arr
260  [idx_dev]);
261 
262  return NOTIFY_DONE;
263 
264  }
265 
266  }
267  return NOTIFY_DONE;
268 
269  }
270 
271  switch (event) {
272 
273  case NETDEV_CHANGE:{
274  if (netif_carrier_ok(dev))
275  return NOTIFY_DONE;
276 
277  if (((dev_num = get_dev_idx(dev->ifindex)) == -1) ||
278  (!(pbpctl_dev = &bpctl_dev_arr[dev_num])))
279  return NOTIFY_DONE;
280 
281  if ((is_bypass_fn(pbpctl_dev)) == 1)
282  pbpctl_dev_m = pbpctl_dev;
283  else
284  pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
285  if (!pbpctl_dev_m)
286  return NOTIFY_DONE;
287  ret = bypass_status(pbpctl_dev_m);
288  if (ret == 1)
289  printk("bpmod: %s is in the Bypass mode now",
290  dev->name);
291  ret_d = disc_status(pbpctl_dev_m);
292  if (ret_d == 1)
293  printk
294  ("bpmod: %s is in the Disconnect mode now",
295  dev->name);
296  if (ret || ret_d) {
297  wdt_timer(pbpctl_dev_m, &time_left);
298  if (time_left == -1)
299  printk("; WDT has expired");
300  printk(".\n");
301 
302  }
303  return NOTIFY_DONE;
304 
305  }
306 
307  default:
308  return NOTIFY_DONE;
309 
310  }
311  return NOTIFY_DONE;
312 
313 }
314 
315 static struct notifier_block bp_notifier_block = {
316  .notifier_call = bp_device_event,
317 };
318 
319 static int device_open(struct inode *inode, struct file *file)
320 {
321 #ifdef DEBUG
322  printk("device_open(%p)\n", file);
323 #endif
324  Device_Open++;
325 /*
326 * Initialize the message
327 */
328  return SUCCESS;
329 }
330 
331 static int device_release(struct inode *inode, struct file *file)
332 {
333 #ifdef DEBUG
334  printk("device_release(%p,%p)\n", inode, file);
335 #endif
336  Device_Open--;
337  return SUCCESS;
338 }
339 
340 int is_bypass_fn(bpctl_dev_t *pbpctl_dev);
341 int wdt_time_left(bpctl_dev_t *pbpctl_dev);
342 
343 static void write_pulse(bpctl_dev_t *pbpctl_dev,
344  unsigned int ctrl_ext,
345  unsigned char value, unsigned char len)
346 {
347  unsigned char ctrl_val = 0;
348  unsigned int i = len;
349  unsigned int ctrl = 0;
350  bpctl_dev_t *pbpctl_dev_c = NULL;
351 
352  if (pbpctl_dev->bp_i80)
353  ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
354  if (pbpctl_dev->bp_540)
355  ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
356 
357  if (pbpctl_dev->bp_10g9) {
358  if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
359  return;
360  ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
361  }
362 
363  while (i--) {
364  ctrl_val = (value >> i) & 0x1;
365  if (ctrl_val) {
366  if (pbpctl_dev->bp_10g9) {
367 
368  /* To start management : MCLK 1, MDIO 1, output */
369  /* DATA 1 CLK 1 */
370  /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
371  BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
372  ctrl_ext |
373  BP10G_MDIO_DATA_OUT9);
374  BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
375  (ctrl | BP10G_MCLK_DATA_OUT9 |
376  BP10G_MCLK_DIR_OUT9));
377 
378  } else if (pbpctl_dev->bp_fiber5) {
379  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
380  BPCTLI_CTRL_EXT_MCLK_DIR5
381  |
382  BPCTLI_CTRL_EXT_MDIO_DIR5
383  |
384  BPCTLI_CTRL_EXT_MDIO_DATA5
385  |
386  BPCTLI_CTRL_EXT_MCLK_DATA5));
387 
388  } else if (pbpctl_dev->bp_i80) {
389  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
390  BPCTLI_CTRL_EXT_MDIO_DIR80
391  |
392  BPCTLI_CTRL_EXT_MDIO_DATA80));
393 
394  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, (ctrl |
395  BPCTLI_CTRL_EXT_MCLK_DIR80
396  |
397  BPCTLI_CTRL_EXT_MCLK_DATA80));
398 
399  } else if (pbpctl_dev->bp_540) {
400  BP10G_WRITE_REG(pbpctl_dev, ESDP, (ctrl |
401  BP540_MDIO_DIR
402  |
403  BP540_MDIO_DATA
404  |
405  BP540_MCLK_DIR
406  |
407  BP540_MCLK_DATA));
408 
409  } else if (pbpctl_dev->bp_10gb) {
410  BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
411  (ctrl_ext | BP10GB_MDIO_SET |
412  BP10GB_MCLK_SET) &
413  ~(BP10GB_MCLK_DIR |
414  BP10GB_MDIO_DIR |
415  BP10GB_MDIO_CLR |
416  BP10GB_MCLK_CLR));
417 
418  } else if (!pbpctl_dev->bp_10g)
419  /* To start management : MCLK 1, MDIO 1, output */
420  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
421  (ctrl_ext |
422  BPCTLI_CTRL_EXT_MCLK_DIR |
423  BPCTLI_CTRL_EXT_MDIO_DIR |
424  BPCTLI_CTRL_EXT_MDIO_DATA |
425  BPCTLI_CTRL_EXT_MCLK_DATA));
426  else {
427 
428  /* To start management : MCLK 1, MDIO 1, output*/
429  BP10G_WRITE_REG(pbpctl_dev, EODSDP,
430  (ctrl_ext | BP10G_MCLK_DATA_OUT
431  | BP10G_MDIO_DATA_OUT));
432 
433  }
434 
435  usec_delay(PULSE_TIME);
436  if (pbpctl_dev->bp_10g9) {
437 
438  /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~(BP10G_MCLK_DATA_OUT9))); */
439  /* DATA 1 CLK 0 */
440  BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
441  ctrl_ext |
442  BP10G_MDIO_DATA_OUT9);
443  BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
444  (ctrl | BP10G_MCLK_DIR_OUT9) &
445  ~BP10G_MCLK_DATA_OUT9);
446 
447  } else if (pbpctl_dev->bp_fiber5) {
448  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
449  ((ctrl_ext |
450  BPCTLI_CTRL_EXT_MCLK_DIR5 |
451  BPCTLI_CTRL_EXT_MDIO_DIR5 |
452  BPCTLI_CTRL_EXT_MDIO_DATA5)
453  &
454  ~
455  (BPCTLI_CTRL_EXT_MCLK_DATA5)));
456 
457  } else if (pbpctl_dev->bp_i80) {
458  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
459  BPCTLI_CTRL_EXT_MDIO_DIR80
460  |
461  BPCTLI_CTRL_EXT_MDIO_DATA80));
462  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
463  ((ctrl |
464  BPCTLI_CTRL_EXT_MCLK_DIR80)
465  &
466  ~
467  (BPCTLI_CTRL_EXT_MCLK_DATA80)));
468 
469  } else if (pbpctl_dev->bp_540) {
470  BP10G_WRITE_REG(pbpctl_dev, ESDP,
471  (ctrl | BP540_MDIO_DIR |
472  BP540_MDIO_DATA |
473  BP540_MCLK_DIR) &
474  ~(BP540_MCLK_DATA));
475 
476  } else if (pbpctl_dev->bp_10gb) {
477 
478  BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
479  (ctrl_ext | BP10GB_MDIO_SET |
480  BP10GB_MCLK_CLR) &
481  ~(BP10GB_MCLK_DIR |
482  BP10GB_MDIO_DIR |
483  BP10GB_MDIO_CLR |
484  BP10GB_MCLK_SET));
485 
486  } else if (!pbpctl_dev->bp_10g)
487 
488  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
489  ((ctrl_ext |
490  BPCTLI_CTRL_EXT_MCLK_DIR |
491  BPCTLI_CTRL_EXT_MDIO_DIR |
492  BPCTLI_CTRL_EXT_MDIO_DATA)
493  &
494  ~
495  (BPCTLI_CTRL_EXT_MCLK_DATA)));
496  else {
497 
498  BP10G_WRITE_REG(pbpctl_dev, EODSDP,
499  ((ctrl_ext |
500  BP10G_MDIO_DATA_OUT) &
501  ~(BP10G_MCLK_DATA_OUT)));
502  }
503 
504  usec_delay(PULSE_TIME);
505 
506  } else {
507  if (pbpctl_dev->bp_10g9) {
508  /* DATA 0 CLK 1 */
509  /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
510  BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
511  (ctrl_ext &
512  ~BP10G_MDIO_DATA_OUT9));
513  BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
514  (ctrl | BP10G_MCLK_DATA_OUT9 |
515  BP10G_MCLK_DIR_OUT9));
516 
517  } else if (pbpctl_dev->bp_fiber5) {
518  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
519  ((ctrl_ext |
520  BPCTLI_CTRL_EXT_MCLK_DIR5 |
521  BPCTLI_CTRL_EXT_MDIO_DIR5 |
522  BPCTLI_CTRL_EXT_MCLK_DATA5)
523  &
524  ~
525  (BPCTLI_CTRL_EXT_MDIO_DATA5)));
526 
527  } else if (pbpctl_dev->bp_i80) {
528  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
529  ((ctrl_ext |
530  BPCTLI_CTRL_EXT_MDIO_DIR80)
531  &
532  ~
533  (BPCTLI_CTRL_EXT_MDIO_DATA80)));
534  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
535  (ctrl |
536  BPCTLI_CTRL_EXT_MCLK_DIR80 |
537  BPCTLI_CTRL_EXT_MCLK_DATA80));
538 
539  } else if (pbpctl_dev->bp_540) {
540  BP10G_WRITE_REG(pbpctl_dev, ESDP,
541  ((ctrl | BP540_MCLK_DIR |
542  BP540_MCLK_DATA |
543  BP540_MDIO_DIR) &
544  ~(BP540_MDIO_DATA)));
545 
546  } else if (pbpctl_dev->bp_10gb) {
547  BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
548  (ctrl_ext | BP10GB_MDIO_CLR |
549  BP10GB_MCLK_SET) &
550  ~(BP10GB_MCLK_DIR |
551  BP10GB_MDIO_DIR |
552  BP10GB_MDIO_SET |
553  BP10GB_MCLK_CLR));
554 
555  } else if (!pbpctl_dev->bp_10g)
556 
557  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
558  ((ctrl_ext |
559  BPCTLI_CTRL_EXT_MCLK_DIR |
560  BPCTLI_CTRL_EXT_MDIO_DIR |
561  BPCTLI_CTRL_EXT_MCLK_DATA)
562  &
563  ~
564  (BPCTLI_CTRL_EXT_MDIO_DATA)));
565  else {
566 
567  BP10G_WRITE_REG(pbpctl_dev, EODSDP,
568  ((ctrl_ext |
569  BP10G_MCLK_DATA_OUT) &
570  ~BP10G_MDIO_DATA_OUT));
571 
572  }
573  usec_delay(PULSE_TIME);
574  if (pbpctl_dev->bp_10g9) {
575  /* DATA 0 CLK 0 */
576  /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
577  BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
578  (ctrl_ext &
579  ~BP10G_MDIO_DATA_OUT9));
580  BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
581  ((ctrl | BP10G_MCLK_DIR_OUT9) &
582  ~(BP10G_MCLK_DATA_OUT9)));
583 
584  } else if (pbpctl_dev->bp_fiber5) {
585  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
586  ((ctrl_ext |
587  BPCTLI_CTRL_EXT_MCLK_DIR5 |
588  BPCTLI_CTRL_EXT_MDIO_DIR5)
589  &
590  ~(BPCTLI_CTRL_EXT_MCLK_DATA5
591  |
592  BPCTLI_CTRL_EXT_MDIO_DATA5)));
593 
594  } else if (pbpctl_dev->bp_i80) {
595  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
596  ((ctrl_ext |
597  BPCTLI_CTRL_EXT_MDIO_DIR80)
598  &
599  ~BPCTLI_CTRL_EXT_MDIO_DATA80));
600  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
601  ((ctrl |
602  BPCTLI_CTRL_EXT_MCLK_DIR80)
603  &
604  ~
605  (BPCTLI_CTRL_EXT_MCLK_DATA80)));
606 
607  } else if (pbpctl_dev->bp_540) {
608  BP10G_WRITE_REG(pbpctl_dev, ESDP,
609  ((ctrl | BP540_MCLK_DIR |
610  BP540_MDIO_DIR) &
611  ~(BP540_MDIO_DATA |
612  BP540_MCLK_DATA)));
613  } else if (pbpctl_dev->bp_10gb) {
614 
615  BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
616  (ctrl_ext | BP10GB_MDIO_CLR |
617  BP10GB_MCLK_CLR) &
618  ~(BP10GB_MCLK_DIR |
619  BP10GB_MDIO_DIR |
620  BP10GB_MDIO_SET |
621  BP10GB_MCLK_SET));
622 
623  } else if (!pbpctl_dev->bp_10g)
624  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
625  ((ctrl_ext |
626  BPCTLI_CTRL_EXT_MCLK_DIR |
627  BPCTLI_CTRL_EXT_MDIO_DIR) &
628  ~(BPCTLI_CTRL_EXT_MCLK_DATA
629  |
630  BPCTLI_CTRL_EXT_MDIO_DATA)));
631  else {
632 
633  BP10G_WRITE_REG(pbpctl_dev, EODSDP,
634  (ctrl_ext &
635  ~(BP10G_MCLK_DATA_OUT |
636  BP10G_MDIO_DATA_OUT)));
637  }
638 
639  usec_delay(PULSE_TIME);
640  }
641 
642  }
643 }
644 
645 static int read_pulse(bpctl_dev_t *pbpctl_dev, unsigned int ctrl_ext,
646  unsigned char len)
647 {
648  unsigned char ctrl_val = 0;
649  unsigned int i = len;
650  unsigned int ctrl = 0;
651  bpctl_dev_t *pbpctl_dev_c = NULL;
652 
653  if (pbpctl_dev->bp_i80)
654  ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
655  if (pbpctl_dev->bp_540)
656  ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
657  if (pbpctl_dev->bp_10g9) {
658  if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
659  return -1;
660  ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
661  }
662 
663 
664  while (i--) {
665  if (pbpctl_dev->bp_10g9) {
666  /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~BP10G_MCLK_DATA_OUT9)); */
667  /* DATA ? CLK 0 */
668  BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
669  ((ctrl | BP10G_MCLK_DIR_OUT9) &
670  ~(BP10G_MCLK_DATA_OUT9)));
671 
672  } else if (pbpctl_dev->bp_fiber5) {
673  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
674  BPCTLI_CTRL_EXT_MCLK_DIR5)
675  &
676  ~
677  (BPCTLI_CTRL_EXT_MDIO_DIR5
678  |
679  BPCTLI_CTRL_EXT_MCLK_DATA5)));
680 
681  } else if (pbpctl_dev->bp_i80) {
682  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
683  (ctrl_ext &
684  ~BPCTLI_CTRL_EXT_MDIO_DIR80));
685  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
686  ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80)
687  & ~(BPCTLI_CTRL_EXT_MCLK_DATA80)));
688 
689  } else if (pbpctl_dev->bp_540) {
690  BP10G_WRITE_REG(pbpctl_dev, ESDP,
691  ((ctrl | BP540_MCLK_DIR) &
692  ~(BP540_MDIO_DIR | BP540_MCLK_DATA)));
693 
694  } else if (pbpctl_dev->bp_10gb) {
695 
696  BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
697  (ctrl_ext | BP10GB_MDIO_DIR |
698  BP10GB_MCLK_CLR) & ~(BP10GB_MCLK_DIR |
699  BP10GB_MDIO_CLR |
700  BP10GB_MDIO_SET |
701  BP10GB_MCLK_SET));
702 
703  } else if (!pbpctl_dev->bp_10g)
704  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
705  BPCTLI_CTRL_EXT_MCLK_DIR)
706  &
707  ~
708  (BPCTLI_CTRL_EXT_MDIO_DIR
709  |
710  BPCTLI_CTRL_EXT_MCLK_DATA)));
711  else {
712 
713  BP10G_WRITE_REG(pbpctl_dev, EODSDP, ((ctrl_ext | BP10G_MDIO_DATA_OUT) & ~BP10G_MCLK_DATA_OUT)); /* ? */
714  /* printk("0x28=0x%x\n",BP10G_READ_REG(pbpctl_dev,EODSDP);); */
715 
716  }
717 
718  usec_delay(PULSE_TIME);
719  if (pbpctl_dev->bp_10g9) {
720  /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
721  /* DATA ? CLK 1 */
722  BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
723  (ctrl | BP10G_MCLK_DATA_OUT9 |
724  BP10G_MCLK_DIR_OUT9));
725 
726  } else if (pbpctl_dev->bp_fiber5) {
727  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
728  BPCTLI_CTRL_EXT_MCLK_DIR5
729  |
730  BPCTLI_CTRL_EXT_MCLK_DATA5)
731  &
732  ~
733  (BPCTLI_CTRL_EXT_MDIO_DIR5)));
734 
735  } else if (pbpctl_dev->bp_i80) {
736  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
737  (ctrl_ext &
738  ~(BPCTLI_CTRL_EXT_MDIO_DIR80)));
739  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
740  (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
741  BPCTLI_CTRL_EXT_MCLK_DATA80));
742 
743  } else if (pbpctl_dev->bp_540) {
744  BP10G_WRITE_REG(pbpctl_dev, ESDP,
745  ((ctrl | BP540_MCLK_DIR |
746  BP540_MCLK_DATA) &
747  ~(BP540_MDIO_DIR)));
748 
749  } else if (pbpctl_dev->bp_10gb) {
750  BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
751  (ctrl_ext | BP10GB_MDIO_DIR |
752  BP10GB_MCLK_SET) & ~(BP10GB_MCLK_DIR |
753  BP10GB_MDIO_CLR |
754  BP10GB_MDIO_SET |
755  BP10GB_MCLK_CLR));
756 
757  } else if (!pbpctl_dev->bp_10g)
758  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
759  BPCTLI_CTRL_EXT_MCLK_DIR
760  |
761  BPCTLI_CTRL_EXT_MCLK_DATA)
762  &
763  ~
764  (BPCTLI_CTRL_EXT_MDIO_DIR)));
765  else {
766 
767  BP10G_WRITE_REG(pbpctl_dev, EODSDP,
768  (ctrl_ext | BP10G_MCLK_DATA_OUT |
769  BP10G_MDIO_DATA_OUT));
770 
771  }
772  if (pbpctl_dev->bp_10g9) {
773  ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
774 
775  } else if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_i80)) {
776  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
777  } else if (pbpctl_dev->bp_540) {
778  ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
779  } else if (pbpctl_dev->bp_10gb)
780  ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
781 
782  else if (!pbpctl_dev->bp_10g)
783  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
784  else
785  ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
786 
787  usec_delay(PULSE_TIME);
788  if (pbpctl_dev->bp_10g9) {
789  if (ctrl_ext & BP10G_MDIO_DATA_IN9)
790  ctrl_val |= 1 << i;
791 
792  } else if (pbpctl_dev->bp_fiber5) {
793  if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA5)
794  ctrl_val |= 1 << i;
795  } else if (pbpctl_dev->bp_i80) {
796  if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA80)
797  ctrl_val |= 1 << i;
798  } else if (pbpctl_dev->bp_540) {
799  if (ctrl_ext & BP540_MDIO_DATA)
800  ctrl_val |= 1 << i;
801  } else if (pbpctl_dev->bp_10gb) {
802  if (ctrl_ext & BP10GB_MDIO_DATA)
803  ctrl_val |= 1 << i;
804 
805  } else if (!pbpctl_dev->bp_10g) {
806 
807  if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA)
808  ctrl_val |= 1 << i;
809  } else {
810 
811  if (ctrl_ext & BP10G_MDIO_DATA_IN)
812  ctrl_val |= 1 << i;
813  }
814 
815  }
816 
817  return ctrl_val;
818 }
819 
820 static void write_reg(bpctl_dev_t *pbpctl_dev, unsigned char value,
821  unsigned char addr)
822 {
823  uint32_t ctrl_ext = 0, ctrl = 0;
824  bpctl_dev_t *pbpctl_dev_c = NULL;
825  unsigned long flags;
826  if (pbpctl_dev->bp_10g9) {
827  if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
828  return;
829  }
830  if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
831  (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER))
832  wdt_time_left(pbpctl_dev);
833 
834 #ifdef BP_SYNC_FLAG
835  spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
836 #else
837  atomic_set(&pbpctl_dev->wdt_busy, 1);
838 #endif
839  if (pbpctl_dev->bp_10g9) {
840 
841  ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
842  ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
843  /* DATA 0 CLK 0 */
844  /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
845  BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
846  (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
847  BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
848  ((ctrl | BP10G_MCLK_DIR_OUT9) &
849  ~(BP10G_MCLK_DATA_OUT9)));
850 
851  } else if (pbpctl_dev->bp_fiber5) {
852  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
853  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
854  BPCTLI_CTRL_EXT_MCLK_DIR5
855  |
856  BPCTLI_CTRL_EXT_MDIO_DIR5)
857  &
858  ~
859  (BPCTLI_CTRL_EXT_MDIO_DATA5
860  |
861  BPCTLI_CTRL_EXT_MCLK_DATA5)));
862  } else if (pbpctl_dev->bp_i80) {
863  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
864  ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
865  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
866  BPCTLI_CTRL_EXT_MDIO_DIR80)
867  &
868  ~BPCTLI_CTRL_EXT_MDIO_DATA80));
869  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
870  ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
871  ~BPCTLI_CTRL_EXT_MCLK_DATA80));
872 
873  } else if (pbpctl_dev->bp_540) {
874  ctrl = ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
875  BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
876  BP540_MDIO_DIR |
877  BP540_MCLK_DIR) &
878  ~(BP540_MDIO_DATA |
879  BP540_MCLK_DATA)));
880 
881  } else if (pbpctl_dev->bp_10gb) {
882  ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
883 
884  BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
885  (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
886  & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
887  BP10GB_MDIO_SET | BP10GB_MCLK_SET));
888 
889  } else if (!pbpctl_dev->bp_10g) {
890 
891  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
892  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
893  BPCTLI_CTRL_EXT_MCLK_DIR
894  |
895  BPCTLI_CTRL_EXT_MDIO_DIR)
896  &
897  ~
898  (BPCTLI_CTRL_EXT_MDIO_DATA
899  |
900  BPCTLI_CTRL_EXT_MCLK_DATA)));
901  } else {
902  ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
903  ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
904  BP10G_WRITE_REG(pbpctl_dev, EODSDP,
905  (ctrl_ext &
906  ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
907  }
908  usec_delay(CMND_INTERVAL);
909 
910  /*send sync cmd */
911  write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
912  /*send wr cmd */
913  write_pulse(pbpctl_dev, ctrl_ext, WR_CMD_VAL, WR_CMD_LEN);
914  write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
915 
916  /*write data */
917  write_pulse(pbpctl_dev, ctrl_ext, value, WR_DATA_LEN);
918  if (pbpctl_dev->bp_10g9) {
919  /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
920  /* DATA 0 CLK 0 */
921  BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
922  (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
923  BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
924  ((ctrl | BP10G_MCLK_DIR_OUT9) &
925  ~(BP10G_MCLK_DATA_OUT9)));
926 
927  } else if (pbpctl_dev->bp_fiber5) {
928  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
929  BPCTLI_CTRL_EXT_MCLK_DIR5
930  |
931  BPCTLI_CTRL_EXT_MDIO_DIR5)
932  &
933  ~
934  (BPCTLI_CTRL_EXT_MDIO_DATA5
935  |
936  BPCTLI_CTRL_EXT_MCLK_DATA5)));
937  } else if (pbpctl_dev->bp_i80) {
938  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
939  BPCTLI_CTRL_EXT_MDIO_DIR80)
940  &
941  ~BPCTLI_CTRL_EXT_MDIO_DATA80));
942  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
943  ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
944  ~BPCTLI_CTRL_EXT_MCLK_DATA80));
945  } else if (pbpctl_dev->bp_540) {
946  BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
947  BP540_MDIO_DIR |
948  BP540_MCLK_DIR) &
949  ~(BP540_MDIO_DATA |
950  BP540_MCLK_DATA)));
951  } else if (pbpctl_dev->bp_10gb) {
952  BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
953  (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
954  & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
955  BP10GB_MDIO_SET | BP10GB_MCLK_SET));
956 
957  } else if (!pbpctl_dev->bp_10g)
958 
959  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
960  BPCTLI_CTRL_EXT_MCLK_DIR
961  |
962  BPCTLI_CTRL_EXT_MDIO_DIR)
963  &
964  ~
965  (BPCTLI_CTRL_EXT_MDIO_DATA
966  |
967  BPCTLI_CTRL_EXT_MCLK_DATA)));
968  else {
969  BP10G_WRITE_REG(pbpctl_dev, EODSDP,
970  (ctrl_ext &
971  ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
972 
973  }
974 
975  usec_delay(CMND_INTERVAL * 4);
976 
977  if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
978  (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER) && (addr == CMND_REG_ADDR))
979  pbpctl_dev->bypass_wdt_on_time = jiffies;
980 #ifdef BP_SYNC_FLAG
981  spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
982 #else
983  atomic_set(&pbpctl_dev->wdt_busy, 0);
984 #endif
985 
986 }
987 
988 static void write_data(bpctl_dev_t *pbpctl_dev, unsigned char value)
989 {
990  write_reg(pbpctl_dev, value, CMND_REG_ADDR);
991 }
992 
993 static int read_reg(bpctl_dev_t *pbpctl_dev, unsigned char addr)
994 {
995  uint32_t ctrl_ext = 0, ctrl = 0, ctrl_value = 0;
996  bpctl_dev_t *pbpctl_dev_c = NULL;
997 
998 #ifdef BP_SYNC_FLAG
999  unsigned long flags;
1000  spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1001 #else
1002  atomic_set(&pbpctl_dev->wdt_busy, 1);
1003 #endif
1004  if (pbpctl_dev->bp_10g9) {
1005  if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
1006  return -1;
1007  }
1008 
1009  if (pbpctl_dev->bp_10g9) {
1010  ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1011  ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1012 
1013  /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1014  /* DATA 0 CLK 0 */
1015  BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1016  (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1017  BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1018  ((ctrl | BP10G_MCLK_DIR_OUT9) &
1019  ~(BP10G_MCLK_DATA_OUT9)));
1020 
1021  } else if (pbpctl_dev->bp_fiber5) {
1022  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1023 
1024  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1025  BPCTLI_CTRL_EXT_MCLK_DIR5
1026  |
1027  BPCTLI_CTRL_EXT_MDIO_DIR5)
1028  &
1029  ~
1030  (BPCTLI_CTRL_EXT_MDIO_DATA5
1031  |
1032  BPCTLI_CTRL_EXT_MCLK_DATA5)));
1033  } else if (pbpctl_dev->bp_i80) {
1034  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1035  ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1036 
1037  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1038  BPCTLI_CTRL_EXT_MDIO_DIR80)
1039  &
1040  ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1041  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1042  ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1043  ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1044  } else if (pbpctl_dev->bp_540) {
1045  ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
1046  ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1047 
1048  BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1049  BP540_MDIO_DIR) &
1050  ~(BP540_MDIO_DATA |
1051  BP540_MCLK_DATA)));
1052  } else if (pbpctl_dev->bp_10gb) {
1053  ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1054 
1055  BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1056  (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1057  & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1058  BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1059 #if 0
1060 
1061  /*BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, (ctrl_ext | BP10GB_MCLK_DIR | BP10GB_MDIO_DIR|
1062  BP10GB_MCLK_CLR|BP10GB_MDIO_CLR));
1063  ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1064  printk("1reg=%x\n", ctrl_ext); */
1065 
1066  BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, ((ctrl_ext |
1067  BP10GB_MCLK_SET |
1068  BP10GB_MDIO_CLR))
1069  & ~(BP10GB_MCLK_CLR | BP10GB_MDIO_SET |
1070  BP10GB_MCLK_DIR | BP10GB_MDIO_DIR));
1071 
1072  /* bnx2x_set_spio(pbpctl_dev, 5, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1073  bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1074  bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_INPUT_HI_Z); */
1075 
1076  ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1077 
1078  printk("2reg=%x\n", ctrl_ext);
1079 
1080 #ifdef BP_SYNC_FLAG
1081  spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1082 #else
1083  atomic_set(&pbpctl_dev->wdt_busy, 0);
1084 #endif
1085 
1086  return 0;
1087 
1088 #endif
1089 
1090  } else if (!pbpctl_dev->bp_10g) {
1091 
1092  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1093 
1094  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1095  BPCTLI_CTRL_EXT_MCLK_DIR
1096  |
1097  BPCTLI_CTRL_EXT_MDIO_DIR)
1098  &
1099  ~
1100  (BPCTLI_CTRL_EXT_MDIO_DATA
1101  |
1102  BPCTLI_CTRL_EXT_MCLK_DATA)));
1103  } else {
1104 
1105  ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1106  ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1107  BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1108  (ctrl_ext &
1109  ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1110 
1111  }
1112 
1113  usec_delay(CMND_INTERVAL);
1114 
1115  /*send sync cmd */
1116  write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
1117  /*send rd cmd */
1118  write_pulse(pbpctl_dev, ctrl_ext, RD_CMD_VAL, RD_CMD_LEN);
1119  /*send addr */
1120  write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
1121  /*read data */
1122  /* zero */
1123  if (pbpctl_dev->bp_10g9) {
1124  /* DATA 0 CLK 1 */
1125  /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
1126  BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1127  (ctrl_ext | BP10G_MDIO_DATA_OUT9));
1128  BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1129  (ctrl | BP10G_MCLK_DATA_OUT9 |
1130  BP10G_MCLK_DIR_OUT9));
1131 
1132  } else if (pbpctl_dev->bp_fiber5) {
1133  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1134  BPCTLI_CTRL_EXT_MCLK_DIR5
1135  |
1136  BPCTLI_CTRL_EXT_MCLK_DATA5)
1137  &
1138  ~
1139  (BPCTLI_CTRL_EXT_MDIO_DIR5
1140  |
1141  BPCTLI_CTRL_EXT_MDIO_DATA5)));
1142 
1143  } else if (pbpctl_dev->bp_i80) {
1144  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
1145  (ctrl_ext &
1146  ~(BPCTLI_CTRL_EXT_MDIO_DATA80 |
1147  BPCTLI_CTRL_EXT_MDIO_DIR80)));
1148  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1149  (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1150  BPCTLI_CTRL_EXT_MCLK_DATA80));
1151 
1152  } else if (pbpctl_dev->bp_540) {
1153  BP10G_WRITE_REG(pbpctl_dev, ESDP,
1154  (((ctrl | BP540_MDIO_DIR | BP540_MCLK_DIR |
1155  BP540_MCLK_DATA) & ~BP540_MDIO_DATA)));
1156 
1157  } else if (pbpctl_dev->bp_10gb) {
1158 
1159  BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1160  (ctrl_ext | BP10GB_MDIO_DIR | BP10GB_MCLK_SET)
1161  & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_SET |
1162  BP10GB_MDIO_CLR | BP10GB_MCLK_CLR));
1163 
1164  } else if (!pbpctl_dev->bp_10g)
1165  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1166  BPCTLI_CTRL_EXT_MCLK_DIR
1167  |
1168  BPCTLI_CTRL_EXT_MCLK_DATA)
1169  &
1170  ~
1171  (BPCTLI_CTRL_EXT_MDIO_DIR
1172  |
1173  BPCTLI_CTRL_EXT_MDIO_DATA)));
1174  else {
1175 
1176  BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1177  (ctrl_ext | BP10G_MCLK_DATA_OUT |
1178  BP10G_MDIO_DATA_OUT));
1179 
1180 
1181  }
1182  usec_delay(PULSE_TIME);
1183 
1184  ctrl_value = read_pulse(pbpctl_dev, ctrl_ext, RD_DATA_LEN);
1185 
1186  if (pbpctl_dev->bp_10g9) {
1187  ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1188  ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1189 
1190  /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1191  /* DATA 0 CLK 0 */
1192  BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1193  (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1194  BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1195  ((ctrl | BP10G_MCLK_DIR_OUT9) &
1196  ~(BP10G_MCLK_DATA_OUT9)));
1197 
1198  } else if (pbpctl_dev->bp_fiber5) {
1199  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1200  BPCTLI_CTRL_EXT_MCLK_DIR5
1201  |
1202  BPCTLI_CTRL_EXT_MDIO_DIR5)
1203  &
1204  ~
1205  (BPCTLI_CTRL_EXT_MDIO_DATA5
1206  |
1207  BPCTLI_CTRL_EXT_MCLK_DATA5)));
1208  } else if (pbpctl_dev->bp_i80) {
1209  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1210  BPCTLI_CTRL_EXT_MDIO_DIR80)
1211  &
1212  ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1213  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1214  ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1215  ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1216 
1217  } else if (pbpctl_dev->bp_540) {
1218  ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1219  BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1220  BP540_MDIO_DIR) &
1221  ~(BP540_MDIO_DATA |
1222  BP540_MCLK_DATA)));
1223 
1224  } else if (pbpctl_dev->bp_10gb) {
1225  ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1226  BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1227  (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1228  & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1229  BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1230 
1231  } else if (!pbpctl_dev->bp_10g) {
1232  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1233  BPCTLI_CTRL_EXT_MCLK_DIR
1234  |
1235  BPCTLI_CTRL_EXT_MDIO_DIR)
1236  &
1237  ~
1238  (BPCTLI_CTRL_EXT_MDIO_DATA
1239  |
1240  BPCTLI_CTRL_EXT_MCLK_DATA)));
1241  } else {
1242 
1243  ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1244  ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1245  BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1246  (ctrl_ext &
1247  ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1248 
1249  }
1250 
1251  usec_delay(CMND_INTERVAL * 4);
1252 #ifdef BP_SYNC_FLAG
1253  spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1254 #else
1255  atomic_set(&pbpctl_dev->wdt_busy, 0);
1256 #endif
1257 
1258  return ctrl_value;
1259 }
1260 
1261 static int wdt_pulse(bpctl_dev_t *pbpctl_dev)
1262 {
1263  uint32_t ctrl_ext = 0, ctrl = 0;
1264  bpctl_dev_t *pbpctl_dev_c = NULL;
1265 
1266 #ifdef BP_SYNC_FLAG
1267  unsigned long flags;
1268 
1269  spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1270 #else
1271 
1272  if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1273  return -1;
1274 #endif
1275  if (pbpctl_dev->bp_10g9) {
1276  if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
1277  return -1;
1278  }
1279 
1280  if (pbpctl_dev->bp_10g9) {
1281  ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1282  ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1283 
1284  /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1285  /* DATA 0 CLK 0 */
1286  BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1287  (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1288  BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1289  ((ctrl | BP10G_MCLK_DIR_OUT9) &
1290  ~(BP10G_MCLK_DATA_OUT9)));
1291 
1292  } else if (pbpctl_dev->bp_fiber5) {
1293  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1294  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1295  BPCTLI_CTRL_EXT_MCLK_DIR5
1296  |
1297  BPCTLI_CTRL_EXT_MDIO_DIR5)
1298  &
1299  ~
1300  (BPCTLI_CTRL_EXT_MDIO_DATA5
1301  |
1302  BPCTLI_CTRL_EXT_MCLK_DATA5)));
1303  } else if (pbpctl_dev->bp_i80) {
1304  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1305  ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1306  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1307  BPCTLI_CTRL_EXT_MDIO_DIR80)
1308  &
1309  ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1310  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1311  ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1312  ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1313  } else if (pbpctl_dev->bp_540) {
1314  ctrl_ext = ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1315  BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1316  BP540_MDIO_DIR) &
1317  ~(BP540_MDIO_DATA |
1318  BP540_MCLK_DATA)));
1319  } else if (pbpctl_dev->bp_10gb) {
1320  ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1321  BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1322  (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1323  & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1324  BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1325 
1326  } else if (!pbpctl_dev->bp_10g) {
1327 
1328  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1329  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1330  BPCTLI_CTRL_EXT_MCLK_DIR
1331  |
1332  BPCTLI_CTRL_EXT_MDIO_DIR)
1333  &
1334  ~
1335  (BPCTLI_CTRL_EXT_MDIO_DATA
1336  |
1337  BPCTLI_CTRL_EXT_MCLK_DATA)));
1338  } else {
1339 
1340  ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1341  ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1342  BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1343  (ctrl_ext &
1344  ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1345 
1346  }
1347  if (pbpctl_dev->bp_10g9) {
1348  /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
1349  /* DATA 0 CLK 1 */
1350  BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1351  (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1352  BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1353  (ctrl | BP10G_MCLK_DATA_OUT9 |
1354  BP10G_MCLK_DIR_OUT9));
1355 
1356  } else if (pbpctl_dev->bp_fiber5) {
1357  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1358  BPCTLI_CTRL_EXT_MCLK_DIR5
1359  |
1360  BPCTLI_CTRL_EXT_MDIO_DIR5
1361  |
1362  BPCTLI_CTRL_EXT_MCLK_DATA5)
1363  &
1364  ~
1365  (BPCTLI_CTRL_EXT_MDIO_DATA5)));
1366  } else if (pbpctl_dev->bp_i80) {
1367  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1368  BPCTLI_CTRL_EXT_MDIO_DIR80)
1369  &
1370  ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1371  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1372  (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1373  BPCTLI_CTRL_EXT_MCLK_DATA80));
1374 
1375  } else if (pbpctl_dev->bp_540) {
1376  BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
1377  BP540_MDIO_DIR |
1378  BP540_MCLK_DIR |
1379  BP540_MCLK_DATA) &
1380  ~BP540_MDIO_DATA));
1381 
1382  } else if (pbpctl_dev->bp_10gb) {
1383  ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1384 
1385  BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1386  (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_SET)
1387  & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1388  BP10GB_MDIO_SET | BP10GB_MCLK_CLR));
1389 
1390  } else if (!pbpctl_dev->bp_10g)
1391  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1392  BPCTLI_CTRL_EXT_MCLK_DIR
1393  |
1394  BPCTLI_CTRL_EXT_MDIO_DIR
1395  |
1396  BPCTLI_CTRL_EXT_MCLK_DATA)
1397  &
1398  ~
1399  (BPCTLI_CTRL_EXT_MDIO_DATA)));
1400  else {
1401 
1402  BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1403  ((ctrl_ext | BP10G_MCLK_DATA_OUT) &
1404  ~BP10G_MDIO_DATA_OUT));
1405 
1406  }
1407 
1408  usec_delay(WDT_INTERVAL);
1409  if (pbpctl_dev->bp_10g9) {
1410  /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1411  /* DATA 0 CLK 0 */
1412  BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1413  (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1414  BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1415  ((ctrl | BP10G_MCLK_DIR_OUT9) &
1416  ~(BP10G_MCLK_DATA_OUT9)));
1417 
1418  } else if (pbpctl_dev->bp_fiber5) {
1419  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1420  BPCTLI_CTRL_EXT_MCLK_DIR5
1421  |
1422  BPCTLI_CTRL_EXT_MDIO_DIR5)
1423  &
1424  ~
1425  (BPCTLI_CTRL_EXT_MCLK_DATA5
1426  |
1427  BPCTLI_CTRL_EXT_MDIO_DATA5)));
1428  } else if (pbpctl_dev->bp_i80) {
1429  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1430  BPCTLI_CTRL_EXT_MDIO_DIR80)
1431  &
1432  ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1433  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1434  ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1435  ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1436 
1437  } else if (pbpctl_dev->bp_540) {
1438  BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1439  BP540_MDIO_DIR) &
1440  ~(BP540_MDIO_DATA |
1441  BP540_MCLK_DATA)));
1442 
1443  } else if (pbpctl_dev->bp_10gb) {
1444  ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1445  BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1446  (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1447  & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1448  BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1449 
1450  } else if (!pbpctl_dev->bp_10g)
1451  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1452  BPCTLI_CTRL_EXT_MCLK_DIR
1453  |
1454  BPCTLI_CTRL_EXT_MDIO_DIR)
1455  &
1456  ~
1457  (BPCTLI_CTRL_EXT_MCLK_DATA
1458  |
1459  BPCTLI_CTRL_EXT_MDIO_DATA)));
1460  else {
1461 
1462  BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1463  (ctrl_ext &
1464  ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1465  }
1466  if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) /*&&
1467  (pbpctl_dev->bp_ext_ver<PXG4BPFI_VER) */ )
1468  pbpctl_dev->bypass_wdt_on_time = jiffies;
1469 #ifdef BP_SYNC_FLAG
1470  spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1471 #endif
1472  usec_delay(CMND_INTERVAL * 4);
1473  return 0;
1474 }
1475 
1476 static void data_pulse(bpctl_dev_t *pbpctl_dev, unsigned char value)
1477 {
1478 
1479  uint32_t ctrl_ext = 0;
1480 #ifdef BP_SYNC_FLAG
1481  unsigned long flags;
1482 #endif
1483  wdt_time_left(pbpctl_dev);
1484 #ifdef BP_SYNC_FLAG
1485  spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1486 #else
1487  atomic_set(&pbpctl_dev->wdt_busy, 1);
1488 #endif
1489 
1490  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1491  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1492  BPCTLI_CTRL_EXT_SDP6_DIR |
1493  BPCTLI_CTRL_EXT_SDP7_DIR) &
1494  ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1495  BPCTLI_CTRL_EXT_SDP7_DATA)));
1496 
1497  usec_delay(INIT_CMND_INTERVAL);
1498  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1499  BPCTLI_CTRL_EXT_SDP6_DIR |
1500  BPCTLI_CTRL_EXT_SDP7_DIR |
1501  BPCTLI_CTRL_EXT_SDP6_DATA) &
1502  ~
1503  (BPCTLI_CTRL_EXT_SDP7_DATA)));
1504  usec_delay(INIT_CMND_INTERVAL);
1505 
1506  while (value) {
1507  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1508  BPCTLI_CTRL_EXT_SDP6_DIR |
1509  BPCTLI_CTRL_EXT_SDP7_DIR |
1510  BPCTLI_CTRL_EXT_SDP6_DATA |
1511  BPCTLI_CTRL_EXT_SDP7_DATA);
1512  usec_delay(PULSE_INTERVAL);
1513  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1514  BPCTLI_CTRL_EXT_SDP6_DIR
1515  |
1516  BPCTLI_CTRL_EXT_SDP7_DIR
1517  |
1518  BPCTLI_CTRL_EXT_SDP6_DATA)
1519  &
1520  ~BPCTLI_CTRL_EXT_SDP7_DATA));
1521  usec_delay(PULSE_INTERVAL);
1522  value--;
1523 
1524  }
1525  usec_delay(INIT_CMND_INTERVAL - PULSE_INTERVAL);
1526  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1527  BPCTLI_CTRL_EXT_SDP6_DIR |
1528  BPCTLI_CTRL_EXT_SDP7_DIR) &
1529  ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1530  BPCTLI_CTRL_EXT_SDP7_DATA)));
1531  usec_delay(WDT_TIME_CNT);
1532  if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1533  pbpctl_dev->bypass_wdt_on_time = jiffies;
1534 #ifdef BP_SYNC_FLAG
1535  spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1536 #else
1537  atomic_set(&pbpctl_dev->wdt_busy, 0);
1538 #endif
1539 
1540 }
1541 
1542 static int send_wdt_pulse(bpctl_dev_t *pbpctl_dev)
1543 {
1544  uint32_t ctrl_ext = 0;
1545 
1546 #ifdef BP_SYNC_FLAG
1547  unsigned long flags;
1548 
1549  spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1550 #else
1551 
1552  if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1553  return -1;
1554 #endif
1555  wdt_time_left(pbpctl_dev);
1556  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1557 
1558  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext | /* 1 */
1559  BPCTLI_CTRL_EXT_SDP7_DIR |
1560  BPCTLI_CTRL_EXT_SDP7_DATA);
1561  usec_delay(PULSE_INTERVAL);
1562  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1563  BPCTLI_CTRL_EXT_SDP7_DIR) &
1564  ~BPCTLI_CTRL_EXT_SDP7_DATA));
1565 
1566  usec_delay(PULSE_INTERVAL);
1567  if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1568  pbpctl_dev->bypass_wdt_on_time = jiffies;
1569 #ifdef BP_SYNC_FLAG
1570  spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1571 #endif
1572 
1573  return 0;
1574 }
1575 
1576 void send_bypass_clear_pulse(bpctl_dev_t *pbpctl_dev, unsigned int value)
1577 {
1578  uint32_t ctrl_ext = 0;
1579 
1580  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1581  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1582  BPCTLI_CTRL_EXT_SDP6_DIR) &
1583  ~BPCTLI_CTRL_EXT_SDP6_DATA));
1584 
1585  usec_delay(PULSE_INTERVAL);
1586  while (value) {
1587  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext | /* 1 */
1588  BPCTLI_CTRL_EXT_SDP6_DIR |
1589  BPCTLI_CTRL_EXT_SDP6_DATA);
1590  usec_delay(PULSE_INTERVAL);
1591  value--;
1592  }
1593  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1594  BPCTLI_CTRL_EXT_SDP6_DIR) &
1595  ~BPCTLI_CTRL_EXT_SDP6_DATA));
1596  usec_delay(PULSE_INTERVAL);
1597 }
1598 
1599 /* #endif OLD_FW */
1600 #ifdef BYPASS_DEBUG
1601 
1602 int pulse_set_fn(bpctl_dev_t *pbpctl_dev, unsigned int counter)
1603 {
1604  uint32_t ctrl_ext = 0;
1605 
1606  if (!pbpctl_dev)
1607  return -1;
1608 
1609  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1610  write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1611 
1612  pbpctl_dev->bypass_wdt_status = 0;
1613  if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1614  write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1615  } else {
1616  wdt_time_left(pbpctl_dev);
1617  if (pbpctl_dev->wdt_status == WDT_STATUS_EN) {
1618  pbpctl_dev->wdt_status = 0;
1619  data_pulse(pbpctl_dev, counter);
1620  pbpctl_dev->wdt_status = WDT_STATUS_EN;
1621  pbpctl_dev->bypass_wdt_on_time = jiffies;
1622 
1623  } else
1624  data_pulse(pbpctl_dev, counter);
1625  }
1626 
1627  return 0;
1628 }
1629 
1630 int zero_set_fn(bpctl_dev_t *pbpctl_dev)
1631 {
1632  uint32_t ctrl_ext = 0, ctrl_value = 0;
1633  if (!pbpctl_dev)
1634  return -1;
1635 
1636  if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1637  printk("zero_set");
1638 
1639  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1640 
1641  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1642  BPCTLI_CTRL_EXT_MCLK_DIR)
1643  &
1644  ~
1645  (BPCTLI_CTRL_EXT_MCLK_DATA
1646  |
1647  BPCTLI_CTRL_EXT_MDIO_DIR
1648  |
1649  BPCTLI_CTRL_EXT_MDIO_DATA)));
1650 
1651  }
1652  return ctrl_value;
1653 }
1654 
1655 int pulse_get2_fn(bpctl_dev_t *pbpctl_dev)
1656 {
1657  uint32_t ctrl_ext = 0, ctrl_value = 0;
1658  if (!pbpctl_dev)
1659  return -1;
1660 
1661  if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1662  printk("pulse_get_fn\n");
1663  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1664  ctrl_value = read_pulse_2(pbpctl_dev, ctrl_ext);
1665  printk("read:%d\n", ctrl_value);
1666  }
1667  return ctrl_value;
1668 }
1669 
1670 int pulse_get1_fn(bpctl_dev_t *pbpctl_dev)
1671 {
1672  uint32_t ctrl_ext = 0, ctrl_value = 0;
1673  if (!pbpctl_dev)
1674  return -1;
1675 
1676  if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1677 
1678  printk("pulse_get_fn\n");
1679 
1680  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1681  ctrl_value = read_pulse_1(pbpctl_dev, ctrl_ext);
1682  printk("read:%d\n", ctrl_value);
1683  }
1684  return ctrl_value;
1685 }
1686 
1687 int gpio6_set_fn(bpctl_dev_t *pbpctl_dev)
1688 {
1689  uint32_t ctrl_ext = 0;
1690 
1691  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1692  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1693  BPCTLI_CTRL_EXT_SDP6_DIR |
1694  BPCTLI_CTRL_EXT_SDP6_DATA);
1695  return 0;
1696 }
1697 
1698 int gpio7_set_fn(bpctl_dev_t *pbpctl_dev)
1699 {
1700  uint32_t ctrl_ext = 0;
1701 
1702  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1703  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1704  BPCTLI_CTRL_EXT_SDP7_DIR |
1705  BPCTLI_CTRL_EXT_SDP7_DATA);
1706  return 0;
1707 }
1708 
1709 int gpio7_clear_fn(bpctl_dev_t *pbpctl_dev)
1710 {
1711  uint32_t ctrl_ext = 0;
1712 
1713  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1714  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1715  BPCTLI_CTRL_EXT_SDP7_DIR) &
1716  ~BPCTLI_CTRL_EXT_SDP7_DATA));
1717  return 0;
1718 }
1719 
1720 int gpio6_clear_fn(bpctl_dev_t *pbpctl_dev)
1721 {
1722  uint32_t ctrl_ext = 0;
1723 
1724  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1725  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1726  BPCTLI_CTRL_EXT_SDP6_DIR) &
1727  ~BPCTLI_CTRL_EXT_SDP6_DATA));
1728  return 0;
1729 }
1730 #endif /*BYPASS_DEBUG */
1731 
1732 static bpctl_dev_t *get_status_port_fn(bpctl_dev_t *pbpctl_dev)
1733 {
1734  int idx_dev = 0;
1735 
1736  if (pbpctl_dev == NULL)
1737  return NULL;
1738 
1739  if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) {
1740  for (idx_dev = 0;
1741  ((bpctl_dev_arr[idx_dev].pdev != NULL)
1742  && (idx_dev < device_num)); idx_dev++) {
1743  if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus)
1744  && (bpctl_dev_arr[idx_dev].slot == pbpctl_dev->slot)
1745  && ((bpctl_dev_arr[idx_dev].func == 1)
1746  && (pbpctl_dev->func == 0))) {
1747 
1748  return &(bpctl_dev_arr[idx_dev]);
1749  }
1750  if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus) &&
1751  (bpctl_dev_arr[idx_dev].slot == pbpctl_dev->slot) &&
1752  ((bpctl_dev_arr[idx_dev].func == 3)
1753  && (pbpctl_dev->func == 2))) {
1754 
1755  return &(bpctl_dev_arr[idx_dev]);
1756  }
1757  }
1758  }
1759  return NULL;
1760 }
1761 
1762 static bpctl_dev_t *get_master_port_fn(bpctl_dev_t *pbpctl_dev)
1763 {
1764  int idx_dev = 0;
1765 
1766  if (pbpctl_dev == NULL)
1767  return NULL;
1768 
1769  if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3)) {
1770  for (idx_dev = 0;
1771  ((bpctl_dev_arr[idx_dev].pdev != NULL)
1772  && (idx_dev < device_num)); idx_dev++) {
1773  if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus)
1774  && (bpctl_dev_arr[idx_dev].slot == pbpctl_dev->slot)
1775  && ((bpctl_dev_arr[idx_dev].func == 0)
1776  && (pbpctl_dev->func == 1))) {
1777 
1778  return &(bpctl_dev_arr[idx_dev]);
1779  }
1780  if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus) &&
1781  (bpctl_dev_arr[idx_dev].slot == pbpctl_dev->slot) &&
1782  ((bpctl_dev_arr[idx_dev].func == 2)
1783  && (pbpctl_dev->func == 3))) {
1784 
1785  return &(bpctl_dev_arr[idx_dev]);
1786  }
1787  }
1788  }
1789  return NULL;
1790 }
1791 
1792 /**************************************/
1793 /**************INTEL API***************/
1794 /**************************************/
1795 
1796 static void write_data_port_int(bpctl_dev_t *pbpctl_dev,
1797  unsigned char ctrl_value)
1798 {
1799  uint32_t value;
1800 
1801  value = BPCTL_READ_REG(pbpctl_dev, CTRL);
1802 /* Make SDP0 Pin Directonality to Output */
1803  value |= BPCTLI_CTRL_SDP0_DIR;
1804  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1805 
1806  value &= ~BPCTLI_CTRL_SDP0_DATA;
1807  value |= ((ctrl_value & 0x1) << BPCTLI_CTRL_SDP0_SHIFT);
1808  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1809 
1810  value = (BPCTL_READ_REG(pbpctl_dev, CTRL_EXT));
1811 /* Make SDP2 Pin Directonality to Output */
1812  value |= BPCTLI_CTRL_EXT_SDP6_DIR;
1813  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1814 
1815  value &= ~BPCTLI_CTRL_EXT_SDP6_DATA;
1816  value |= (((ctrl_value & 0x2) >> 1) << BPCTLI_CTRL_EXT_SDP6_SHIFT);
1817  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1818 
1819 }
1820 
1821 static int write_data_int(bpctl_dev_t *pbpctl_dev, unsigned char value)
1822 {
1823  bpctl_dev_t *pbpctl_dev_b = NULL;
1824 
1825  if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
1826  return -1;
1827  atomic_set(&pbpctl_dev->wdt_busy, 1);
1828  write_data_port_int(pbpctl_dev, value & 0x3);
1829  write_data_port_int(pbpctl_dev_b, ((value & 0xc) >> 2));
1830  atomic_set(&pbpctl_dev->wdt_busy, 0);
1831 
1832  return 0;
1833 }
1834 
1835 static int wdt_pulse_int(bpctl_dev_t *pbpctl_dev)
1836 {
1837 
1838  if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1839  return -1;
1840 
1841  if ((write_data_int(pbpctl_dev, RESET_WDT_INT)) < 0)
1842  return -1;
1843  msec_delay_bp(CMND_INTERVAL_INT);
1844  if ((write_data_int(pbpctl_dev, CMND_OFF_INT)) < 0)
1845  return -1;
1846  msec_delay_bp(CMND_INTERVAL_INT);
1847 
1848  if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1849  pbpctl_dev->bypass_wdt_on_time = jiffies;
1850 
1851  return 0;
1852 }
1853 
1854 /*************************************/
1855 /************* COMMANDS **************/
1856 /*************************************/
1857 
1858 /* CMND_ON 0x4 (100)*/
1859 int cmnd_on(bpctl_dev_t *pbpctl_dev)
1860 {
1861  int ret = BP_NOT_CAP;
1862 
1863  if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1864  if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
1865  return 0;
1866  if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1867  write_data(pbpctl_dev, CMND_ON);
1868  else
1869  data_pulse(pbpctl_dev, CMND_ON);
1870  ret = 0;
1871  }
1872  return ret;
1873 }
1874 
1875 /* CMND_OFF 0x2 (10)*/
1876 int cmnd_off(bpctl_dev_t *pbpctl_dev)
1877 {
1878  int ret = BP_NOT_CAP;
1879 
1880  if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1881  if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1882  write_data_int(pbpctl_dev, CMND_OFF_INT);
1883  msec_delay_bp(CMND_INTERVAL_INT);
1884  } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1885  write_data(pbpctl_dev, CMND_OFF);
1886  else
1887  data_pulse(pbpctl_dev, CMND_OFF);
1888  ret = 0;
1889  };
1890  return ret;
1891 }
1892 
1893 /* BYPASS_ON (0xa)*/
1894 int bypass_on(bpctl_dev_t *pbpctl_dev)
1895 {
1896  int ret = BP_NOT_CAP;
1897 
1898  if (pbpctl_dev->bp_caps & BP_CAP) {
1899  if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1900  write_data_int(pbpctl_dev, BYPASS_ON_INT);
1901  msec_delay_bp(BYPASS_DELAY_INT);
1902  pbpctl_dev->bp_status_un = 0;
1903  } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1904  write_data(pbpctl_dev, BYPASS_ON);
1905  if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1906  msec_delay_bp(LATCH_DELAY);
1907  } else
1908  data_pulse(pbpctl_dev, BYPASS_ON);
1909  ret = 0;
1910  };
1911  return ret;
1912 }
1913 
1914 /* BYPASS_OFF (0x8 111)*/
1915 int bypass_off(bpctl_dev_t *pbpctl_dev)
1916 {
1917  int ret = BP_NOT_CAP;
1918 
1919  if (pbpctl_dev->bp_caps & BP_CAP) {
1920  if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1921  write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
1922  msec_delay_bp(BYPASS_DELAY_INT);
1923  write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
1924  msec_delay_bp(BYPASS_DELAY_INT);
1925  pbpctl_dev->bp_status_un = 0;
1926  } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1927  write_data(pbpctl_dev, BYPASS_OFF);
1928  if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1929  msec_delay_bp(LATCH_DELAY);
1930  } else
1931  data_pulse(pbpctl_dev, BYPASS_OFF);
1932  ret = 0;
1933  }
1934  return ret;
1935 }
1936 
1937 /* TAP_OFF (0x9)*/
1938 int tap_off(bpctl_dev_t *pbpctl_dev)
1939 {
1940  int ret = BP_NOT_CAP;
1941  if ((pbpctl_dev->bp_caps & TAP_CAP)
1942  && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
1943  write_data(pbpctl_dev, TAP_OFF);
1944  msec_delay_bp(LATCH_DELAY);
1945  ret = 0;
1946  };
1947  return ret;
1948 }
1949 
1950 /* TAP_ON (0xb)*/
1951 int tap_on(bpctl_dev_t *pbpctl_dev)
1952 {
1953  int ret = BP_NOT_CAP;
1954  if ((pbpctl_dev->bp_caps & TAP_CAP)
1955  && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
1956  write_data(pbpctl_dev, TAP_ON);
1957  msec_delay_bp(LATCH_DELAY);
1958  ret = 0;
1959  };
1960  return ret;
1961 }
1962 
1963 /* DISC_OFF (0x9)*/
1964 int disc_off(bpctl_dev_t *pbpctl_dev)
1965 {
1966  int ret = 0;
1967  if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
1968  write_data(pbpctl_dev, DISC_OFF);
1969  msec_delay_bp(LATCH_DELAY);
1970  } else
1971  ret = BP_NOT_CAP;
1972  return ret;
1973 }
1974 
1975 /* DISC_ON (0xb)*/
1976 int disc_on(bpctl_dev_t *pbpctl_dev)
1977 {
1978  int ret = 0;
1979  if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
1980  write_data(pbpctl_dev, /*DISC_ON */ 0x85);
1981  msec_delay_bp(LATCH_DELAY);
1982  } else
1983  ret = BP_NOT_CAP;
1984  return ret;
1985 }
1986 
1987 /* DISC_PORT_ON */
1988 int disc_port_on(bpctl_dev_t *pbpctl_dev)
1989 {
1990  int ret = 0;
1991  bpctl_dev_t *pbpctl_dev_m;
1992 
1993  if ((is_bypass_fn(pbpctl_dev)) == 1)
1994  pbpctl_dev_m = pbpctl_dev;
1995  else
1996  pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
1997  if (pbpctl_dev_m == NULL)
1998  return BP_NOT_CAP;
1999 
2000  if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2001  if (is_bypass_fn(pbpctl_dev) == 1) {
2002 
2003  write_data(pbpctl_dev_m, TX_DISA);
2004  } else {
2005 
2006  write_data(pbpctl_dev_m, TX_DISB);
2007  }
2008 
2009  msec_delay_bp(LATCH_DELAY);
2010 
2011  }
2012  return ret;
2013 }
2014 
2015 /* DISC_PORT_OFF */
2016 int disc_port_off(bpctl_dev_t *pbpctl_dev)
2017 {
2018  int ret = 0;
2019  bpctl_dev_t *pbpctl_dev_m;
2020 
2021  if ((is_bypass_fn(pbpctl_dev)) == 1)
2022  pbpctl_dev_m = pbpctl_dev;
2023  else
2024  pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2025  if (pbpctl_dev_m == NULL)
2026  return BP_NOT_CAP;
2027 
2028  if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2029  if (is_bypass_fn(pbpctl_dev) == 1)
2030  write_data(pbpctl_dev_m, TX_ENA);
2031  else
2032  write_data(pbpctl_dev_m, TX_ENB);
2033 
2034  msec_delay_bp(LATCH_DELAY);
2035 
2036  }
2037  return ret;
2038 }
2039 
2040 /*TWO_PORT_LINK_HW_EN (0xe)*/
2041 int tpl_hw_on(bpctl_dev_t *pbpctl_dev)
2042 {
2043  int ret = 0, ctrl = 0;
2044  bpctl_dev_t *pbpctl_dev_b = NULL;
2045 
2046  if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
2047  return BP_NOT_CAP;
2048 
2049  if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
2050  cmnd_on(pbpctl_dev);
2051  write_data(pbpctl_dev, TPL2_ON);
2052  msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2053  cmnd_off(pbpctl_dev);
2054  return ret;
2055  }
2056 
2057  if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
2058  ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
2059  BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
2060  ((ctrl | BPCTLI_CTRL_SWDPIO0) &
2061  ~BPCTLI_CTRL_SWDPIN0));
2062  } else
2063  ret = BP_NOT_CAP;
2064  return ret;
2065 }
2066 
2067 /*TWO_PORT_LINK_HW_DIS (0xc)*/
2068 int tpl_hw_off(bpctl_dev_t *pbpctl_dev)
2069 {
2070  int ret = 0, ctrl = 0;
2071  bpctl_dev_t *pbpctl_dev_b = NULL;
2072 
2073  if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
2074  return BP_NOT_CAP;
2075  if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
2076  cmnd_on(pbpctl_dev);
2077  write_data(pbpctl_dev, TPL2_OFF);
2078  msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2079  cmnd_off(pbpctl_dev);
2080  return ret;
2081  }
2082  if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
2083  ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
2084  BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
2085  (ctrl | BPCTLI_CTRL_SWDPIO0 |
2086  BPCTLI_CTRL_SWDPIN0));
2087  } else
2088  ret = BP_NOT_CAP;
2089  return ret;
2090 }
2091 
2092 /* WDT_OFF (0x6 110)*/
2093 int wdt_off(bpctl_dev_t *pbpctl_dev)
2094 {
2095  int ret = BP_NOT_CAP;
2096 
2097  if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2098  if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2099  bypass_off(pbpctl_dev);
2100  } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2101  write_data(pbpctl_dev, WDT_OFF);
2102  else
2103  data_pulse(pbpctl_dev, WDT_OFF);
2104  pbpctl_dev->wdt_status = WDT_STATUS_DIS;
2105  ret = 0;
2106  };
2107  return ret;
2108 }
2109 
2110 /* WDT_ON (0x10)*/
2111 
2112 /***Global***/
2113 static unsigned int
2114  wdt_val_array[] = { 1000, 1500, 2000, 3000, 4000, 8000, 16000, 32000, 0 };
2115 
2116 int wdt_on(bpctl_dev_t *pbpctl_dev, unsigned int timeout)
2117 {
2118 
2119  if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2120  unsigned int pulse = 0, temp_value = 0, temp_cnt = 0;
2121  pbpctl_dev->wdt_status = 0;
2122 
2123  if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2124  for (; wdt_val_array[temp_cnt]; temp_cnt++)
2125  if (timeout <= wdt_val_array[temp_cnt])
2126  break;
2127 
2128  if (!wdt_val_array[temp_cnt])
2129  temp_cnt--;
2130 
2131  timeout = wdt_val_array[temp_cnt];
2132  temp_cnt += 0x7;
2133 
2134  write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2135  msec_delay_bp(BYPASS_DELAY_INT);
2136  pbpctl_dev->bp_status_un = 0;
2137  write_data_int(pbpctl_dev, temp_cnt);
2138  pbpctl_dev->bypass_wdt_on_time = jiffies;
2139  msec_delay_bp(CMND_INTERVAL_INT);
2140  pbpctl_dev->bypass_timer_interval = timeout;
2141  } else {
2142  timeout =
2143  (timeout <
2144  TIMEOUT_UNIT ? TIMEOUT_UNIT : (timeout >
2145  WDT_TIMEOUT_MAX ?
2146  WDT_TIMEOUT_MAX :
2147  timeout));
2148  temp_value = timeout / 100;
2149  while ((temp_value >>= 1))
2150  temp_cnt++;
2151  if (timeout > ((1 << temp_cnt) * 100))
2152  temp_cnt++;
2153  pbpctl_dev->bypass_wdt_on_time = jiffies;
2154  pulse = (WDT_ON | temp_cnt);
2155  if (pbpctl_dev->bp_ext_ver == OLD_IF_VER)
2156  data_pulse(pbpctl_dev, pulse);
2157  else
2158  write_data(pbpctl_dev, pulse);
2159  pbpctl_dev->bypass_timer_interval =
2160  (1 << temp_cnt) * 100;
2161  }
2162  pbpctl_dev->wdt_status = WDT_STATUS_EN;
2163  return 0;
2164  }
2165  return BP_NOT_CAP;
2166 }
2167 
2168 void bp75_put_hw_semaphore_generic(bpctl_dev_t *pbpctl_dev)
2169 {
2170  u32 swsm;
2171 
2172  swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2173 
2174  swsm &= ~(BPCTLI_SWSM_SMBI | BPCTLI_SWSM_SWESMBI);
2175 
2176  BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm);
2177 }
2178 
2179 s32 bp75_get_hw_semaphore_generic(bpctl_dev_t *pbpctl_dev)
2180 {
2181  u32 swsm;
2182  s32 ret_val = 0;
2183  s32 timeout = 8192 + 1;
2184  s32 i = 0;
2185 
2186  /* Get the SW semaphore */
2187  while (i < timeout) {
2188  swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2189  if (!(swsm & BPCTLI_SWSM_SMBI))
2190  break;
2191 
2192  usec_delay(50);
2193  i++;
2194  }
2195 
2196  if (i == timeout) {
2197  printk
2198  ("bpctl_mod: Driver can't access device - SMBI bit is set.\n");
2199  ret_val = -1;
2200  goto out;
2201  }
2202 
2203  /* Get the FW semaphore. */
2204  for (i = 0; i < timeout; i++) {
2205  swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2206  BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm | BPCTLI_SWSM_SWESMBI);
2207 
2208  /* Semaphore acquired if bit latched */
2209  if (BPCTL_READ_REG(pbpctl_dev, SWSM) & BPCTLI_SWSM_SWESMBI)
2210  break;
2211 
2212  usec_delay(50);
2213  }
2214 
2215  if (i == timeout) {
2216  /* Release semaphores */
2217  bp75_put_hw_semaphore_generic(pbpctl_dev);
2218  printk("bpctl_mod: Driver can't access the NVM\n");
2219  ret_val = -1;
2220  goto out;
2221  }
2222 
2223  out:
2224  return ret_val;
2225 }
2226 
2227 static void bp75_release_phy(bpctl_dev_t *pbpctl_dev)
2228 {
2229  u16 mask = BPCTLI_SWFW_PHY0_SM;
2230  u32 swfw_sync;
2231 
2232  if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2233  mask = BPCTLI_SWFW_PHY1_SM;
2234 
2235  while (bp75_get_hw_semaphore_generic(pbpctl_dev) != 0) ;
2236  /* Empty */
2237 
2238  swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2239  swfw_sync &= ~mask;
2240  BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2241 
2242  bp75_put_hw_semaphore_generic(pbpctl_dev);
2243 }
2244 
2245 static s32 bp75_acquire_phy(bpctl_dev_t *pbpctl_dev)
2246 {
2247  u16 mask = BPCTLI_SWFW_PHY0_SM;
2248  u32 swfw_sync;
2249  u32 swmask;
2250  u32 fwmask;
2251  s32 ret_val = 0;
2252  s32 i = 0, timeout = 200;
2253 
2254  if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2255  mask = BPCTLI_SWFW_PHY1_SM;
2256 
2257  swmask = mask;
2258  fwmask = mask << 16;
2259 
2260  while (i < timeout) {
2261  if (bp75_get_hw_semaphore_generic(pbpctl_dev)) {
2262  ret_val = -1;
2263  goto out;
2264  }
2265 
2266  swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2267  if (!(swfw_sync & (fwmask | swmask)))
2268  break;
2269 
2270  bp75_put_hw_semaphore_generic(pbpctl_dev);
2271  mdelay(5);
2272  i++;
2273  }
2274 
2275  if (i == timeout) {
2276  printk
2277  ("bpctl_mod: Driver can't access resource, SW_FW_SYNC timeout.\n");
2278  ret_val = -1;
2279  goto out;
2280  }
2281 
2282  swfw_sync |= swmask;
2283  BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2284 
2285  bp75_put_hw_semaphore_generic(pbpctl_dev);
2286 
2287  out:
2288  return ret_val;
2289 }
2290 
2291 s32 bp75_read_phy_reg_mdic(bpctl_dev_t *pbpctl_dev, u32 offset, u16 *data)
2292 {
2293  u32 i, mdic = 0;
2294  s32 ret_val = 0;
2295  u32 phy_addr = 1;
2296 
2297  mdic = ((offset << BPCTLI_MDIC_REG_SHIFT) |
2298  (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_READ));
2299 
2300  BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2301 
2302  for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2303  usec_delay(50);
2304  mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2305  if (mdic & BPCTLI_MDIC_READY)
2306  break;
2307  }
2308  if (!(mdic & BPCTLI_MDIC_READY)) {
2309  printk("bpctl_mod: MDI Read did not complete\n");
2310  ret_val = -1;
2311  goto out;
2312  }
2313  if (mdic & BPCTLI_MDIC_ERROR) {
2314  printk("bpctl_mod: MDI Error\n");
2315  ret_val = -1;
2316  goto out;
2317  }
2318  *data = (u16) mdic;
2319 
2320  out:
2321  return ret_val;
2322 }
2323 
2324 s32 bp75_write_phy_reg_mdic(bpctl_dev_t *pbpctl_dev, u32 offset, u16 data)
2325 {
2326  u32 i, mdic = 0;
2327  s32 ret_val = 0;
2328  u32 phy_addr = 1;
2329 
2330  mdic = (((u32) data) |
2331  (offset << BPCTLI_MDIC_REG_SHIFT) |
2332  (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_WRITE));
2333 
2334  BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2335 
2336  for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2337  usec_delay(50);
2338  mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2339  if (mdic & BPCTLI_MDIC_READY)
2340  break;
2341  }
2342  if (!(mdic & BPCTLI_MDIC_READY)) {
2343  printk("bpctl_mod: MDI Write did not complete\n");
2344  ret_val = -1;
2345  goto out;
2346  }
2347  if (mdic & BPCTLI_MDIC_ERROR) {
2348  printk("bpctl_mod: MDI Error\n");
2349  ret_val = -1;
2350  goto out;
2351  }
2352 
2353  out:
2354  return ret_val;
2355 }
2356 
2357 static s32 bp75_read_phy_reg(bpctl_dev_t *pbpctl_dev, u32 offset, u16 *data)
2358 {
2359  s32 ret_val = 0;
2360 
2361  ret_val = bp75_acquire_phy(pbpctl_dev);
2362  if (ret_val)
2363  goto out;
2364 
2365  if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2366  ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2367  BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2368  (u16) offset);
2369  if (ret_val)
2370  goto release;
2371  }
2372 
2373  ret_val =
2374  bp75_read_phy_reg_mdic(pbpctl_dev,
2375  BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2376 
2377  release:
2378  bp75_release_phy(pbpctl_dev);
2379  out:
2380  return ret_val;
2381 }
2382 
2383 static s32 bp75_write_phy_reg(bpctl_dev_t *pbpctl_dev, u32 offset, u16 data)
2384 {
2385  s32 ret_val = 0;
2386 
2387  ret_val = bp75_acquire_phy(pbpctl_dev);
2388  if (ret_val)
2389  goto out;
2390 
2391  if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2392  ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2393  BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2394  (u16) offset);
2395  if (ret_val)
2396  goto release;
2397  }
2398 
2399  ret_val =
2400  bp75_write_phy_reg_mdic(pbpctl_dev,
2401  BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2402 
2403  release:
2404  bp75_release_phy(pbpctl_dev);
2405 
2406  out:
2407  return ret_val;
2408 }
2409 
2410 /* SET_TX (non-Bypass command :)) */
2411 static int set_tx(bpctl_dev_t *pbpctl_dev, int tx_state)
2412 {
2413  int ret = 0, ctrl = 0;
2414  bpctl_dev_t *pbpctl_dev_m;
2415  if ((is_bypass_fn(pbpctl_dev)) == 1)
2416  pbpctl_dev_m = pbpctl_dev;
2417  else
2418  pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2419  if (pbpctl_dev_m == NULL)
2420  return BP_NOT_CAP;
2421  if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2422  ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2423  if (!tx_state) {
2424  if (pbpctl_dev->bp_540) {
2425  ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2426  BP10G_WRITE_REG(pbpctl_dev, ESDP,
2427  (ctrl | BP10G_SDP1_DIR |
2428  BP10G_SDP1_DATA));
2429 
2430  } else {
2431  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2432  (ctrl | BPCTLI_CTRL_SDP1_DIR
2433  | BPCTLI_CTRL_SWDPIN1));
2434  }
2435  } else {
2436  if (pbpctl_dev->bp_540) {
2437  ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2438  BP10G_WRITE_REG(pbpctl_dev, ESDP,
2439  ((ctrl | BP10G_SDP1_DIR) &
2440  ~BP10G_SDP1_DATA));
2441  } else {
2442  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2443  ((ctrl |
2444  BPCTLI_CTRL_SDP1_DIR) &
2445  ~BPCTLI_CTRL_SWDPIN1));
2446  }
2447  return ret;
2448 
2449  }
2450  } else if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
2451  if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
2452  if (tx_state) {
2453  uint16_t mii_reg;
2454  if (!
2455  (ret =
2456  bp75_read_phy_reg(pbpctl_dev,
2457  BPCTLI_PHY_CONTROL,
2458  &mii_reg))) {
2459  if (mii_reg & BPCTLI_MII_CR_POWER_DOWN) {
2460  ret =
2461  bp75_write_phy_reg
2462  (pbpctl_dev,
2463  BPCTLI_PHY_CONTROL,
2464  mii_reg &
2465  ~BPCTLI_MII_CR_POWER_DOWN);
2466  }
2467  }
2468  } else {
2469  uint16_t mii_reg;
2470  if (!
2471  (ret =
2472  bp75_read_phy_reg(pbpctl_dev,
2473  BPCTLI_PHY_CONTROL,
2474  &mii_reg))) {
2475 
2476  mii_reg |= BPCTLI_MII_CR_POWER_DOWN;
2477  ret =
2478  bp75_write_phy_reg(pbpctl_dev,
2479  BPCTLI_PHY_CONTROL,
2480  mii_reg);
2481  }
2482  }
2483 
2484  }
2485  if (pbpctl_dev->bp_fiber5) {
2486  ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
2487 
2488  } else if (pbpctl_dev->bp_10gb)
2489  ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
2490 
2491  else if (!pbpctl_dev->bp_10g)
2492  ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2493  else
2494  ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2495 
2496  if (!tx_state)
2497  if (pbpctl_dev->bp_10g9) {
2498  BP10G_WRITE_REG(pbpctl_dev, ESDP,
2499  (ctrl | BP10G_SDP3_DATA |
2500  BP10G_SDP3_DIR));
2501 
2502  } else if (pbpctl_dev->bp_fiber5) {
2503  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2504  (ctrl |
2505  BPCTLI_CTRL_EXT_SDP6_DIR |
2506  BPCTLI_CTRL_EXT_SDP6_DATA));
2507 
2508  } else if (pbpctl_dev->bp_10gb) {
2509  if ((pbpctl_dev->func == 1)
2510  || (pbpctl_dev->func == 3))
2511  BP10GB_WRITE_REG(pbpctl_dev,
2512  MISC_REG_GPIO,
2513  (ctrl |
2514  BP10GB_GPIO0_SET_P1) &
2515  ~(BP10GB_GPIO0_CLR_P1 |
2516  BP10GB_GPIO0_OE_P1));
2517  else
2518  BP10GB_WRITE_REG(pbpctl_dev,
2519  MISC_REG_GPIO,
2520  (ctrl |
2521  BP10GB_GPIO0_OE_P0 |
2522  BP10GB_GPIO0_SET_P0));
2523 
2524  } else if (pbpctl_dev->bp_i80) {
2525  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2526  (ctrl | BPCTLI_CTRL_SDP1_DIR
2527  | BPCTLI_CTRL_SWDPIN1));
2528 
2529  } else if (pbpctl_dev->bp_540) {
2530  ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2531  BP10G_WRITE_REG(pbpctl_dev, ESDP,
2532  (ctrl | BP10G_SDP1_DIR |
2533  BP10G_SDP1_DATA));
2534 
2535  }
2536 
2537  else if (!pbpctl_dev->bp_10g)
2538  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2539  (ctrl | BPCTLI_CTRL_SWDPIO0 |
2540  BPCTLI_CTRL_SWDPIN0));
2541 
2542  else
2543  BP10G_WRITE_REG(pbpctl_dev, ESDP,
2544  (ctrl | BP10G_SDP0_DATA |
2545  BP10G_SDP0_DIR));
2546 
2547  else {
2548  if (pbpctl_dev->bp_10g9) {
2549  BP10G_WRITE_REG(pbpctl_dev, ESDP,
2550  ((ctrl | BP10G_SDP3_DIR) &
2551  ~BP10G_SDP3_DATA));
2552 
2553  } else if (pbpctl_dev->bp_fiber5) {
2554  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2555  ((ctrl |
2556  BPCTLI_CTRL_EXT_SDP6_DIR) &
2557  ~BPCTLI_CTRL_EXT_SDP6_DATA));
2558 
2559  } else if (pbpctl_dev->bp_10gb) {
2560  if ((bpctl_dev_arr->func == 1)
2561  || (bpctl_dev_arr->func == 3))
2562  BP10GB_WRITE_REG(pbpctl_dev,
2563  MISC_REG_GPIO,
2564  (ctrl |
2565  BP10GB_GPIO0_CLR_P1) &
2566  ~(BP10GB_GPIO0_SET_P1 |
2567  BP10GB_GPIO0_OE_P1));
2568  else
2569  BP10GB_WRITE_REG(pbpctl_dev,
2570  MISC_REG_GPIO,
2571  (ctrl |
2572  BP10GB_GPIO0_OE_P0 |
2573  BP10GB_GPIO0_CLR_P0));
2574 
2575  } else if (pbpctl_dev->bp_i80) {
2576  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2577  ((ctrl |
2578  BPCTLI_CTRL_SDP1_DIR) &
2579  ~BPCTLI_CTRL_SWDPIN1));
2580  } else if (pbpctl_dev->bp_540) {
2581  ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2582  BP10G_WRITE_REG(pbpctl_dev, ESDP,
2583  ((ctrl | BP10G_SDP1_DIR) &
2584  ~BP10G_SDP1_DATA));
2585  }
2586 
2587  else if (!pbpctl_dev->bp_10g) {
2588  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2589  ((ctrl | BPCTLI_CTRL_SWDPIO0)
2590  & ~BPCTLI_CTRL_SWDPIN0));
2591  if (!PEGF_IF_SERIES(pbpctl_dev->subdevice)) {
2592  BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2593  (ctrl &
2594  ~
2595  (BPCTLI_CTRL_SDP0_DATA
2596  |
2597  BPCTLI_CTRL_SDP0_DIR)));
2598  }
2599  } else
2600  BP10G_WRITE_REG(pbpctl_dev, ESDP,
2601  ((ctrl | BP10G_SDP0_DIR) &
2602  ~BP10G_SDP0_DATA));
2603 
2604  }
2605 
2606  } else
2607  ret = BP_NOT_CAP;
2608  return ret;
2609 
2610 }
2611 
2612 /* SET_FORCE_LINK (non-Bypass command :)) */
2613 static int set_bp_force_link(bpctl_dev_t *pbpctl_dev, int tx_state)
2614 {
2615  int ret = 0, ctrl = 0;
2616 
2617  if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
2618 
2619  if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
2620 
2621  ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2622  if (!tx_state)
2623  BP10G_WRITE_REG(pbpctl_dev, ESDP,
2624  ctrl & ~BP10G_SDP1_DIR);
2625  else
2626  BP10G_WRITE_REG(pbpctl_dev, ESDP,
2627  ((ctrl | BP10G_SDP1_DIR) &
2628  ~BP10G_SDP1_DATA));
2629  return ret;
2630  }
2631 
2632  }
2633  return BP_NOT_CAP;
2634 }
2635 
2636 /*RESET_CONT 0x20 */
2637 int reset_cont(bpctl_dev_t *pbpctl_dev)
2638 {
2639  int ret = BP_NOT_CAP;
2640 
2641  if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
2642  if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
2643  return BP_NOT_CAP;
2644  if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2645  write_data(pbpctl_dev, RESET_CONT);
2646  else
2647  data_pulse(pbpctl_dev, RESET_CONT);
2648  ret = 0;
2649  };
2650  return ret;
2651 }
2652 
2653 /*DIS_BYPASS_CAP 0x22 */
2654 int dis_bypass_cap(bpctl_dev_t *pbpctl_dev)
2655 {
2656 
2657  if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2658  if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2659  write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2660  msec_delay_bp(BYPASS_DELAY_INT);
2661  } else {
2662  write_data(pbpctl_dev, BYPASS_OFF);
2663  msec_delay_bp(LATCH_DELAY);
2664  write_data(pbpctl_dev, DIS_BYPASS_CAP);
2665  msec_delay_bp(BYPASS_CAP_DELAY);
2666  }
2667  return 0;
2668  }
2669  return BP_NOT_CAP;
2670 }
2671 
2672 /*EN_BYPASS_CAP 0x24 */
2673 int en_bypass_cap(bpctl_dev_t *pbpctl_dev)
2674 {
2675  if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2676  if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2677  write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2678  msec_delay_bp(BYPASS_DELAY_INT);
2679  } else {
2680  write_data(pbpctl_dev, EN_BYPASS_CAP);
2681  msec_delay_bp(BYPASS_CAP_DELAY);
2682  }
2683  return 0;
2684  }
2685  return BP_NOT_CAP;
2686 }
2687 
2688 /* BYPASS_STATE_PWRON 0x26*/
2689 int bypass_state_pwron(bpctl_dev_t *pbpctl_dev)
2690 {
2691  if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2692  write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2693  if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2694  msec_delay_bp(DFLT_PWRON_DELAY);
2695  else
2696  msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2697  return 0;
2698  }
2699  return BP_NOT_CAP;
2700 }
2701 
2702 /* NORMAL_STATE_PWRON 0x28*/
2703 int normal_state_pwron(bpctl_dev_t *pbpctl_dev)
2704 {
2705  if ((pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP)
2706  || (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)) {
2707  write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2708  if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2709  msec_delay_bp(DFLT_PWRON_DELAY);
2710  else
2711  msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2712  return 0;
2713  }
2714  return BP_NOT_CAP;
2715 }
2716 
2717 /* BYPASS_STATE_PWROFF 0x27*/
2718 int bypass_state_pwroff(bpctl_dev_t *pbpctl_dev)
2719 {
2720  if (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP) {
2721  write_data(pbpctl_dev, BYPASS_STATE_PWROFF);
2722  msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2723  return 0;
2724  }
2725  return BP_NOT_CAP;
2726 }
2727 
2728 /* NORMAL_STATE_PWROFF 0x29*/
2729 int normal_state_pwroff(bpctl_dev_t *pbpctl_dev)
2730 {
2731  if ((pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
2732  write_data(pbpctl_dev, NORMAL_STATE_PWROFF);
2733  msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2734  return 0;
2735  }
2736  return BP_NOT_CAP;
2737 }
2738 
2739 /*TAP_STATE_PWRON 0x2a*/
2740 int tap_state_pwron(bpctl_dev_t *pbpctl_dev)
2741 {
2742  if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2743  write_data(pbpctl_dev, TAP_STATE_PWRON);
2744  msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2745  return 0;
2746  }
2747  return BP_NOT_CAP;
2748 }
2749 
2750 /*DIS_TAP_CAP 0x2c*/
2751 int dis_tap_cap(bpctl_dev_t *pbpctl_dev)
2752 {
2753  if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2754  write_data(pbpctl_dev, DIS_TAP_CAP);
2755  msec_delay_bp(BYPASS_CAP_DELAY);
2756  return 0;
2757  }
2758  return BP_NOT_CAP;
2759 }
2760 
2761 /*EN_TAP_CAP 0x2e*/
2762 int en_tap_cap(bpctl_dev_t *pbpctl_dev)
2763 {
2764  if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2765  write_data(pbpctl_dev, EN_TAP_CAP);
2766  msec_delay_bp(BYPASS_CAP_DELAY);
2767  return 0;
2768  }
2769  return BP_NOT_CAP;
2770 }
2771 
2772 /*DISC_STATE_PWRON 0x2a*/
2773 int disc_state_pwron(bpctl_dev_t *pbpctl_dev)
2774 {
2775  if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
2776  if (pbpctl_dev->bp_ext_ver >= 0x8) {
2777  write_data(pbpctl_dev, DISC_STATE_PWRON);
2778  msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2779  return BP_OK;
2780  }
2781  }
2782  return BP_NOT_CAP;
2783 }
2784 
2785 /*DIS_DISC_CAP 0x2c*/
2786 int dis_disc_cap(bpctl_dev_t *pbpctl_dev)
2787 {
2788  if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2789  if (pbpctl_dev->bp_ext_ver >= 0x8) {
2790  write_data(pbpctl_dev, DIS_DISC_CAP);
2791  msec_delay_bp(BYPASS_CAP_DELAY);
2792  return BP_OK;
2793  }
2794  }
2795  return BP_NOT_CAP;
2796 }
2797 
2798 /*DISC_STATE_PWRON 0x2a*/
2799 int disc_port_state_pwron(bpctl_dev_t *pbpctl_dev)
2800 {
2801  int ret = 0;
2802  bpctl_dev_t *pbpctl_dev_m;
2803 
2804  return BP_NOT_CAP;
2805 
2806  if ((is_bypass_fn(pbpctl_dev)) == 1)
2807  pbpctl_dev_m = pbpctl_dev;
2808  else
2809  pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2810  if (pbpctl_dev_m == NULL)
2811  return BP_NOT_CAP;
2812 
2813  if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2814  if (is_bypass_fn(pbpctl_dev) == 1)
2815  write_data(pbpctl_dev_m, TX_DISA_PWRUP);
2816  else
2817  write_data(pbpctl_dev_m, TX_DISB_PWRUP);
2818 
2819  msec_delay_bp(LATCH_DELAY);
2820 
2821  }
2822  return ret;
2823 }
2824 
2825 int normal_port_state_pwron(bpctl_dev_t *pbpctl_dev)
2826 {
2827  int ret = 0;
2828  bpctl_dev_t *pbpctl_dev_m;
2829  return BP_NOT_CAP;
2830 
2831  if ((is_bypass_fn(pbpctl_dev)) == 1)
2832  pbpctl_dev_m = pbpctl_dev;
2833  else
2834  pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2835  if (pbpctl_dev_m == NULL)
2836  return BP_NOT_CAP;
2837 
2838  if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2839  if (is_bypass_fn(pbpctl_dev) == 1)
2840  write_data(pbpctl_dev_m, TX_ENA_PWRUP);
2841  else
2842  write_data(pbpctl_dev_m, TX_ENB_PWRUP);
2843 
2844  msec_delay_bp(LATCH_DELAY);
2845 
2846  }
2847  return ret;
2848 }
2849 
2850 /*EN_TAP_CAP 0x2e*/
2851 int en_disc_cap(bpctl_dev_t *pbpctl_dev)
2852 {
2853  if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2854  if (pbpctl_dev->bp_ext_ver >= 0x8) {
2855  write_data(pbpctl_dev, EN_DISC_CAP);
2856  msec_delay_bp(BYPASS_CAP_DELAY);
2857  return BP_OK;
2858  }
2859  }
2860  return BP_NOT_CAP;
2861 }
2862 
2863 int std_nic_on(bpctl_dev_t *pbpctl_dev)
2864 {
2865 
2866  if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2867 
2868  if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2869  write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2870  msec_delay_bp(BYPASS_DELAY_INT);
2871  pbpctl_dev->bp_status_un = 0;
2872  return BP_OK;
2873  }
2874 
2875  if (pbpctl_dev->bp_ext_ver >= 0x8) {
2876  write_data(pbpctl_dev, STD_NIC_ON);
2877  msec_delay_bp(BYPASS_CAP_DELAY);
2878  return BP_OK;
2879 
2880  }
2881 
2882  if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2883  wdt_off(pbpctl_dev);
2884 
2885  if (pbpctl_dev->bp_caps & BP_CAP) {
2886  write_data(pbpctl_dev, BYPASS_OFF);
2887  msec_delay_bp(LATCH_DELAY);
2888  }
2889 
2890  if (pbpctl_dev->bp_caps & TAP_CAP) {
2891  write_data(pbpctl_dev, TAP_OFF);
2892  msec_delay_bp(LATCH_DELAY);
2893  }
2894 
2895  write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2896  if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2897  msec_delay_bp(DFLT_PWRON_DELAY);
2898  else
2899  msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2900 
2901  if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2902  write_data(pbpctl_dev, DIS_BYPASS_CAP);
2903  msec_delay_bp(BYPASS_CAP_DELAY);
2904  }
2905 
2906  if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2907  write_data(pbpctl_dev, DIS_TAP_CAP);
2908  msec_delay_bp(BYPASS_CAP_DELAY);
2909 
2910  }
2911  return 0;
2912  }
2913  }
2914  return BP_NOT_CAP;
2915 }
2916 
2917 int std_nic_off(bpctl_dev_t *pbpctl_dev)
2918 {
2919 
2920  if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2921  if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2922  write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2923  msec_delay_bp(BYPASS_DELAY_INT);
2924  return BP_OK;
2925  }
2926  if (pbpctl_dev->bp_ext_ver >= 0x8) {
2927  write_data(pbpctl_dev, STD_NIC_OFF);
2928  msec_delay_bp(BYPASS_CAP_DELAY);
2929  return BP_OK;
2930 
2931  }
2932 
2933  if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2934 
2935  if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2936  write_data(pbpctl_dev, TAP_STATE_PWRON);
2937  msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2938  }
2939 
2940  if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2941  write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2942  if (pbpctl_dev->bp_ext_ver > PXG2BPI_VER)
2943  msec_delay_bp(LATCH_DELAY +
2944  EEPROM_WR_DELAY);
2945  else
2946  msec_delay_bp(DFLT_PWRON_DELAY);
2947  }
2948 
2949  if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2950  write_data(pbpctl_dev, EN_TAP_CAP);
2951  msec_delay_bp(BYPASS_CAP_DELAY);
2952  }
2953  if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2954  write_data(pbpctl_dev, EN_DISC_CAP);
2955  msec_delay_bp(BYPASS_CAP_DELAY);
2956  }
2957 
2958  if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2959  write_data(pbpctl_dev, EN_BYPASS_CAP);
2960  msec_delay_bp(BYPASS_CAP_DELAY);
2961  }
2962 
2963  return 0;
2964  }
2965  }
2966  return BP_NOT_CAP;
2967 }
2968 
2969 int wdt_time_left(bpctl_dev_t *pbpctl_dev)
2970 {
2971 
2972  /* unsigned long curr_time=((long long)(jiffies*1000))/HZ, delta_time=0,wdt_on_time=((long long)(pbpctl_dev->bypass_wdt_on_time*1000))/HZ; */
2973  unsigned long curr_time = jiffies, delta_time = 0, wdt_on_time =
2974  pbpctl_dev->bypass_wdt_on_time, delta_time_msec = 0;
2975  int time_left = 0;
2976 
2977  switch (pbpctl_dev->wdt_status) {
2978  case WDT_STATUS_DIS:
2979  time_left = 0;
2980  break;
2981  case WDT_STATUS_EN:
2982  delta_time =
2983  (curr_time >=
2984  wdt_on_time) ? (curr_time - wdt_on_time) : (~wdt_on_time +
2985  curr_time);
2986  delta_time_msec = jiffies_to_msecs(delta_time);
2987  time_left = pbpctl_dev->bypass_timer_interval - delta_time_msec;
2988  if (time_left < 0) {
2989  time_left = -1;
2990  pbpctl_dev->wdt_status = WDT_STATUS_EXP;
2991  }
2992  break;
2993  case WDT_STATUS_EXP:
2994  time_left = -1;
2995  break;
2996  }
2997 
2998  return time_left;
2999 }
3000 
3001 static int wdt_timer(bpctl_dev_t *pbpctl_dev, int *time_left)
3002 {
3003  int ret = 0;
3004  if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3005  {
3006  if (pbpctl_dev->wdt_status == WDT_STATUS_UNKNOWN)
3007  ret = BP_NOT_CAP;
3008  else
3009  *time_left = wdt_time_left(pbpctl_dev);
3010  }
3011 
3012  } else
3013  ret = BP_NOT_CAP;
3014  return ret;
3015 }
3016 
3017 static int wdt_timer_reload(bpctl_dev_t *pbpctl_dev)
3018 {
3019 
3020  int ret = 0;
3021 
3022  if ((pbpctl_dev->bp_caps & WD_CTL_CAP) &&
3023  (pbpctl_dev->wdt_status != WDT_STATUS_UNKNOWN)) {
3024  if (pbpctl_dev->wdt_status == WDT_STATUS_DIS)
3025  return 0;
3026  if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
3027  ret = wdt_pulse(pbpctl_dev);
3028  else if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
3029  ret = wdt_pulse_int(pbpctl_dev);
3030  else
3031  ret = send_wdt_pulse(pbpctl_dev);
3032  /* if (ret==-1)
3033  mod_timer(&pbpctl_dev->bp_timer, jiffies+1);*/
3034  return 1;
3035  }
3036  return BP_NOT_CAP;
3037 }
3038 
3039 static void wd_reset_timer(unsigned long param)
3040 {
3041  bpctl_dev_t *pbpctl_dev = (bpctl_dev_t *) param;
3042 #ifdef BP_SELF_TEST
3043  struct sk_buff *skb_tmp;
3044 #endif
3045 
3046  if ((pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) &&
3047  ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)) {
3048  mod_timer(&pbpctl_dev->bp_timer, jiffies + 1);
3049  return;
3050  }
3051 #ifdef BP_SELF_TEST
3052 
3053  if (pbpctl_dev->bp_self_test_flag == 1) {
3054  skb_tmp = dev_alloc_skb(BPTEST_DATA_LEN + 2);
3055  if ((skb_tmp) && (pbpctl_dev->ndev) && (pbpctl_dev->bp_tx_data)) {
3056  memcpy(skb_put(skb_tmp, BPTEST_DATA_LEN),
3057  pbpctl_dev->bp_tx_data, BPTEST_DATA_LEN);
3058  skb_tmp->dev = pbpctl_dev->ndev;
3059  skb_tmp->protocol =
3060  eth_type_trans(skb_tmp, pbpctl_dev->ndev);
3061  skb_tmp->ip_summed = CHECKSUM_UNNECESSARY;
3062  netif_receive_skb(skb_tmp);
3063  goto bp_timer_reload;
3064  return;
3065  }
3066  }
3067 #endif
3068 
3069  wdt_timer_reload(pbpctl_dev);
3070 #ifdef BP_SELF_TEST
3071  bp_timer_reload:
3072 #endif
3073  if (pbpctl_dev->reset_time) {
3074  mod_timer(&pbpctl_dev->bp_timer,
3075  jiffies + (HZ * pbpctl_dev->reset_time) / 1000);
3076  }
3077 }
3078 
3079 /*WAIT_AT_PWRUP 0x80 */
3080 int bp_wait_at_pwup_en(bpctl_dev_t *pbpctl_dev)
3081 {
3082 
3083  if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3084  if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3085  write_data(pbpctl_dev, BP_WAIT_AT_PWUP_EN);
3086  msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3087 
3088  return BP_OK;
3089  }
3090  }
3091  return BP_NOT_CAP;
3092 }
3093 
3094 /*DIS_WAIT_AT_PWRUP 0x81 */
3095 int bp_wait_at_pwup_dis(bpctl_dev_t *pbpctl_dev)
3096 {
3097 
3098  if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3099 
3100  if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3101  write_data(pbpctl_dev, BP_WAIT_AT_PWUP_DIS);
3102  msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3103 
3104  return BP_OK;
3105  }
3106  }
3107  return BP_NOT_CAP;
3108 }
3109 
3110 /*EN_HW_RESET 0x82 */
3111 
3112 int bp_hw_reset_en(bpctl_dev_t *pbpctl_dev)
3113 {
3114 
3115  if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3116  if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3117  write_data(pbpctl_dev, BP_HW_RESET_EN);
3118  msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3119 
3120  return BP_OK;
3121  }
3122  }
3123  return BP_NOT_CAP;
3124 }
3125 
3126 /*DIS_HW_RESET 0x83 */
3127 
3128 int bp_hw_reset_dis(bpctl_dev_t *pbpctl_dev)
3129 {
3130 
3131  if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3132  if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3133  write_data(pbpctl_dev, BP_HW_RESET_DIS);
3134  msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3135 
3136  return BP_OK;
3137  }
3138  }
3139  return BP_NOT_CAP;
3140 }
3141 
3142 
3143 int wdt_exp_mode(bpctl_dev_t *pbpctl_dev, int mode)
3144 {
3145  uint32_t status_reg = 0, status_reg1 = 0;
3146 
3147  if ((pbpctl_dev->bp_caps & (TAP_STATUS_CAP | DISC_CAP)) &&
3148  (pbpctl_dev->bp_caps & BP_CAP)) {
3149  if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
3150 
3151  if ((pbpctl_dev->bp_ext_ver >= 0x8) &&
3152  (mode == 2) && (pbpctl_dev->bp_caps & DISC_CAP)) {
3153  status_reg1 =
3154  read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3155  if (!(status_reg1 & WDTE_DISC_BPN_MASK))
3156  write_reg(pbpctl_dev,
3157  status_reg1 |
3158  WDTE_DISC_BPN_MASK,
3159  STATUS_DISC_REG_ADDR);
3160  return BP_OK;
3161  }
3162  }
3163  status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3164 
3165  if ((mode == 0) && (pbpctl_dev->bp_caps & BP_CAP)) {
3166  if (pbpctl_dev->bp_ext_ver >= 0x8) {
3167  status_reg1 =
3168  read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3169  if (status_reg1 & WDTE_DISC_BPN_MASK)
3170  write_reg(pbpctl_dev,
3171  status_reg1 &
3172  ~WDTE_DISC_BPN_MASK,
3173  STATUS_DISC_REG_ADDR);
3174  }
3175  if (status_reg & WDTE_TAP_BPN_MASK)
3176  write_reg(pbpctl_dev,
3177  status_reg & ~WDTE_TAP_BPN_MASK,
3178  STATUS_TAP_REG_ADDR);
3179  return BP_OK;
3180 
3181  } else if ((mode == 1) && (pbpctl_dev->bp_caps & TAP_CAP)) {
3182  if (!(status_reg & WDTE_TAP_BPN_MASK))
3183  write_reg(pbpctl_dev,
3184  status_reg | WDTE_TAP_BPN_MASK,
3185  STATUS_TAP_REG_ADDR);
3186  /*else return BP_NOT_CAP; */
3187  return BP_OK;
3188  }
3189 
3190  }
3191  return BP_NOT_CAP;
3192 }
3193 
3194 int bypass_fw_ver(bpctl_dev_t *pbpctl_dev)
3195 {
3196  if (is_bypass_fn(pbpctl_dev))
3197  return read_reg(pbpctl_dev, VER_REG_ADDR);
3198  else
3199  return BP_NOT_CAP;
3200 }
3201 
3202 int bypass_sign_check(bpctl_dev_t *pbpctl_dev)
3203 {
3204 
3205  if (is_bypass_fn(pbpctl_dev))
3206  return (((read_reg(pbpctl_dev, PIC_SIGN_REG_ADDR)) ==
3207  PIC_SIGN_VALUE) ? 1 : 0);
3208  else
3209  return BP_NOT_CAP;
3210 }
3211 
3212 static int tx_status(bpctl_dev_t *pbpctl_dev)
3213 {
3214  uint32_t ctrl = 0;
3215  bpctl_dev_t *pbpctl_dev_m;
3216  if ((is_bypass_fn(pbpctl_dev)) == 1)
3217  pbpctl_dev_m = pbpctl_dev;
3218  else
3219  pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3220  if (pbpctl_dev_m == NULL)
3221  return BP_NOT_CAP;
3222  if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3223 
3224  ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3225  if (pbpctl_dev->bp_i80)
3226  return ((ctrl & BPCTLI_CTRL_SWDPIN1) != 0 ? 0 : 1);
3227  if (pbpctl_dev->bp_540) {
3228  ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3229 
3230  return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3231  }
3232 
3233  }
3234 
3235  if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
3236  if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
3237  uint16_t mii_reg;
3238  if (!
3239  (bp75_read_phy_reg
3240  (pbpctl_dev, BPCTLI_PHY_CONTROL, &mii_reg))) {
3241  if (mii_reg & BPCTLI_MII_CR_POWER_DOWN)
3242  return 0;
3243 
3244  else
3245  return 1;
3246  }
3247  return -1;
3248  }
3249 
3250  if (pbpctl_dev->bp_10g9) {
3251  return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3252  BP10G_SDP3_DATA) != 0 ? 0 : 1);
3253 
3254  } else if (pbpctl_dev->bp_fiber5) {
3255  ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
3256  if (ctrl & BPCTLI_CTRL_EXT_SDP6_DATA)
3257  return 0;
3258  return 1;
3259  } else if (pbpctl_dev->bp_10gb) {
3260  ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3261  BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3262  (ctrl | BP10GB_GPIO0_OE_P1) &
3263  ~(BP10GB_GPIO0_SET_P1 |
3264  BP10GB_GPIO0_CLR_P1));
3265 
3266  if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
3267  return (((BP10GB_READ_REG
3268  (pbpctl_dev,
3269  MISC_REG_GPIO)) & BP10GB_GPIO0_P1) !=
3270  0 ? 0 : 1);
3271  else
3272  return (((BP10GB_READ_REG
3273  (pbpctl_dev,
3274  MISC_REG_GPIO)) & BP10GB_GPIO0_P0) !=
3275  0 ? 0 : 1);
3276  }
3277 
3278  if (!pbpctl_dev->bp_10g) {
3279 
3280  ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3281  if (pbpctl_dev->bp_i80)
3282  return ((ctrl & BPCTLI_CTRL_SWDPIN1) !=
3283  0 ? 0 : 1);
3284  if (pbpctl_dev->bp_540) {
3285  ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3286 
3287  return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3288  }
3289 
3290  return ((ctrl & BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3291  } else
3292  return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3293  BP10G_SDP0_DATA) != 0 ? 0 : 1);
3294 
3295  }
3296  return BP_NOT_CAP;
3297 }
3298 
3299 static int bp_force_link_status(bpctl_dev_t *pbpctl_dev)
3300 {
3301 
3302  if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
3303 
3304  if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
3305  return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3306  BP10G_SDP1_DIR) != 0 ? 1 : 0);
3307 
3308  }
3309  }
3310  return BP_NOT_CAP;
3311 }
3312 
3313 int bypass_from_last_read(bpctl_dev_t *pbpctl_dev)
3314 {
3315  uint32_t ctrl_ext = 0;
3316  bpctl_dev_t *pbpctl_dev_b = NULL;
3317 
3318  if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3319  && (pbpctl_dev_b = get_status_port_fn(pbpctl_dev))) {
3320  ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3321  BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL_EXT,
3322  (ctrl_ext & ~BPCTLI_CTRL_EXT_SDP7_DIR));
3323  ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3324  if (ctrl_ext & BPCTLI_CTRL_EXT_SDP7_DATA)
3325  return 0;
3326  return 1;
3327  } else
3328  return BP_NOT_CAP;
3329 }
3330 
3331 int bypass_status_clear(bpctl_dev_t *pbpctl_dev)
3332 {
3333  bpctl_dev_t *pbpctl_dev_b = NULL;
3334 
3335  if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3336  && (pbpctl_dev_b = get_status_port_fn(pbpctl_dev))) {
3337 
3338  send_bypass_clear_pulse(pbpctl_dev_b, 1);
3339  return 0;
3340  } else
3341  return BP_NOT_CAP;
3342 }
3343 
3344 int bypass_flag_status(bpctl_dev_t *pbpctl_dev)
3345 {
3346 
3347  if ((pbpctl_dev->bp_caps & BP_CAP)) {
3348  if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3349  return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3350  BYPASS_FLAG_MASK) ==
3351  BYPASS_FLAG_MASK) ? 1 : 0);
3352  }
3353  }
3354  return BP_NOT_CAP;
3355 }
3356 
3357 int bypass_flag_status_clear(bpctl_dev_t *pbpctl_dev)
3358 {
3359 
3360  if (pbpctl_dev->bp_caps & BP_CAP) {
3361  if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3362  uint32_t status_reg = 0;
3363  status_reg = read_reg(pbpctl_dev, STATUS_REG_ADDR);
3364  write_reg(pbpctl_dev, status_reg & ~BYPASS_FLAG_MASK,
3365  STATUS_REG_ADDR);
3366  return 0;
3367  }
3368  }
3369  return BP_NOT_CAP;
3370 }
3371 
3372 int bypass_change_status(bpctl_dev_t *pbpctl_dev)
3373 {
3374  int ret = BP_NOT_CAP;
3375 
3376  if (pbpctl_dev->bp_caps & BP_STATUS_CHANGE_CAP) {
3377  if (pbpctl_dev->bp_ext_ver >= 0x8) {
3378  ret = bypass_flag_status(pbpctl_dev);
3379  bypass_flag_status_clear(pbpctl_dev);
3380  } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3381  ret = bypass_flag_status(pbpctl_dev);
3382  bypass_flag_status_clear(pbpctl_dev);
3383  } else {
3384  ret = bypass_from_last_read(pbpctl_dev);
3385  bypass_status_clear(pbpctl_dev);
3386  }
3387  }
3388  return ret;
3389 }
3390 
3391 int bypass_off_status(bpctl_dev_t *pbpctl_dev)
3392 {
3393 
3394  if (pbpctl_dev->bp_caps & BP_CAP) {
3395  if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3396  return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3397  BYPASS_OFF_MASK) == BYPASS_OFF_MASK) ? 1 : 0);
3398  }
3399  }
3400  return BP_NOT_CAP;
3401 }
3402 
3403 static int bypass_status(bpctl_dev_t *pbpctl_dev)
3404 {
3405  u32 ctrl_ext = 0;
3406  if (pbpctl_dev->bp_caps & BP_CAP) {
3407 
3408  bpctl_dev_t *pbpctl_dev_b = NULL;
3409 
3410  if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3411  return BP_NOT_CAP;
3412 
3413  if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
3414 
3415  if (!pbpctl_dev->bp_status_un)
3416  return (((BPCTL_READ_REG
3417  (pbpctl_dev_b,
3418  CTRL_EXT)) &
3419  BPCTLI_CTRL_EXT_SDP7_DATA) !=
3420  0 ? 1 : 0);
3421  else
3422  return BP_NOT_CAP;
3423  }
3424  if (pbpctl_dev->bp_ext_ver >= 0x8) {
3425 
3426  if (pbpctl_dev->bp_10g9) {
3427  ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3428  BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3429  (ctrl_ext | BP10G_I2C_CLK_OUT));
3430  return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3431  BP10G_I2C_CLK_IN) != 0 ? 0 : 1);
3432 
3433  } else if (pbpctl_dev->bp_540) {
3434  return (((BP10G_READ_REG(pbpctl_dev_b, ESDP)) &
3435  BP10G_SDP0_DATA) != 0 ? 0 : 1);
3436  }
3437 
3438  else if ((pbpctl_dev->bp_fiber5)
3439  || (pbpctl_dev->bp_i80)) {
3440  return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3441  BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3442  } else if (pbpctl_dev->bp_10gb) {
3443  ctrl_ext =
3444  BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3445  BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3446  (ctrl_ext | BP10GB_GPIO3_OE_P0)
3447  & ~(BP10GB_GPIO3_SET_P0 |
3448  BP10GB_GPIO3_CLR_P0));
3449 
3450  return (((BP10GB_READ_REG
3451  (pbpctl_dev,
3452  MISC_REG_GPIO)) & BP10GB_GPIO3_P0) !=
3453  0 ? 0 : 1);
3454  }
3455 
3456  else if (!pbpctl_dev->bp_10g)
3457  return (((BPCTL_READ_REG
3458  (pbpctl_dev_b,
3459  CTRL_EXT)) &
3460  BPCTLI_CTRL_EXT_SDP7_DATA) !=
3461  0 ? 0 : 1);
3462 
3463  else {
3464  ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3465  BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3466  (ctrl_ext |
3467  BP10G_SDP7_DATA_OUT));
3468  return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3469  BP10G_SDP7_DATA_IN) != 0 ? 0 : 1);
3470  }
3471 
3472  } else if (pbpctl_dev->media_type == bp_copper) {
3473 
3474  return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3475  BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3476  } else {
3477  if ((bypass_status_clear(pbpctl_dev)) >= 0)
3478  return bypass_from_last_read(pbpctl_dev);
3479  }
3480 
3481  }
3482  return BP_NOT_CAP;
3483 }
3484 
3485 int default_pwron_status(bpctl_dev_t *pbpctl_dev)
3486 {
3487 
3488  if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3489  if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
3490  if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3491  return ((((read_reg
3492  (pbpctl_dev,
3493  STATUS_REG_ADDR)) & DFLT_PWRON_MASK)
3494  == DFLT_PWRON_MASK) ? 0 : 1);
3495  }
3496  } /*else if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3497  (pbpctl_dev->bp_caps&BP_PWUP_ON_CAP))
3498  return 1; */
3499  }
3500  return BP_NOT_CAP;
3501 }
3502 
3503 static int default_pwroff_status(bpctl_dev_t *pbpctl_dev)
3504 {
3505 
3506  /*if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3507  (pbpctl_dev->bp_caps&BP_PWOFF_ON_CAP))
3508  return 1; */
3509  if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3510  && (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
3511  return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3512  DFLT_PWROFF_MASK) == DFLT_PWROFF_MASK) ? 0 : 1);
3513  }
3514  return BP_NOT_CAP;
3515 }
3516 
3517 int dis_bypass_cap_status(bpctl_dev_t *pbpctl_dev)
3518 {
3519 
3520  if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
3521  if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3522  return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3523  DIS_BYPASS_CAP_MASK) ==
3524  DIS_BYPASS_CAP_MASK) ? 1 : 0);
3525  }
3526  }
3527  return BP_NOT_CAP;
3528 }
3529 
3530 int cmd_en_status(bpctl_dev_t *pbpctl_dev)
3531 {
3532 
3533  if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3534  if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3535  return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3536  CMND_EN_MASK) == CMND_EN_MASK) ? 1 : 0);
3537  }
3538  }
3539  return BP_NOT_CAP;
3540 }
3541 
3542 int wdt_en_status(bpctl_dev_t *pbpctl_dev)
3543 {
3544 
3545  if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3546  if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3547  return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3548  WDT_EN_MASK) == WDT_EN_MASK) ? 1 : 0);
3549  }
3550  }
3551  return BP_NOT_CAP;
3552 }
3553 
3554 int wdt_programmed(bpctl_dev_t *pbpctl_dev, int *timeout)
3555 {
3556  int ret = 0;
3557  if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3558  if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3559  if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3560  WDT_EN_MASK) {
3561  u8 wdt_val;
3562  wdt_val = read_reg(pbpctl_dev, WDT_REG_ADDR);
3563  *timeout = (1 << wdt_val) * 100;
3564  } else
3565  *timeout = 0;
3566  } else {
3567  int curr_wdt_status = pbpctl_dev->wdt_status;
3568  if (curr_wdt_status == WDT_STATUS_UNKNOWN)
3569  *timeout = -1;
3570  else
3571  *timeout =
3572  curr_wdt_status ==
3573  0 ? 0 : pbpctl_dev->bypass_timer_interval;
3574  };
3575  } else
3576  ret = BP_NOT_CAP;
3577  return ret;
3578 }
3579 
3580 int bypass_support(bpctl_dev_t *pbpctl_dev)
3581 {
3582  int ret = 0;
3583 
3584  if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3585  if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3586  ret =
3587  ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3588  BYPASS_SUPPORT_MASK) ==
3589  BYPASS_SUPPORT_MASK) ? 1 : 0);
3590  } else if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
3591  ret = 1;
3592  } else
3593  ret = BP_NOT_CAP;
3594  return ret;
3595 }
3596 
3597 int tap_support(bpctl_dev_t *pbpctl_dev)
3598 {
3599  int ret = 0;
3600 
3601  if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3602  if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3603  ret =
3604  ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3605  TAP_SUPPORT_MASK) == TAP_SUPPORT_MASK) ? 1 : 0);
3606  } else if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
3607  ret = 0;
3608  } else
3609  ret = BP_NOT_CAP;
3610  return ret;
3611 }
3612 
3613 int normal_support(bpctl_dev_t *pbpctl_dev)
3614 {
3615  int ret = BP_NOT_CAP;
3616 
3617  if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3618  if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3619  ret =
3620  ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3621  NORMAL_UNSUPPORT_MASK) ==
3622  NORMAL_UNSUPPORT_MASK) ? 0 : 1);
3623  } else
3624  ret = 1;
3625  };
3626  return ret;
3627 }
3628 
3629 int get_bp_prod_caps(bpctl_dev_t *pbpctl_dev)
3630 {
3631  if ((pbpctl_dev->bp_caps & SW_CTL_CAP) &&
3632  (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER))
3633  return read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR);
3634  return BP_NOT_CAP;
3635 
3636 }
3637 
3638 int tap_flag_status(bpctl_dev_t *pbpctl_dev)
3639 {
3640 
3641  if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3642  if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3643  return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3644  TAP_FLAG_MASK) == TAP_FLAG_MASK) ? 1 : 0);
3645 
3646  }
3647  return BP_NOT_CAP;
3648 }
3649 
3650 int tap_flag_status_clear(bpctl_dev_t *pbpctl_dev)
3651 {
3652  uint32_t status_reg = 0;
3653  if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3654  if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3655  status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3656  write_reg(pbpctl_dev, status_reg & ~TAP_FLAG_MASK,
3657  STATUS_TAP_REG_ADDR);
3658  return 0;
3659  }
3660  }
3661  return BP_NOT_CAP;
3662 }
3663 
3664 int tap_change_status(bpctl_dev_t *pbpctl_dev)
3665 {
3666  int ret = BP_NOT_CAP;
3667  if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3668  if (pbpctl_dev->bp_caps & TAP_CAP) {
3669  if (pbpctl_dev->bp_caps & BP_CAP) {
3670  ret = tap_flag_status(pbpctl_dev);
3671  tap_flag_status_clear(pbpctl_dev);
3672  } else {
3673  ret = bypass_from_last_read(pbpctl_dev);
3674  bypass_status_clear(pbpctl_dev);
3675  }
3676  }
3677  }
3678  return ret;
3679 }
3680 
3681 int tap_off_status(bpctl_dev_t *pbpctl_dev)
3682 {
3683  if (pbpctl_dev->bp_caps & TAP_CAP) {
3684  if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3685  return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3686  TAP_OFF_MASK) == TAP_OFF_MASK) ? 1 : 0);
3687  }
3688  return BP_NOT_CAP;
3689 }
3690 
3691 int tap_status(bpctl_dev_t *pbpctl_dev)
3692 {
3693  u32 ctrl_ext = 0;
3694 
3695  if (pbpctl_dev->bp_caps & TAP_CAP) {
3696  bpctl_dev_t *pbpctl_dev_b = NULL;
3697 
3698  if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3699  return BP_NOT_CAP;
3700 
3701  if (pbpctl_dev->bp_ext_ver >= 0x8) {
3702  if (!pbpctl_dev->bp_10g)
3703  return (((BPCTL_READ_REG
3704  (pbpctl_dev_b,
3705  CTRL_EXT)) &
3706  BPCTLI_CTRL_EXT_SDP6_DATA) !=
3707  0 ? 0 : 1);
3708  else {
3709  ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3710  BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3711  (ctrl_ext |
3712  BP10G_SDP6_DATA_OUT));
3713  return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3714  BP10G_SDP6_DATA_IN) != 0 ? 0 : 1);
3715  }
3716 
3717  } else if (pbpctl_dev->media_type == bp_copper)
3718  return (((BPCTL_READ_REG(pbpctl_dev, CTRL)) &
3719  BPCTLI_CTRL_SWDPIN0) != 0 ? 1 : 0);
3720  else {
3721  if ((bypass_status_clear(pbpctl_dev)) >= 0)
3722  return bypass_from_last_read(pbpctl_dev);
3723  }
3724 
3725  }
3726  return BP_NOT_CAP;
3727 }
3728 
3729 int default_pwron_tap_status(bpctl_dev_t *pbpctl_dev)
3730 {
3731  if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3732  if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3733  return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3734  DFLT_PWRON_TAP_MASK) ==
3735  DFLT_PWRON_TAP_MASK) ? 1 : 0);
3736  }
3737  return BP_NOT_CAP;
3738 }
3739 
3740 int dis_tap_cap_status(bpctl_dev_t *pbpctl_dev)
3741 {
3742  if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3743  if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3744  return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3745  DIS_TAP_CAP_MASK) ==
3746  DIS_TAP_CAP_MASK) ? 1 : 0);
3747  }
3748  return BP_NOT_CAP;
3749 }
3750 
3751 int disc_flag_status(bpctl_dev_t *pbpctl_dev)
3752 {
3753 
3754  if (pbpctl_dev->bp_caps & DISC_CAP) {
3755  if (pbpctl_dev->bp_ext_ver >= 0x8)
3756  return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3757  DISC_FLAG_MASK) == DISC_FLAG_MASK) ? 1 : 0);
3758 
3759  }
3760  return BP_NOT_CAP;
3761 }
3762 
3763 int disc_flag_status_clear(bpctl_dev_t *pbpctl_dev)
3764 {
3765  uint32_t status_reg = 0;
3766  if (pbpctl_dev->bp_caps & DISC_CAP) {
3767  if (pbpctl_dev->bp_ext_ver >= 0x8) {
3768  status_reg = read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3769  write_reg(pbpctl_dev, status_reg & ~DISC_FLAG_MASK,
3770  STATUS_DISC_REG_ADDR);
3771  return BP_OK;
3772  }
3773  }
3774  return BP_NOT_CAP;
3775 }
3776 
3777 int disc_change_status(bpctl_dev_t *pbpctl_dev)
3778 {
3779  int ret = BP_NOT_CAP;
3780  if (pbpctl_dev->bp_caps & DISC_CAP) {
3781  ret = disc_flag_status(pbpctl_dev);
3782  disc_flag_status_clear(pbpctl_dev);
3783  return ret;
3784  }
3785  return BP_NOT_CAP;
3786 }
3787 
3788 int disc_off_status(bpctl_dev_t *pbpctl_dev)
3789 {
3790  bpctl_dev_t *pbpctl_dev_b = NULL;
3791  u32 ctrl_ext = 0;
3792 
3793  if (pbpctl_dev->bp_caps & DISC_CAP) {
3794  if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3795  return BP_NOT_CAP;
3796  if (DISCF_IF_SERIES(pbpctl_dev->subdevice))
3797  return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3798  DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3799 
3800  if (pbpctl_dev->bp_i80) {
3801  return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT)) &
3802  BPCTLI_CTRL_EXT_SDP6_DATA) != 0 ? 1 : 0);
3803 
3804  }
3805  if (pbpctl_dev->bp_540) {
3806  ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, ESDP);
3807  return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3808  BP10G_SDP2_DATA) != 0 ? 1 : 0);
3809 
3810  }
3811  if (pbpctl_dev->media_type == bp_copper) {
3812 
3813 #if 0
3814  return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3815  DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3816 #endif
3817  if (!pbpctl_dev->bp_10g)
3818  return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3819  BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3820  else
3821  return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3822  BP10G_SDP1_DATA) != 0 ? 1 : 0);
3823 
3824  } else {
3825 
3826  if (pbpctl_dev->bp_10g9) {
3827  ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3828  BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3829  (ctrl_ext |
3830  BP10G_I2C_DATA_OUT));
3831  return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3832  BP10G_I2C_DATA_IN) != 0 ? 1 : 0);
3833 
3834  } else if (pbpctl_dev->bp_fiber5) {
3835  return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3836  BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3837  } else if (pbpctl_dev->bp_10gb) {
3838  ctrl_ext =
3839  BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3840  BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3841  (ctrl_ext | BP10GB_GPIO3_OE_P1)
3842  & ~(BP10GB_GPIO3_SET_P1 |
3843  BP10GB_GPIO3_CLR_P1));
3844 
3845  return (((BP10GB_READ_REG
3846  (pbpctl_dev,
3847  MISC_REG_GPIO)) & BP10GB_GPIO3_P1) !=
3848  0 ? 1 : 0);
3849  }
3850  if (!pbpctl_dev->bp_10g) {
3851 
3852  return (((BPCTL_READ_REG
3853  (pbpctl_dev_b,
3854  CTRL_EXT)) &
3855  BPCTLI_CTRL_EXT_SDP6_DATA) !=
3856  0 ? 1 : 0);
3857  } else {
3858  ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3859  BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3860  (ctrl_ext |
3861  BP10G_SDP6_DATA_OUT));
3862  return (((BP10G_READ_REG(pbpctl_dev_b, EODSDP))
3863  & BP10G_SDP6_DATA_IN) != 0 ? 1 : 0);
3864  }
3865 
3866  }
3867  }
3868  return BP_NOT_CAP;
3869 }
3870 
3871 static int disc_status(bpctl_dev_t *pbpctl_dev)
3872 {
3873  int ctrl = 0;
3874  if (pbpctl_dev->bp_caps & DISC_CAP) {
3875 
3876  if ((ctrl = disc_off_status(pbpctl_dev)) < 0)
3877  return ctrl;
3878  return ((ctrl == 0) ? 1 : 0);
3879 
3880  }
3881  return BP_NOT_CAP;
3882 }
3883 
3884 int default_pwron_disc_status(bpctl_dev_t *pbpctl_dev)
3885 {
3886  if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
3887  if (pbpctl_dev->bp_ext_ver >= 0x8)
3888  return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3889  DFLT_PWRON_DISC_MASK) ==
3890  DFLT_PWRON_DISC_MASK) ? 1 : 0);
3891  }
3892  return BP_NOT_CAP;
3893 }
3894 
3895 int dis_disc_cap_status(bpctl_dev_t *pbpctl_dev)
3896 {
3897  if (pbpctl_dev->bp_caps & DIS_DISC_CAP) {
3898  if (pbpctl_dev->bp_ext_ver >= 0x8)
3899  return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3900  DIS_DISC_CAP_MASK) ==
3901  DIS_DISC_CAP_MASK) ? 1 : 0);
3902  }
3903  return BP_NOT_CAP;
3904 }
3905 
3906 int disc_port_status(bpctl_dev_t *pbpctl_dev)
3907 {
3908  int ret = BP_NOT_CAP;
3909  bpctl_dev_t *pbpctl_dev_m;
3910 
3911  if ((is_bypass_fn(pbpctl_dev)) == 1)
3912  pbpctl_dev_m = pbpctl_dev;
3913  else
3914  pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3915  if (pbpctl_dev_m == NULL)
3916  return BP_NOT_CAP;
3917 
3918  if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3919  if (is_bypass_fn(pbpctl_dev) == 1) {
3920  return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3921  TX_DISA_MASK) == TX_DISA_MASK) ? 1 : 0);
3922  } else
3923  return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3924  TX_DISB_MASK) == TX_DISB_MASK) ? 1 : 0);
3925 
3926  }
3927  return ret;
3928 }
3929 
3930 int default_pwron_disc_port_status(bpctl_dev_t *pbpctl_dev)
3931 {
3932  int ret = BP_NOT_CAP;
3933  bpctl_dev_t *pbpctl_dev_m;
3934 
3935  if ((is_bypass_fn(pbpctl_dev)) == 1)
3936  pbpctl_dev_m = pbpctl_dev;
3937  else
3938  pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3939  if (pbpctl_dev_m == NULL)
3940  return BP_NOT_CAP;
3941 
3942  if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3943  if (is_bypass_fn(pbpctl_dev) == 1)
3944  return ret;
3945  /* return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0); */
3946  else
3947  return ret;
3948  /* return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0); */
3949 
3950  }
3951  return ret;
3952 }
3953 
3954 int wdt_exp_mode_status(bpctl_dev_t *pbpctl_dev)
3955 {
3956  if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3957  if (pbpctl_dev->bp_ext_ver <= PXG2BPI_VER)
3958  return 0; /* bypass mode */
3959  else if (pbpctl_dev->bp_ext_ver == PXG2TBPI_VER)
3960  return 1; /* tap mode */
3961  else if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
3962  if (pbpctl_dev->bp_ext_ver >= 0x8) {
3963  if (((read_reg
3964  (pbpctl_dev,
3965  STATUS_DISC_REG_ADDR)) &
3966  WDTE_DISC_BPN_MASK) == WDTE_DISC_BPN_MASK)
3967  return 2;
3968  }
3969  return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3970  WDTE_TAP_BPN_MASK) ==
3971  WDTE_TAP_BPN_MASK) ? 1 : 0);
3972  }
3973  }
3974  return BP_NOT_CAP;
3975 }
3976 
3977 int tpl2_flag_status(bpctl_dev_t *pbpctl_dev)
3978 {
3979 
3980  if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
3981  return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3982  TPL2_FLAG_MASK) == TPL2_FLAG_MASK) ? 1 : 0);
3983 
3984  }
3985  return BP_NOT_CAP;
3986 }
3987 
3988 int tpl_hw_status(bpctl_dev_t *pbpctl_dev)
3989 {
3990  bpctl_dev_t *pbpctl_dev_b = NULL;
3991 
3992  if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3993  return BP_NOT_CAP;
3994 
3995  if (TPL_IF_SERIES(pbpctl_dev->subdevice))
3996  return (((BPCTL_READ_REG(pbpctl_dev, CTRL)) &
3997  BPCTLI_CTRL_SWDPIN0) != 0 ? 1 : 0);
3998  return BP_NOT_CAP;
3999 }
4000 
4001 
4002 int bp_wait_at_pwup_status(bpctl_dev_t *pbpctl_dev)
4003 {
4004  if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
4005  if (pbpctl_dev->bp_ext_ver >= 0x8)
4006  return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
4007  WAIT_AT_PWUP_MASK) ==
4008  WAIT_AT_PWUP_MASK) ? 1 : 0);
4009  }
4010  return BP_NOT_CAP;
4011 }
4012 
4013 int bp_hw_reset_status(bpctl_dev_t *pbpctl_dev)
4014 {
4015 
4016  if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
4017 
4018  if (pbpctl_dev->bp_ext_ver >= 0x8)
4019  return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
4020  EN_HW_RESET_MASK) ==
4021  EN_HW_RESET_MASK) ? 1 : 0);
4022  }
4023  return BP_NOT_CAP;
4024 }
4025 
4026 
4027 int std_nic_status(bpctl_dev_t *pbpctl_dev)
4028 {
4029  int status_val = 0;
4030 
4031  if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
4032  if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4033  return BP_NOT_CAP;
4034  if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
4035  return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
4036  STD_NIC_ON_MASK) == STD_NIC_ON_MASK) ? 1 : 0);
4037  }
4038 
4039  if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
4040  if (pbpctl_dev->bp_caps & BP_CAP) {
4041  status_val =
4042  read_reg(pbpctl_dev, STATUS_REG_ADDR);
4043  if (((!(status_val & WDT_EN_MASK))
4044  && ((status_val & STD_NIC_MASK) ==
4045  STD_NIC_MASK)))
4046  status_val = 1;
4047  else
4048  return 0;
4049  }
4050  if (pbpctl_dev->bp_caps & TAP_CAP) {
4051  status_val =
4052  read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
4053  if ((status_val & STD_NIC_TAP_MASK) ==
4054  STD_NIC_TAP_MASK)
4055  status_val = 1;
4056  else
4057  return 0;
4058  }
4059  if (pbpctl_dev->bp_caps & TAP_CAP) {
4060  if ((disc_off_status(pbpctl_dev)))
4061  status_val = 1;
4062  else
4063  return 0;
4064  }
4065 
4066  return status_val;
4067  }
4068  }
4069  return BP_NOT_CAP;
4070 }
4071 
4072 /******************************************************/
4073 /**************SW_INIT*********************************/
4074 /******************************************************/
4075 void bypass_caps_init(bpctl_dev_t *pbpctl_dev)
4076 {
4077  u_int32_t ctrl_ext = 0;
4078  bpctl_dev_t *pbpctl_dev_m = NULL;
4079 
4080 #ifdef BYPASS_DEBUG
4081  int ret = 0;
4082  if (!(INTEL_IF_SERIES(adapter->bp_device_block.subdevice))) {
4083  ret = read_reg(pbpctl_dev, VER_REG_ADDR);
4084  printk("VER_REG reg1=%x\n", ret);
4085  ret = read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR);
4086  printk("PRODUCT_CAP reg=%x\n", ret);
4087  ret = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
4088  printk("STATUS_TAP reg1=%x\n", ret);
4089  ret = read_reg(pbpctl_dev, 0x7);
4090  printk("SIG_REG reg1=%x\n", ret);
4091  ret = read_reg(pbpctl_dev, STATUS_REG_ADDR);
4092  printk("STATUS_REG_ADDR=%x\n", ret);
4093  ret = read_reg(pbpctl_dev, WDT_REG_ADDR);
4094  printk("WDT_REG_ADDR=%x\n", ret);
4095  ret = read_reg(pbpctl_dev, TMRL_REG_ADDR);
4096  printk("TMRL_REG_ADDR=%x\n", ret);
4097  ret = read_reg(pbpctl_dev, TMRH_REG_ADDR);
4098  printk("TMRH_REG_ADDR=%x\n", ret);
4099  }
4100 #endif
4101  if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_10g9)) {
4102  pbpctl_dev->media_type = bp_fiber;
4103  } else if (pbpctl_dev->bp_10gb) {
4104  if (BP10GB_CX4_SERIES(pbpctl_dev->subdevice))
4105  pbpctl_dev->media_type = bp_cx4;
4106  else
4107  pbpctl_dev->media_type = bp_fiber;
4108 
4109  }
4110 
4111  else if (pbpctl_dev->bp_540)
4112  pbpctl_dev->media_type = bp_none;
4113  else if (!pbpctl_dev->bp_10g) {
4114 
4115  ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
4116  if ((ctrl_ext & BPCTLI_CTRL_EXT_LINK_MODE_MASK) == 0x0)
4117  pbpctl_dev->media_type = bp_copper;
4118  else
4119  pbpctl_dev->media_type = bp_fiber;
4120 
4121  } else {
4122  if (BP10G_CX4_SERIES(pbpctl_dev->subdevice))
4123  pbpctl_dev->media_type = bp_cx4;
4124  else
4125  pbpctl_dev->media_type = bp_fiber;
4126  }
4127 
4128  if (is_bypass_fn(pbpctl_dev)) {
4129 
4130  pbpctl_dev->bp_caps |= BP_PWOFF_ON_CAP;
4131  if (pbpctl_dev->media_type == bp_fiber)
4132  pbpctl_dev->bp_caps |=
4133  (TX_CTL_CAP | TX_STATUS_CAP | TPL_CAP);
4134 
4135  if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
4136  pbpctl_dev->bp_caps |= TPL_CAP;
4137  }
4138 
4139  if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
4140  pbpctl_dev->bp_caps |=
4141  (BP_CAP | BP_STATUS_CAP | SW_CTL_CAP |
4142  BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWOFF_OFF_CAP
4143  | WD_CTL_CAP | WD_STATUS_CAP | STD_NIC_CAP |
4144  WD_TIMEOUT_CAP);
4145 
4146  pbpctl_dev->bp_ext_ver = OLD_IF_VER;
4147  return;
4148  }
4149 
4150  if ((pbpctl_dev->bp_fw_ver == 0xff) &&
4151  OLD_IF_SERIES(pbpctl_dev->subdevice)) {
4152 
4153  pbpctl_dev->bp_caps |=
4154  (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
4155  SW_CTL_CAP | BP_PWUP_ON_CAP | WD_CTL_CAP |
4156  WD_STATUS_CAP | WD_TIMEOUT_CAP);
4157 
4158  pbpctl_dev->bp_ext_ver = OLD_IF_VER;
4159  return;
4160  }
4161 
4162  else {
4163  switch (pbpctl_dev->bp_fw_ver) {
4164  case BP_FW_VER_A0:
4165  case BP_FW_VER_A1:{
4166  pbpctl_dev->bp_ext_ver =
4167  (pbpctl_dev->
4168  bp_fw_ver & EXT_VER_MASK);
4169  break;
4170  }
4171  default:{
4172  if ((bypass_sign_check(pbpctl_dev)) !=
4173  1) {
4174  pbpctl_dev->bp_caps = 0;
4175  return;
4176  }
4177  pbpctl_dev->bp_ext_ver =
4178  (pbpctl_dev->
4179  bp_fw_ver & EXT_VER_MASK);
4180  }
4181  }
4182  }
4183 
4184  if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
4185  pbpctl_dev->bp_caps |=
4186  (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
4187  SW_CTL_CAP | BP_DIS_CAP | BP_DIS_STATUS_CAP |
4188  BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP
4189  | WD_CTL_CAP | STD_NIC_CAP | WD_STATUS_CAP |
4190  WD_TIMEOUT_CAP);
4191  else if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
4192  int cap_reg;
4193 
4194  pbpctl_dev->bp_caps |=
4195  (SW_CTL_CAP | WD_CTL_CAP | WD_STATUS_CAP |
4196  WD_TIMEOUT_CAP);
4197  cap_reg = get_bp_prod_caps(pbpctl_dev);
4198 
4199  if ((cap_reg & NORMAL_UNSUPPORT_MASK) ==
4200  NORMAL_UNSUPPORT_MASK)
4201  pbpctl_dev->bp_caps |= NIC_CAP_NEG;
4202  else
4203  pbpctl_dev->bp_caps |= STD_NIC_CAP;
4204 
4205  if ((normal_support(pbpctl_dev)) == 1)
4206 
4207  pbpctl_dev->bp_caps |= STD_NIC_CAP;
4208 
4209  else
4210  pbpctl_dev->bp_caps |= NIC_CAP_NEG;
4211  if ((cap_reg & BYPASS_SUPPORT_MASK) ==
4212  BYPASS_SUPPORT_MASK) {
4213  pbpctl_dev->bp_caps |=
4214  (BP_CAP | BP_STATUS_CAP |
4215  BP_STATUS_CHANGE_CAP | BP_DIS_CAP |
4216  BP_DIS_STATUS_CAP | BP_PWUP_ON_CAP |
4217  BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP);
4218  if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER7)
4219  pbpctl_dev->bp_caps |=
4220  BP_PWOFF_ON_CAP | BP_PWOFF_OFF_CAP |
4221  BP_PWOFF_CTL_CAP;
4222  }
4223  if ((cap_reg & TAP_SUPPORT_MASK) == TAP_SUPPORT_MASK) {
4224  pbpctl_dev->bp_caps |=
4225  (TAP_CAP | TAP_STATUS_CAP |
4226  TAP_STATUS_CHANGE_CAP | TAP_DIS_CAP |
4227  TAP_DIS_STATUS_CAP | TAP_PWUP_ON_CAP |
4228  TAP_PWUP_OFF_CAP | TAP_PWUP_CTL_CAP);
4229  }
4230  if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
4231  if ((cap_reg & DISC_SUPPORT_MASK) ==
4232  DISC_SUPPORT_MASK)
4233  pbpctl_dev->bp_caps |=
4234  (DISC_CAP | DISC_DIS_CAP |
4235  DISC_PWUP_CTL_CAP);
4236  if ((cap_reg & TPL2_SUPPORT_MASK) ==
4237  TPL2_SUPPORT_MASK) {
4238  pbpctl_dev->bp_caps_ex |= TPL2_CAP_EX;
4239  pbpctl_dev->bp_caps |= TPL_CAP;
4240  pbpctl_dev->bp_tpl_flag =
4241  tpl2_flag_status(pbpctl_dev);
4242  }
4243 
4244  }
4245 
4246  if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER9) {
4247  if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
4248  DISC_PORT_SUPPORT_MASK) {
4249  pbpctl_dev->bp_caps_ex |=
4250  DISC_PORT_CAP_EX;
4251  pbpctl_dev->bp_caps |=
4252  (TX_CTL_CAP | TX_STATUS_CAP);
4253  }
4254 
4255  }
4256 
4257  }
4258  if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
4259  if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
4260  WDT_EN_MASK)
4261  pbpctl_dev->wdt_status = WDT_STATUS_EN;
4262  else
4263  pbpctl_dev->wdt_status = WDT_STATUS_DIS;
4264  }
4265 
4266  } else if ((P2BPFI_IF_SERIES(pbpctl_dev->subdevice)) ||
4267  (PEGF5_IF_SERIES(pbpctl_dev->subdevice)) ||
4268  (PEGF80_IF_SERIES(pbpctl_dev->subdevice)) ||
4269  (BP10G9_IF_SERIES(pbpctl_dev->subdevice))) {
4270  pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4271  }
4272  if ((pbpctl_dev->subdevice & 0xa00) == 0xa00)
4273  pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4274  if (PEG5_IF_SERIES(pbpctl_dev->subdevice))
4275  pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4276 
4277  if (BP10GB_IF_SERIES(pbpctl_dev->subdevice)) {
4278  pbpctl_dev->bp_caps &= ~(TX_CTL_CAP | TX_STATUS_CAP);
4279  }
4280  pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4281  if (pbpctl_dev_m != NULL) {
4282  int cap_reg = 0;
4283  if (pbpctl_dev_m->bp_ext_ver >= 0x9) {
4284  cap_reg = get_bp_prod_caps(pbpctl_dev_m);
4285  if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
4286  DISC_PORT_SUPPORT_MASK)
4287  pbpctl_dev->bp_caps |=
4288  (TX_CTL_CAP | TX_STATUS_CAP);
4289  pbpctl_dev->bp_caps_ex |= DISC_PORT_CAP_EX;
4290  }
4291  }
4292 }
4293 
4294 int bypass_off_init(bpctl_dev_t *pbpctl_dev)
4295 {
4296  int ret = 0;
4297 
4298  if ((ret = cmnd_on(pbpctl_dev)) < 0)
4299  return ret;
4300  if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4301  return dis_bypass_cap(pbpctl_dev);
4302  wdt_off(pbpctl_dev);
4303  if (pbpctl_dev->bp_caps & BP_CAP)
4304  bypass_off(pbpctl_dev);
4305  if (pbpctl_dev->bp_caps & TAP_CAP)
4306  tap_off(pbpctl_dev);
4307  cmnd_off(pbpctl_dev);
4308  return 0;
4309 }
4310 
4311 void remove_bypass_wd_auto(bpctl_dev_t *pbpctl_dev)
4312 {
4313 #ifdef BP_SELF_TEST
4314  bpctl_dev_t *pbpctl_dev_sl = NULL;
4315 #endif
4316 
4317  if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4318 
4319  del_timer_sync(&pbpctl_dev->bp_timer);
4320 #ifdef BP_SELF_TEST
4321  pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
4322 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31))
4323  if (pbpctl_dev_sl && (pbpctl_dev_sl->ndev)
4324  && (pbpctl_dev_sl->ndev->hard_start_xmit)
4325  && (pbpctl_dev_sl->hard_start_xmit_save)) {
4326  rtnl_lock();
4327  pbpctl_dev_sl->ndev->hard_start_xmit =
4328  pbpctl_dev_sl->hard_start_xmit_save;
4329  rtnl_unlock();
4330  }
4331 #else
4332  if (pbpctl_dev_sl && (pbpctl_dev_sl->ndev)) {
4333  if ((pbpctl_dev_sl->ndev->netdev_ops)
4334  && (pbpctl_dev_sl->old_ops)) {
4335  rtnl_lock();
4336  pbpctl_dev_sl->ndev->netdev_ops =
4337  pbpctl_dev_sl->old_ops;
4338  pbpctl_dev_sl->old_ops = NULL;
4339 
4340  rtnl_unlock();
4341 
4342  }
4343 
4344  }
4345 
4346 #endif
4347 #endif
4348  }
4349 
4350 }
4351 
4352 int init_bypass_wd_auto(bpctl_dev_t *pbpctl_dev)
4353 {
4354  if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4355  init_timer(&pbpctl_dev->bp_timer);
4356  pbpctl_dev->bp_timer.function = &wd_reset_timer;
4357  pbpctl_dev->bp_timer.data = (unsigned long)pbpctl_dev;
4358  return 1;
4359  }
4360  return BP_NOT_CAP;
4361 }
4362 
4363 #ifdef BP_SELF_TEST
4364 int bp_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
4365 {
4366  bpctl_dev_t *pbpctl_dev = NULL, *pbpctl_dev_m = NULL;
4367  int idx_dev = 0;
4368  struct ethhdr *eth = (struct ethhdr *)skb->data;
4369 
4370  for (idx_dev = 0;
4371  ((bpctl_dev_arr[idx_dev].ndev != NULL) && (idx_dev < device_num));
4372  idx_dev++) {
4373  if (bpctl_dev_arr[idx_dev].ndev == dev) {
4374  pbpctl_dev = &bpctl_dev_arr[idx_dev];
4375  break;
4376  }
4377  }
4378  if (!pbpctl_dev)
4379  return 1;
4380  if ((htons(ETH_P_BPTEST) == eth->h_proto)) {
4381 
4382  pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4383  if (pbpctl_dev_m) {
4384 
4385  if (bypass_status(pbpctl_dev_m)) {
4386  cmnd_on(pbpctl_dev_m);
4387  bypass_off(pbpctl_dev_m);
4388  cmnd_off(pbpctl_dev_m);
4389  }
4390  wdt_timer_reload(pbpctl_dev_m);
4391  }
4392  dev_kfree_skb_irq(skb);
4393  return 0;
4394  }
4395  return pbpctl_dev->hard_start_xmit_save(skb, dev);
4396 }
4397 #endif
4398 
4399 int set_bypass_wd_auto(bpctl_dev_t *pbpctl_dev, unsigned int param)
4400 {
4401  if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4402  if (pbpctl_dev->reset_time != param) {
4403  if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4404  pbpctl_dev->reset_time =
4405  (param <
4406  WDT_AUTO_MIN_INT) ? WDT_AUTO_MIN_INT :
4407  param;
4408  else
4409  pbpctl_dev->reset_time = param;
4410  if (param)
4411  mod_timer(&pbpctl_dev->bp_timer, jiffies);
4412  }
4413  return 0;
4414  }
4415  return BP_NOT_CAP;
4416 }
4417 
4418 int get_bypass_wd_auto(bpctl_dev_t *pbpctl_dev)
4419 {
4420 
4421  if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4422  return pbpctl_dev->reset_time;
4423  }
4424  return BP_NOT_CAP;
4425 }
4426 
4427 #ifdef BP_SELF_TEST
4428 
4429 int set_bp_self_test(bpctl_dev_t *pbpctl_dev, unsigned int param)
4430 {
4431  bpctl_dev_t *pbpctl_dev_sl = NULL;
4432 
4433  if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4434  pbpctl_dev->bp_self_test_flag = param == 0 ? 0 : 1;
4435  pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
4436 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31))
4437  if ((pbpctl_dev_sl->ndev) &&
4438  (pbpctl_dev_sl->ndev->hard_start_xmit)) {
4439  rtnl_lock();
4440  if (pbpctl_dev->bp_self_test_flag == 1) {
4441 
4442  pbpctl_dev_sl->hard_start_xmit_save =
4443  pbpctl_dev_sl->ndev->hard_start_xmit;
4444  pbpctl_dev_sl->ndev->hard_start_xmit =
4445  bp_hard_start_xmit;
4446  } else if (pbpctl_dev_sl->hard_start_xmit_save) {
4447  pbpctl_dev_sl->ndev->hard_start_xmit =
4448  pbpctl_dev_sl->hard_start_xmit_save;
4449  }
4450  rtnl_unlock();
4451  }
4452 #else
4453  if ((pbpctl_dev_sl->ndev) && (pbpctl_dev_sl->ndev->netdev_ops)) {
4454  rtnl_lock();
4455  if (pbpctl_dev->bp_self_test_flag == 1) {
4456 
4457  pbpctl_dev_sl->old_ops =
4458  pbpctl_dev_sl->ndev->netdev_ops;
4459  pbpctl_dev_sl->new_ops =
4460  *pbpctl_dev_sl->old_ops;
4461  pbpctl_dev_sl->new_ops.ndo_start_xmit =
4462  bp_hard_start_xmit;
4463  pbpctl_dev_sl->ndev->netdev_ops =
4464  &pbpctl_dev_sl->new_ops;
4465 
4466  } else if (pbpctl_dev_sl->old_ops) {
4467  pbpctl_dev_sl->ndev->netdev_ops =
4468  pbpctl_dev_sl->old_ops;
4469  pbpctl_dev_sl->old_ops = NULL;
4470  }
4471  rtnl_unlock();
4472  }
4473 #endif
4474 
4475  set_bypass_wd_auto(pbpctl_dev, param);
4476  return 0;
4477  }
4478  return BP_NOT_CAP;
4479 }
4480 
4481 int get_bp_self_test(bpctl_dev_t *pbpctl_dev)
4482 {
4483 
4484  if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4485  if (pbpctl_dev->bp_self_test_flag == 1)
4486  return pbpctl_dev->reset_time;
4487  else
4488  return 0;
4489  }
4490  return BP_NOT_CAP;
4491 }
4492 
4493 #endif
4494 
4495 /**************************************************************/
4496 /************************* API ********************************/
4497 /**************************************************************/
4498 
4499 int is_bypass_fn(bpctl_dev_t *pbpctl_dev)
4500 {
4501  if (!pbpctl_dev)
4502  return -1;
4503 
4504  return (((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) ? 1 : 0);
4505 }
4506 
4507 int set_bypass_fn(bpctl_dev_t *pbpctl_dev, int bypass_mode)
4508 {
4509  int ret = 0;
4510 
4511  if (!(pbpctl_dev->bp_caps & BP_CAP))
4512  return BP_NOT_CAP;
4513  if ((ret = cmnd_on(pbpctl_dev)) < 0)
4514  return ret;
4515  if (!bypass_mode)
4516  ret = bypass_off(pbpctl_dev);
4517  else
4518  ret = bypass_on(pbpctl_dev);
4519  cmnd_off(pbpctl_dev);
4520 
4521  return ret;
4522 }
4523 
4524 int get_bypass_fn(bpctl_dev_t *pbpctl_dev)
4525 {
4526  return bypass_status(pbpctl_dev);
4527 }
4528 
4529 int get_bypass_change_fn(bpctl_dev_t *pbpctl_dev)
4530 {
4531  if (!pbpctl_dev)
4532  return -1;
4533 
4534  return bypass_change_status(pbpctl_dev);
4535 }
4536 
4537 int set_dis_bypass_fn(bpctl_dev_t *pbpctl_dev, int dis_param)
4538 {
4539  int ret = 0;
4540  if (!pbpctl_dev)
4541  return -1;
4542 
4543  if (!(pbpctl_dev->bp_caps & BP_DIS_CAP))
4544  return BP_NOT_CAP;
4545  if ((ret = cmnd_on(pbpctl_dev)) < 0)
4546  return ret;
4547  if (dis_param)
4548  ret = dis_bypass_cap(pbpctl_dev);
4549  else
4550  ret = en_bypass_cap(pbpctl_dev);
4551  cmnd_off(pbpctl_dev);
4552  return ret;
4553 }
4554 
4555 int get_dis_bypass_fn(bpctl_dev_t *pbpctl_dev)
4556 {
4557  if (!pbpctl_dev)
4558  return -1;
4559 
4560  return dis_bypass_cap_status(pbpctl_dev);
4561 }
4562 
4563 int set_bypass_pwoff_fn(bpctl_dev_t *pbpctl_dev, int bypass_mode)
4564 {
4565  int ret = 0;
4566  if (!pbpctl_dev)
4567  return -1;
4568 
4569  if (!(pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP))
4570  return BP_NOT_CAP;
4571  if ((ret = cmnd_on(pbpctl_dev)) < 0)
4572  return ret;
4573  if (bypass_mode)
4574  ret = bypass_state_pwroff(pbpctl_dev);
4575  else
4576  ret = normal_state_pwroff(pbpctl_dev);
4577  cmnd_off(pbpctl_dev);
4578  return ret;
4579 }
4580 
4581 int get_bypass_pwoff_fn(bpctl_dev_t *pbpctl_dev)
4582 {
4583  if (!pbpctl_dev)
4584  return -1;
4585 
4586  return default_pwroff_status(pbpctl_dev);
4587 }
4588 
4589 int set_bypass_pwup_fn(bpctl_dev_t *pbpctl_dev, int bypass_mode)
4590 {
4591  int ret = 0;
4592  if (!pbpctl_dev)
4593  return -1;
4594 
4595  if (!(pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP))
4596  return BP_NOT_CAP;
4597  if ((ret = cmnd_on(pbpctl_dev)) < 0)
4598  return ret;
4599  if (bypass_mode)
4600  ret = bypass_state_pwron(pbpctl_dev);
4601  else
4602  ret = normal_state_pwron(pbpctl_dev);
4603  cmnd_off(pbpctl_dev);
4604  return ret;
4605 }
4606 
4607 int get_bypass_pwup_fn(bpctl_dev_t *pbpctl_dev)
4608 {
4609  if (!pbpctl_dev)
4610  return -1;
4611 
4612  return default_pwron_status(pbpctl_dev);
4613 }
4614 
4615 int set_bypass_wd_fn(bpctl_dev_t *pbpctl_dev, int timeout)
4616 {
4617  int ret = 0;
4618  if (!pbpctl_dev)
4619  return -1;
4620 
4621  if (!(pbpctl_dev->bp_caps & WD_CTL_CAP))
4622  return BP_NOT_CAP;
4623 
4624  if ((ret = cmnd_on(pbpctl_dev)) < 0)
4625  return ret;
4626  if (!timeout)
4627  ret = wdt_off(pbpctl_dev);
4628  else {
4629  wdt_on(pbpctl_dev, timeout);
4630  ret = pbpctl_dev->bypass_timer_interval;
4631  }
4632  cmnd_off(pbpctl_dev);
4633  return ret;
4634 }
4635 
4636 int get_bypass_wd_fn(bpctl_dev_t *pbpctl_dev, int *timeout)
4637 {
4638  if (!pbpctl_dev)
4639  return -1;
4640 
4641  return wdt_programmed(pbpctl_dev, timeout);
4642 }
4643 
4644 int get_wd_expire_time_fn(bpctl_dev_t *pbpctl_dev, int *time_left)
4645 {
4646  if (!pbpctl_dev)
4647  return -1;
4648 
4649  return wdt_timer(pbpctl_dev, time_left);
4650 }
4651 
4652 int reset_bypass_wd_timer_fn(bpctl_dev_t *pbpctl_dev)
4653 {
4654  if (!pbpctl_dev)
4655  return -1;
4656 
4657  return wdt_timer_reload(pbpctl_dev);
4658 }
4659 
4660 int get_wd_set_caps_fn(bpctl_dev_t *pbpctl_dev)
4661 {
4662  int bp_status = 0;
4663 
4664  unsigned int step_value = TIMEOUT_MAX_STEP + 1, bit_cnt = 0;
4665  if (!pbpctl_dev)
4666  return -1;
4667 
4668  if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4669  return BP_NOT_CAP;
4670 
4671  while ((step_value >>= 1))
4672  bit_cnt++;
4673 
4674  if (is_bypass_fn(pbpctl_dev)) {
4675  bp_status =
4676  WD_STEP_COUNT_MASK(bit_cnt) | WDT_STEP_TIME |
4677  WD_MIN_TIME_MASK(TIMEOUT_UNIT / 100);
4678  } else
4679  return -1;
4680 
4681  return bp_status;
4682 }
4683 
4684 int set_std_nic_fn(bpctl_dev_t *pbpctl_dev, int nic_mode)
4685 {
4686  int ret = 0;
4687  if (!pbpctl_dev)
4688  return -1;
4689 
4690  if (!(pbpctl_dev->bp_caps & STD_NIC_CAP))
4691  return BP_NOT_CAP;
4692 
4693  if ((ret = cmnd_on(pbpctl_dev)) < 0)
4694  return ret;
4695  if (nic_mode)
4696  ret = std_nic_on(pbpctl_dev);
4697  else
4698  ret = std_nic_off(pbpctl_dev);
4699  cmnd_off(pbpctl_dev);
4700  return ret;
4701 }
4702 
4703 int get_std_nic_fn(bpctl_dev_t *pbpctl_dev)
4704 {
4705  if (!pbpctl_dev)
4706  return -1;
4707 
4708  return std_nic_status(pbpctl_dev);
4709 }
4710 
4711 int set_tap_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
4712 {
4713  if (!pbpctl_dev)
4714  return -1;
4715 
4716  if ((pbpctl_dev->bp_caps & TAP_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4717  if (!tap_mode)
4718  tap_off(pbpctl_dev);
4719  else
4720  tap_on(pbpctl_dev);
4721  cmnd_off(pbpctl_dev);
4722  return 0;
4723  }
4724  return BP_NOT_CAP;
4725 }
4726 
4727 int get_tap_fn(bpctl_dev_t *pbpctl_dev)
4728 {
4729  if (!pbpctl_dev)
4730  return -1;
4731 
4732  return tap_status(pbpctl_dev);
4733 }
4734 
4735 int set_tap_pwup_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
4736 {
4737  int ret = 0;
4738  if (!pbpctl_dev)
4739  return -1;
4740 
4741  if ((pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)
4742  && ((cmnd_on(pbpctl_dev)) >= 0)) {
4743  if (tap_mode)
4744  ret = tap_state_pwron(pbpctl_dev);
4745  else
4746  ret = normal_state_pwron(pbpctl_dev);
4747  cmnd_off(pbpctl_dev);
4748  } else
4749  ret = BP_NOT_CAP;
4750  return ret;
4751 }
4752 
4753 int get_tap_pwup_fn(bpctl_dev_t *pbpctl_dev)
4754 {
4755  int ret = 0;
4756  if (!pbpctl_dev)
4757  return -1;
4758 
4759  if ((ret = default_pwron_tap_status(pbpctl_dev)) < 0)
4760  return ret;
4761  return ((ret == 0) ? 1 : 0);
4762 }
4763 
4764 int get_tap_change_fn(bpctl_dev_t *pbpctl_dev)
4765 {
4766  if (!pbpctl_dev)
4767  return -1;
4768 
4769  return tap_change_status(pbpctl_dev);
4770 }
4771 
4772 int set_dis_tap_fn(bpctl_dev_t *pbpctl_dev, int dis_param)
4773 {
4774  int ret = 0;
4775  if (!pbpctl_dev)
4776  return -1;
4777 
4778  if ((pbpctl_dev->bp_caps & TAP_DIS_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4779  if (dis_param)
4780  ret = dis_tap_cap(pbpctl_dev);
4781  else
4782  ret = en_tap_cap(pbpctl_dev);
4783  cmnd_off(pbpctl_dev);
4784  return ret;
4785  } else
4786  return BP_NOT_CAP;
4787 }
4788 
4789 int get_dis_tap_fn(bpctl_dev_t *pbpctl_dev)
4790 {
4791  if (!pbpctl_dev)
4792  return -1;
4793 
4794  return dis_tap_cap_status(pbpctl_dev);
4795 }
4796 
4797 int set_disc_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
4798 {
4799  if (!pbpctl_dev)
4800  return -1;
4801 
4802  if ((pbpctl_dev->bp_caps & DISC_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4803  if (!disc_mode)
4804  disc_off(pbpctl_dev);
4805  else
4806  disc_on(pbpctl_dev);
4807  cmnd_off(pbpctl_dev);
4808 
4809  return BP_OK;
4810  }
4811  return BP_NOT_CAP;
4812 }
4813 
4814 int get_disc_fn(bpctl_dev_t *pbpctl_dev)
4815 {
4816  int ret = 0;
4817  if (!pbpctl_dev)
4818  return -1;
4819 
4820  ret = disc_status(pbpctl_dev);
4821 
4822  return ret;
4823 }
4824 
4825 int set_disc_pwup_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
4826 {
4827  int ret = 0;
4828  if (!pbpctl_dev)
4829  return -1;
4830 
4831  if ((pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP)
4832  && ((cmnd_on(pbpctl_dev)) >= 0)) {
4833  if (disc_mode)
4834  ret = disc_state_pwron(pbpctl_dev);
4835  else
4836  ret = normal_state_pwron(pbpctl_dev);
4837  cmnd_off(pbpctl_dev);
4838  } else
4839  ret = BP_NOT_CAP;
4840  return ret;
4841 }
4842 
4843 int get_disc_pwup_fn(bpctl_dev_t *pbpctl_dev)
4844 {
4845  int ret = 0;
4846  if (!pbpctl_dev)
4847  return -1;
4848 
4849  ret = default_pwron_disc_status(pbpctl_dev);
4850  return (ret == 0 ? 1 : (ret < 0 ? BP_NOT_CAP : 0));
4851 }
4852 
4853 int get_disc_change_fn(bpctl_dev_t *pbpctl_dev)
4854 {
4855  int ret = 0;
4856  if (!pbpctl_dev)
4857  return -1;
4858 
4859  ret = disc_change_status(pbpctl_dev);
4860  return ret;
4861 }
4862 
4863 int set_dis_disc_fn(bpctl_dev_t *pbpctl_dev, int dis_param)
4864 {
4865  int ret = 0;
4866  if (!pbpctl_dev)
4867  return -1;
4868 
4869  if ((pbpctl_dev->bp_caps & DISC_DIS_CAP)
4870  && ((cmnd_on(pbpctl_dev)) >= 0)) {
4871  if (dis_param)
4872  ret = dis_disc_cap(pbpctl_dev);
4873  else
4874  ret = en_disc_cap(pbpctl_dev);
4875  cmnd_off(pbpctl_dev);
4876  return ret;
4877  } else
4878  return BP_NOT_CAP;
4879 }
4880 
4881 int get_dis_disc_fn(bpctl_dev_t *pbpctl_dev)
4882 {
4883  int ret = 0;
4884  if (!pbpctl_dev)
4885  return -1;
4886 
4887  ret = dis_disc_cap_status(pbpctl_dev);
4888 
4889  return ret;
4890 }
4891 
4892 int set_disc_port_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
4893 {
4894  int ret = BP_NOT_CAP;
4895  if (!pbpctl_dev)
4896  return -1;
4897 
4898  if (!disc_mode)
4899  ret = disc_port_off(pbpctl_dev);
4900  else
4901  ret = disc_port_on(pbpctl_dev);
4902 
4903  return ret;
4904 }
4905 
4906 int get_disc_port_fn(bpctl_dev_t *pbpctl_dev)
4907 {
4908  if (!pbpctl_dev)
4909  return -1;
4910 
4911  return disc_port_status(pbpctl_dev);
4912 }
4913 
4914 int set_disc_port_pwup_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
4915 {
4916  int ret = BP_NOT_CAP;
4917  if (!pbpctl_dev)
4918  return -1;
4919 
4920  if (!disc_mode)
4921  ret = normal_port_state_pwron(pbpctl_dev);
4922  else
4923  ret = disc_port_state_pwron(pbpctl_dev);
4924 
4925  return ret;
4926 }
4927 
4928 int get_disc_port_pwup_fn(bpctl_dev_t *pbpctl_dev)
4929 {
4930  int ret = 0;
4931  if (!pbpctl_dev)
4932  return -1;
4933 
4934  if ((ret = default_pwron_disc_port_status(pbpctl_dev)) < 0)
4935  return ret;
4936  return ((ret == 0) ? 1 : 0);
4937 }
4938 
4939 int get_wd_exp_mode_fn(bpctl_dev_t *pbpctl_dev)
4940 {
4941  if (!pbpctl_dev)
4942  return -1;
4943 
4944  return wdt_exp_mode_status(pbpctl_dev);
4945 }
4946 
4947 int set_wd_exp_mode_fn(bpctl_dev_t *pbpctl_dev, int param)
4948 {
4949  if (!pbpctl_dev)
4950  return -1;
4951 
4952  return wdt_exp_mode(pbpctl_dev, param);
4953 }
4954 
4955 int reset_cont_fn(bpctl_dev_t *pbpctl_dev)
4956 {
4957  int ret = 0;
4958  if (!pbpctl_dev)
4959  return -1;
4960 
4961  if ((ret = cmnd_on(pbpctl_dev)) < 0)
4962  return ret;
4963  return reset_cont(pbpctl_dev);
4964 }
4965 
4966 int set_tx_fn(bpctl_dev_t *pbpctl_dev, int tx_state)
4967 {
4968 
4969  bpctl_dev_t *pbpctl_dev_b = NULL;
4970  if (!pbpctl_dev)
4971  return -1;
4972 
4973  if ((pbpctl_dev->bp_caps & TPL_CAP) &&
4974  (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
4975  if ((pbpctl_dev->bp_tpl_flag))
4976  return BP_NOT_CAP;
4977  } else if ((pbpctl_dev_b = get_master_port_fn(pbpctl_dev))) {
4978  if ((pbpctl_dev_b->bp_caps & TPL_CAP) &&
4979  (pbpctl_dev_b->bp_tpl_flag))
4980  return BP_NOT_CAP;
4981  }
4982  return set_tx(pbpctl_dev, tx_state);
4983 }
4984 
4985 int set_bp_force_link_fn(int dev_num, int tx_state)
4986 {
4987  static bpctl_dev_t *bpctl_dev_curr;
4988 
4989  if ((dev_num < 0) || (dev_num > device_num)
4990  || (bpctl_dev_arr[dev_num].pdev == NULL))
4991  return -1;
4992  bpctl_dev_curr = &bpctl_dev_arr[dev_num];
4993 
4994  return set_bp_force_link(bpctl_dev_curr, tx_state);
4995 }
4996 
4997 int set_wd_autoreset_fn(bpctl_dev_t *pbpctl_dev, int param)
4998 {
4999  if (!pbpctl_dev)
5000  return -1;
5001 
5002  return set_bypass_wd_auto(pbpctl_dev, param);
5003 }
5004 
5005 int get_wd_autoreset_fn(bpctl_dev_t *pbpctl_dev)
5006 {
5007  if (!pbpctl_dev)
5008  return -1;
5009 
5010  return get_bypass_wd_auto(pbpctl_dev);
5011 }
5012 
5013 #ifdef BP_SELF_TEST
5014 int set_bp_self_test_fn(bpctl_dev_t *pbpctl_dev, int param)
5015 {
5016  if (!pbpctl_dev)
5017  return -1;
5018 
5019  return set_bp_self_test(pbpctl_dev, param);
5020 }
5021 
5022 int get_bp_self_test_fn(bpctl_dev_t *pbpctl_dev)
5023 {
5024  if (!pbpctl_dev)
5025  return -1;
5026 
5027  return get_bp_self_test(pbpctl_dev);
5028 }
5029 
5030 #endif
5031 
5032 int get_bypass_caps_fn(bpctl_dev_t *pbpctl_dev)
5033 {
5034  if (!pbpctl_dev)
5035  return -1;
5036 
5037  return pbpctl_dev->bp_caps;
5038 
5039 }
5040 
5041 int get_bypass_slave_fn(bpctl_dev_t *pbpctl_dev, bpctl_dev_t **pbpctl_dev_out)
5042 {
5043  int idx_dev = 0;
5044  if (!pbpctl_dev)
5045  return -1;
5046 
5047  if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) {
5048  for (idx_dev = 0;
5049  ((bpctl_dev_arr[idx_dev].pdev != NULL)
5050  && (idx_dev < device_num)); idx_dev++) {
5051  if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus)
5052  && (bpctl_dev_arr[idx_dev].slot ==
5053  pbpctl_dev->slot)) {
5054  if ((pbpctl_dev->func == 0)
5055  && (bpctl_dev_arr[idx_dev].func == 1)) {
5056  *pbpctl_dev_out =
5057  &bpctl_dev_arr[idx_dev];
5058  return 1;
5059  }
5060  if ((pbpctl_dev->func == 2) &&
5061  (bpctl_dev_arr[idx_dev].func == 3)) {
5062  *pbpctl_dev_out =
5063  &bpctl_dev_arr[idx_dev];
5064  return 1;
5065  }
5066  }
5067  }
5068  return -1;
5069  } else
5070  return 0;
5071 }
5072 
5073 int is_bypass(bpctl_dev_t *pbpctl_dev)
5074 {
5075  if (!pbpctl_dev)
5076  return -1;
5077 
5078  if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2))
5079  return 1;
5080  else
5081  return 0;
5082 }
5083 
5084 int get_tx_fn(bpctl_dev_t *pbpctl_dev)
5085 {
5086  bpctl_dev_t *pbpctl_dev_b = NULL;
5087  if (!pbpctl_dev)
5088  return -1;
5089 
5090  if ((pbpctl_dev->bp_caps & TPL_CAP) &&
5091  (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
5092  if ((pbpctl_dev->bp_tpl_flag))
5093  return BP_NOT_CAP;
5094  } else if ((pbpctl_dev_b = get_master_port_fn(pbpctl_dev))) {
5095  if ((pbpctl_dev_b->bp_caps & TPL_CAP) &&
5096  (pbpctl_dev_b->bp_tpl_flag))
5097  return BP_NOT_CAP;
5098  }
5099  return tx_status(pbpctl_dev);
5100 }
5101 
5102 int get_bp_force_link_fn(int dev_num)
5103 {
5104  static bpctl_dev_t *bpctl_dev_curr;
5105 
5106  if ((dev_num < 0) || (dev_num > device_num)
5107  || (bpctl_dev_arr[dev_num].pdev == NULL))
5108  return -1;
5109  bpctl_dev_curr = &bpctl_dev_arr[dev_num];
5110 
5111  return bp_force_link_status(bpctl_dev_curr);
5112 }
5113 
5114 static int get_bypass_link_status(bpctl_dev_t *pbpctl_dev)
5115 {
5116  if (!pbpctl_dev)
5117  return -1;
5118 
5119  if (pbpctl_dev->media_type == bp_fiber)
5120  return ((BPCTL_READ_REG(pbpctl_dev, CTRL) &
5121  BPCTLI_CTRL_SWDPIN1));
5122  else
5123  return ((BPCTL_READ_REG(pbpctl_dev, STATUS) &
5124  BPCTLI_STATUS_LU));
5125 
5126 }
5127 
5128 static void bp_tpl_timer_fn(unsigned long param)
5129 {
5130  bpctl_dev_t *pbpctl_dev = (bpctl_dev_t *) param;
5131  uint32_t link1, link2;
5132  bpctl_dev_t *pbpctl_dev_b = NULL;
5133 
5134  if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
5135  return;
5136 
5137  if (!pbpctl_dev->bp_tpl_flag) {
5138  set_tx(pbpctl_dev_b, 1);
5139  set_tx(pbpctl_dev, 1);
5140  return;
5141  }
5142  link1 = get_bypass_link_status(pbpctl_dev);
5143 
5144  link2 = get_bypass_link_status(pbpctl_dev_b);
5145  if ((link1) && (tx_status(pbpctl_dev))) {
5146  if ((!link2) && (tx_status(pbpctl_dev_b))) {
5147  set_tx(pbpctl_dev, 0);
5148  } else if (!tx_status(pbpctl_dev_b)) {
5149  set_tx(pbpctl_dev_b, 1);
5150  }
5151  } else if ((!link1) && (tx_status(pbpctl_dev))) {
5152  if ((link2) && (tx_status(pbpctl_dev_b))) {
5153  set_tx(pbpctl_dev_b, 0);
5154  }
5155  } else if ((link1) && (!tx_status(pbpctl_dev))) {
5156  if ((link2) && (tx_status(pbpctl_dev_b))) {
5157  set_tx(pbpctl_dev, 1);
5158  }
5159  } else if ((!link1) && (!tx_status(pbpctl_dev))) {
5160  if ((link2) && (tx_status(pbpctl_dev_b))) {
5161  set_tx(pbpctl_dev, 1);
5162  }
5163  }
5164 
5165  mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + BP_LINK_MON_DELAY * HZ);
5166 }
5167 
5168 void remove_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev)
5169 {
5170  bpctl_dev_t *pbpctl_dev_b = NULL;
5171  if (!pbpctl_dev)
5172  return;
5173  pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5174 
5175  if (pbpctl_dev->bp_caps & TPL_CAP) {
5176  del_timer_sync(&pbpctl_dev->bp_tpl_timer);
5177  pbpctl_dev->bp_tpl_flag = 0;
5178  pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5179  if (pbpctl_dev_b)
5180  set_tx(pbpctl_dev_b, 1);
5181  set_tx(pbpctl_dev, 1);
5182  }
5183  return;
5184 }
5185 
5186 int init_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev)
5187 {
5188  if (!pbpctl_dev)
5189  return -1;
5190  if (pbpctl_dev->bp_caps & TPL_CAP) {
5191  init_timer(&pbpctl_dev->bp_tpl_timer);
5192  pbpctl_dev->bp_tpl_timer.function = &bp_tpl_timer_fn;
5193  pbpctl_dev->bp_tpl_timer.data = (unsigned long)pbpctl_dev;
5194  return BP_OK;
5195  }
5196  return BP_NOT_CAP;
5197 }
5198 
5199 int set_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev, unsigned int param)
5200 {
5201  if (!pbpctl_dev)
5202  return -1;
5203  if (pbpctl_dev->bp_caps & TPL_CAP) {
5204  if ((param) && (!pbpctl_dev->bp_tpl_flag)) {
5205  pbpctl_dev->bp_tpl_flag = param;
5206  mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + 1);
5207  return BP_OK;
5208  };
5209  if ((!param) && (pbpctl_dev->bp_tpl_flag))
5210  remove_bypass_tpl_auto(pbpctl_dev);
5211 
5212  return BP_OK;
5213  }
5214  return BP_NOT_CAP;
5215 }
5216 
5217 int get_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev)
5218 {
5219  if (!pbpctl_dev)
5220  return -1;
5221  if (pbpctl_dev->bp_caps & TPL_CAP) {
5222  return pbpctl_dev->bp_tpl_flag;
5223  }
5224  return BP_NOT_CAP;
5225 }
5226 
5227 int set_tpl_fn(bpctl_dev_t *pbpctl_dev, int tpl_mode)
5228 {
5229 
5230  bpctl_dev_t *pbpctl_dev_b = NULL;
5231  if (!pbpctl_dev)
5232  return -1;
5233 
5234  pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5235 
5236  if (pbpctl_dev->bp_caps & TPL_CAP) {
5237  if (tpl_mode) {
5238  if ((pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
5239  set_tx(pbpctl_dev_b, 1);
5240  set_tx(pbpctl_dev, 1);
5241  }
5242  if ((TPL_IF_SERIES(pbpctl_dev->subdevice)) ||
5243  (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)) {
5244  pbpctl_dev->bp_tpl_flag = tpl_mode;
5245  if (!tpl_mode)
5246  tpl_hw_off(pbpctl_dev);
5247  else
5248  tpl_hw_on(pbpctl_dev);
5249  } else
5250  set_bypass_tpl_auto(pbpctl_dev, tpl_mode);
5251  return 0;
5252  }
5253  return BP_NOT_CAP;
5254 }
5255 
5256 int get_tpl_fn(bpctl_dev_t *pbpctl_dev)
5257 {
5258  int ret = BP_NOT_CAP;
5259  if (!pbpctl_dev)
5260  return -1;
5261 
5262  if (pbpctl_dev->bp_caps & TPL_CAP) {
5263  if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)
5264  return tpl2_flag_status(pbpctl_dev);
5265  ret = pbpctl_dev->bp_tpl_flag;
5266  }
5267  return ret;
5268 }
5269 
5270 int set_bp_wait_at_pwup_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
5271 {
5272  if (!pbpctl_dev)
5273  return -1;
5274 
5275  if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
5276  /* bp_lock(pbp_device_block); */
5277  cmnd_on(pbpctl_dev);
5278  if (!tap_mode)
5279  bp_wait_at_pwup_dis(pbpctl_dev);
5280  else
5281  bp_wait_at_pwup_en(pbpctl_dev);
5282  cmnd_off(pbpctl_dev);
5283 
5284  /* bp_unlock(pbp_device_block); */
5285  return BP_OK;
5286  }
5287  return BP_NOT_CAP;
5288 }
5289 
5290 int get_bp_wait_at_pwup_fn(bpctl_dev_t *pbpctl_dev)
5291 {
5292  int ret = 0;
5293  if (!pbpctl_dev)
5294  return -1;
5295 
5296  /* bp_lock(pbp_device_block); */
5297  ret = bp_wait_at_pwup_status(pbpctl_dev);
5298  /* bp_unlock(pbp_device_block); */
5299 
5300  return ret;
5301 }
5302 
5303 int set_bp_hw_reset_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
5304 {
5305  if (!pbpctl_dev)
5306  return -1;
5307 
5308  if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
5309  /* bp_lock(pbp_device_block); */
5310  cmnd_on(pbpctl_dev);
5311 
5312  if (!tap_mode)
5313  bp_hw_reset_dis(pbpctl_dev);
5314  else
5315  bp_hw_reset_en(pbpctl_dev);
5316  cmnd_off(pbpctl_dev);
5317  /* bp_unlock(pbp_device_block); */
5318  return BP_OK;
5319  }
5320  return BP_NOT_CAP;
5321 }
5322 
5323 int get_bp_hw_reset_fn(bpctl_dev_t *pbpctl_dev)
5324 {
5325  int ret = 0;
5326  if (!pbpctl_dev)
5327  return -1;
5328 
5329  /* bp_lock(pbp_device_block); */
5330  ret = bp_hw_reset_status(pbpctl_dev);
5331 
5332  /* bp_unlock(pbp_device_block); */
5333 
5334  return ret;
5335 }
5336 
5337 
5338 int get_bypass_info_fn(bpctl_dev_t *pbpctl_dev, char *dev_name,
5339  char *add_param)
5340 {
5341  if (!pbpctl_dev)
5342  return -1;
5343  if (!is_bypass_fn(pbpctl_dev))
5344  return -1;
5345  strcpy(dev_name, pbpctl_dev->name);
5346  *add_param = pbpctl_dev->bp_fw_ver;
5347  return 0;
5348 }
5349 
5350 int get_dev_idx_bsf(int bus, int slot, int func)
5351 {
5352  int idx_dev = 0;
5353  for (idx_dev = 0;
5354  ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5355  idx_dev++) {
5356  if ((bus == bpctl_dev_arr[idx_dev].bus)
5357  && (slot == bpctl_dev_arr[idx_dev].slot)
5358  && (func == bpctl_dev_arr[idx_dev].func))
5359 
5360  return idx_dev;
5361  }
5362  return -1;
5363 }
5364 
5365 static void str_low(char *str)
5366 {
5367  int i;
5368 
5369  for (i = 0; i < strlen(str); i++)
5370  if ((str[i] >= 65) && (str[i] <= 90))
5371  str[i] += 32;
5372 }
5373 
5374 static unsigned long str_to_hex(char *p)
5375 {
5376  unsigned long hex = 0;
5377  unsigned long length = strlen(p), shift = 0;
5378  unsigned char dig = 0;
5379 
5380  str_low(p);
5381  length = strlen(p);
5382 
5383  if (length == 0)
5384  return 0;
5385 
5386  do {
5387  dig = p[--length];
5388  dig = dig < 'a' ? (dig - '0') : (dig - 'a' + 0xa);
5389  hex |= (dig << shift);
5390  shift += 4;
5391  } while (length);
5392  return hex;
5393 }
5394 
5395 static int get_dev_idx(int ifindex)
5396 {
5397  int idx_dev = 0;
5398 
5399  for (idx_dev = 0;
5400  ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5401  idx_dev++) {
5402  if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
5403  return idx_dev;
5404  }
5405 
5406  return -1;
5407 }
5408 
5409 static bpctl_dev_t *get_dev_idx_p(int ifindex)
5410 {
5411  int idx_dev = 0;
5412 
5413  for (idx_dev = 0;
5414  ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5415  idx_dev++) {
5416  if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
5417  return &bpctl_dev_arr[idx_dev];
5418  }
5419 
5420  return NULL;
5421 }
5422 
5423 static void if_scan_init(void)
5424 {
5425  int idx_dev = 0;
5426  struct net_device *dev;
5427  int ifindex;
5428  /* rcu_read_lock(); */
5429  /* rtnl_lock(); */
5430  /* rcu_read_lock(); */
5431 #if 1
5432 #if (LINUX_VERSION_CODE >= 0x020618)
5433  for_each_netdev(&init_net, dev)
5434 #elif (LINUX_VERSION_CODE >= 0x20616)
5435  for_each_netdev(dev)
5436 #else
5437  for (dev = dev_base; dev; dev = dev->next)
5438 #endif
5439  {
5440 
5441  struct ethtool_drvinfo drvinfo;
5442  char cbuf[32];
5443  char *buf = NULL;
5444  char res[10];
5445  int i = 0;
5446  int bus = 0, slot = 0, func = 0;
5447  ifindex = dev->ifindex;
5448 
5449  memset(res, 0, 10);
5450  memset(&drvinfo, 0, sizeof(struct ethtool_drvinfo));
5451 
5452  if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
5453  memset(&drvinfo, 0, sizeof(drvinfo));
5454  dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
5455  } else
5456  continue;
5457  if (!drvinfo.bus_info)
5458  continue;
5459  if (!strcmp(drvinfo.bus_info, "N/A"))
5460  continue;
5461  memcpy(&cbuf, drvinfo.bus_info, 32);
5462  buf = &cbuf[0];
5463 
5464  while (*buf++ != ':') ;
5465  for (i = 0; i < 10; i++, buf++) {
5466  if (*buf == ':')
5467  break;
5468  res[i] = *buf;
5469 
5470  }
5471  buf++;
5472  bus = str_to_hex(res);
5473  memset(res, 0, 10);
5474 
5475  for (i = 0; i < 10; i++, buf++) {
5476  if (*buf == '.')
5477  break;
5478  res[i] = *buf;
5479 
5480  }
5481  buf++;
5482  slot = str_to_hex(res);
5483  func = str_to_hex(buf);
5484  idx_dev = get_dev_idx_bsf(bus, slot, func);
5485 
5486  if (idx_dev != -1) {
5487 
5488  bpctl_dev_arr[idx_dev].ifindex = ifindex;
5489  bpctl_dev_arr[idx_dev].ndev = dev;
5490 
5491  }
5492 
5493  }
5494 #endif
5495  /* rtnl_unlock(); */
5496  /* rcu_read_unlock(); */
5497 
5498 }
5499 
5500 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
5501 static int device_ioctl(struct inode *inode, /* see include/linux/fs.h */
5502  struct file *file, /* ditto */
5503  unsigned int ioctl_num, /* number and param for ioctl */
5504  unsigned long ioctl_param)
5505 #else
5506 static long device_ioctl(struct file *file, /* ditto */
5507  unsigned int ioctl_num, /* number and param for ioctl */
5508  unsigned long ioctl_param)
5509 #endif
5510 {
5511  struct bpctl_cmd bpctl_cmd;
5512  int dev_idx = 0;
5513  bpctl_dev_t *pbpctl_dev_out;
5514  void __user *argp = (void __user *)ioctl_param;
5515  int ret = 0;
5516  unsigned long flags;
5517 
5518  static bpctl_dev_t *pbpctl_dev;
5519 
5520 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
5521  /* lock_kernel(); */
5522 #endif
5523  lock_bpctl();
5524  /* local_irq_save(flags); */
5525  /* if(!spin_trylock_irqsave(&bpvm_lock)){
5526  local_irq_restore(flags);
5527  unlock_bpctl();
5528  unlock_kernel();
5529  return -1;
5530  } */
5531  /* spin_lock_irqsave(&bpvm_lock, flags); */
5532 
5533 /*
5534 * Switch according to the ioctl called
5535 */
5536  if (ioctl_num == IOCTL_TX_MSG(IF_SCAN)) {
5537  if_scan_init();
5538  ret = SUCCESS;
5539  goto bp_exit;
5540  }
5541  if (copy_from_user(&bpctl_cmd, argp, sizeof(struct bpctl_cmd))) {
5542 
5543  ret = -EFAULT;
5544  goto bp_exit;
5545  }
5546 
5547  if (ioctl_num == IOCTL_TX_MSG(GET_DEV_NUM)) {
5548  bpctl_cmd.out_param[0] = device_num;
5549  if (copy_to_user
5550  (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
5551  ret = -EFAULT;
5552  goto bp_exit;
5553  }
5554  ret = SUCCESS;
5555  goto bp_exit;
5556 
5557  }
5558  /* lock_bpctl(); */
5559  /* preempt_disable(); */
5560  local_irq_save(flags);
5561  if (!spin_trylock(&bpvm_lock)) {
5562  local_irq_restore(flags);
5563  unlock_bpctl();
5564  return -1;
5565  }
5566 
5567 /* preempt_disable();
5568  rcu_read_lock();
5569  spin_lock_irqsave(&bpvm_lock, flags);
5570 */
5571  if ((bpctl_cmd.in_param[5]) ||
5572  (bpctl_cmd.in_param[6]) || (bpctl_cmd.in_param[7]))
5573  dev_idx = get_dev_idx_bsf(bpctl_cmd.in_param[5],
5574  bpctl_cmd.in_param[6],
5575  bpctl_cmd.in_param[7]);
5576  else if (bpctl_cmd.in_param[1] == 0)
5577  dev_idx = bpctl_cmd.in_param[0];
5578  else
5579  dev_idx = get_dev_idx(bpctl_cmd.in_param[1]);
5580 
5581  if (dev_idx < 0 || dev_idx > device_num) {
5582  /* unlock_bpctl();
5583  preempt_enable(); */
5584  ret = -EOPNOTSUPP;
5585  /* preempt_enable();
5586  rcu_read_unlock(); */
5587  spin_unlock_irqrestore(&bpvm_lock, flags);
5588  goto bp_exit;
5589  }
5590 
5591  bpctl_cmd.out_param[0] = bpctl_dev_arr[dev_idx].bus;
5592  bpctl_cmd.out_param[1] = bpctl_dev_arr[dev_idx].slot;
5593  bpctl_cmd.out_param[2] = bpctl_dev_arr[dev_idx].func;
5594  bpctl_cmd.out_param[3] = bpctl_dev_arr[dev_idx].ifindex;
5595 
5596  if ((bpctl_dev_arr[dev_idx].bp_10gb)
5597  && (!(bpctl_dev_arr[dev_idx].ifindex))) {
5598  printk("Please load network driver for %s adapter!\n",
5599  bpctl_dev_arr[dev_idx].name);
5600  bpctl_cmd.status = -1;
5601  ret = SUCCESS;
5602  /* preempt_enable(); */
5603  /* rcu_read_unlock(); */
5604  spin_unlock_irqrestore(&bpvm_lock, flags);
5605  goto bp_exit;
5606 
5607  }
5608  if ((bpctl_dev_arr[dev_idx].bp_10gb) && (bpctl_dev_arr[dev_idx].ndev)) {
5609  if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5610  if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5611  printk
5612  ("Please bring up network interfaces for %s adapter!\n",
5613  bpctl_dev_arr[dev_idx].name);
5614  bpctl_cmd.status = -1;
5615  ret = SUCCESS;
5616  /* preempt_enable(); */
5617  /* rcu_read_unlock(); */
5618  spin_unlock_irqrestore(&bpvm_lock, flags);
5619  goto bp_exit;
5620  }
5621 
5622  }
5623  }
5624 
5625  if ((dev_idx < 0) || (dev_idx > device_num)
5626  || (bpctl_dev_arr[dev_idx].pdev == NULL)) {
5627  bpctl_cmd.status = -1;
5628  goto bpcmd_exit;
5629  }
5630 
5631  pbpctl_dev = &bpctl_dev_arr[dev_idx];
5632 
5633  switch (ioctl_num) {
5634  case IOCTL_TX_MSG(SET_BYPASS_PWOFF):
5635  bpctl_cmd.status =
5636  set_bypass_pwoff_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5637  break;
5638 
5639  case IOCTL_TX_MSG(GET_BYPASS_PWOFF):
5640  bpctl_cmd.status = get_bypass_pwoff_fn(pbpctl_dev);
5641  break;
5642 
5643  case IOCTL_TX_MSG(SET_BYPASS_PWUP):
5644  bpctl_cmd.status =
5645  set_bypass_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5646  break;
5647 
5648  case IOCTL_TX_MSG(GET_BYPASS_PWUP):
5649  bpctl_cmd.status = get_bypass_pwup_fn(pbpctl_dev);
5650  break;
5651 
5652  case IOCTL_TX_MSG(SET_BYPASS_WD):
5653  bpctl_cmd.status =
5654  set_bypass_wd_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5655  break;
5656 
5657  case IOCTL_TX_MSG(GET_BYPASS_WD):
5658  bpctl_cmd.status =
5659  get_bypass_wd_fn(pbpctl_dev, (int *)&(bpctl_cmd.data[0]));
5660  break;
5661 
5662  case IOCTL_TX_MSG(GET_WD_EXPIRE_TIME):
5663  bpctl_cmd.status =
5664  get_wd_expire_time_fn(pbpctl_dev,
5665  (int *)&(bpctl_cmd.data[0]));
5666  break;
5667 
5668  case IOCTL_TX_MSG(RESET_BYPASS_WD_TIMER):
5669  bpctl_cmd.status = reset_bypass_wd_timer_fn(pbpctl_dev);
5670  break;
5671 
5672  case IOCTL_TX_MSG(GET_WD_SET_CAPS):
5673  bpctl_cmd.status = get_wd_set_caps_fn(pbpctl_dev);
5674  break;
5675 
5676  case IOCTL_TX_MSG(SET_STD_NIC):
5677  bpctl_cmd.status =
5678  set_std_nic_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5679  break;
5680 
5681  case IOCTL_TX_MSG(GET_STD_NIC):
5682  bpctl_cmd.status = get_std_nic_fn(pbpctl_dev);
5683  break;
5684 
5685  case IOCTL_TX_MSG(SET_TAP):
5686  bpctl_cmd.status =
5687  set_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5688  break;
5689 
5690  case IOCTL_TX_MSG(GET_TAP):
5691  bpctl_cmd.status = get_tap_fn(pbpctl_dev);
5692  break;
5693 
5694  case IOCTL_TX_MSG(GET_TAP_CHANGE):
5695  bpctl_cmd.status = get_tap_change_fn(pbpctl_dev);
5696  break;
5697 
5698  case IOCTL_TX_MSG(SET_DIS_TAP):
5699  bpctl_cmd.status =
5700  set_dis_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5701  break;
5702 
5703  case IOCTL_TX_MSG(GET_DIS_TAP):
5704  bpctl_cmd.status = get_dis_tap_fn(pbpctl_dev);
5705  break;
5706 
5707  case IOCTL_TX_MSG(SET_TAP_PWUP):
5708  bpctl_cmd.status =
5709  set_tap_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5710  break;
5711 
5712  case IOCTL_TX_MSG(GET_TAP_PWUP):
5713  bpctl_cmd.status = get_tap_pwup_fn(pbpctl_dev);
5714  break;
5715 
5716  case IOCTL_TX_MSG(SET_WD_EXP_MODE):
5717  bpctl_cmd.status =
5718  set_wd_exp_mode_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5719  break;
5720 
5721  case IOCTL_TX_MSG(GET_WD_EXP_MODE):
5722  bpctl_cmd.status = get_wd_exp_mode_fn(pbpctl_dev);
5723  break;
5724 
5725  case IOCTL_TX_MSG(GET_DIS_BYPASS):
5726  bpctl_cmd.status = get_dis_bypass_fn(pbpctl_dev);
5727  break;
5728 
5729  case IOCTL_TX_MSG(SET_DIS_BYPASS):
5730  bpctl_cmd.status =
5731  set_dis_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5732  break;
5733 
5734  case IOCTL_TX_MSG(GET_BYPASS_CHANGE):
5735  bpctl_cmd.status = get_bypass_change_fn(pbpctl_dev);
5736  break;
5737 
5738  case IOCTL_TX_MSG(GET_BYPASS):
5739  bpctl_cmd.status = get_bypass_fn(pbpctl_dev);
5740  break;
5741 
5742  case IOCTL_TX_MSG(SET_BYPASS):
5743  bpctl_cmd.status =
5744  set_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5745  break;
5746 
5747  case IOCTL_TX_MSG(GET_BYPASS_CAPS):
5748  bpctl_cmd.status = get_bypass_caps_fn(pbpctl_dev);
5749  /*preempt_enable(); */
5750  /*rcu_read_unlock();*/
5751  spin_unlock_irqrestore(&bpvm_lock, flags);
5752  if (copy_to_user
5753  (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
5754  /*unlock_bpctl(); */
5755  /*preempt_enable(); */
5756  ret = -EFAULT;
5757  goto bp_exit;
5758  }
5759  goto bp_exit;
5760 
5761  case IOCTL_TX_MSG(GET_BYPASS_SLAVE):
5762  bpctl_cmd.status =
5763  get_bypass_slave_fn(pbpctl_dev, &pbpctl_dev_out);
5764  if (bpctl_cmd.status == 1) {
5765  bpctl_cmd.out_param[4] = pbpctl_dev_out->bus;
5766  bpctl_cmd.out_param[5] = pbpctl_dev_out->slot;
5767  bpctl_cmd.out_param[6] = pbpctl_dev_out->func;
5768  bpctl_cmd.out_param[7] = pbpctl_dev_out->ifindex;
5769  }
5770  break;
5771 
5772  case IOCTL_TX_MSG(IS_BYPASS):
5773  bpctl_cmd.status = is_bypass(pbpctl_dev);
5774  break;
5775  case IOCTL_TX_MSG(SET_TX):
5776  bpctl_cmd.status = set_tx_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5777  break;
5778  case IOCTL_TX_MSG(GET_TX):
5779  bpctl_cmd.status = get_tx_fn(pbpctl_dev);
5780  break;
5781  case IOCTL_TX_MSG(SET_WD_AUTORESET):
5782  bpctl_cmd.status =
5783  set_wd_autoreset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5784 
5785  break;
5786  case IOCTL_TX_MSG(GET_WD_AUTORESET):
5787 
5788  bpctl_cmd.status = get_wd_autoreset_fn(pbpctl_dev);
5789  break;
5790  case IOCTL_TX_MSG(SET_DISC):
5791  bpctl_cmd.status =
5792  set_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5793  break;
5794  case IOCTL_TX_MSG(GET_DISC):
5795  bpctl_cmd.status = get_disc_fn(pbpctl_dev);
5796  break;
5797  case IOCTL_TX_MSG(GET_DISC_CHANGE):
5798  bpctl_cmd.status = get_disc_change_fn(pbpctl_dev);
5799  break;
5800  case IOCTL_TX_MSG(SET_DIS_DISC):
5801  bpctl_cmd.status =
5802  set_dis_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5803  break;
5804  case IOCTL_TX_MSG(GET_DIS_DISC):
5805  bpctl_cmd.status = get_dis_disc_fn(pbpctl_dev);
5806  break;
5807  case IOCTL_TX_MSG(SET_DISC_PWUP):
5808  bpctl_cmd.status =
5809  set_disc_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5810  break;
5811  case IOCTL_TX_MSG(GET_DISC_PWUP):
5812  bpctl_cmd.status = get_disc_pwup_fn(pbpctl_dev);
5813  break;
5814 
5815  case IOCTL_TX_MSG(GET_BYPASS_INFO):
5816 
5817  bpctl_cmd.status =
5818  get_bypass_info_fn(pbpctl_dev, (char *)&bpctl_cmd.data,
5819  (char *)&bpctl_cmd.out_param[4]);
5820  break;
5821 
5822  case IOCTL_TX_MSG(SET_TPL):
5823  bpctl_cmd.status =
5824  set_tpl_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5825  break;
5826 
5827  case IOCTL_TX_MSG(GET_TPL):
5828  bpctl_cmd.status = get_tpl_fn(pbpctl_dev);
5829  break;
5830  case IOCTL_TX_MSG(SET_BP_WAIT_AT_PWUP):
5831  bpctl_cmd.status =
5832  set_bp_wait_at_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5833  break;
5834 
5835  case IOCTL_TX_MSG(GET_BP_WAIT_AT_PWUP):
5836  bpctl_cmd.status = get_bp_wait_at_pwup_fn(pbpctl_dev);
5837  break;
5838  case IOCTL_TX_MSG(SET_BP_HW_RESET):
5839  bpctl_cmd.status =
5840  set_bp_hw_reset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5841  break;
5842 
5843  case IOCTL_TX_MSG(GET_BP_HW_RESET):
5844  bpctl_cmd.status = get_bp_hw_reset_fn(pbpctl_dev);
5845  break;
5846 #ifdef BP_SELF_TEST
5847  case IOCTL_TX_MSG(SET_BP_SELF_TEST):
5848  bpctl_cmd.status =
5849  set_bp_self_test_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5850 
5851  break;
5852  case IOCTL_TX_MSG(GET_BP_SELF_TEST):
5853  bpctl_cmd.status = get_bp_self_test_fn(pbpctl_dev);
5854  break;
5855 
5856 #endif
5857 #if 0
5858  case IOCTL_TX_MSG(SET_DISC_PORT):
5859  bpctl_cmd.status =
5860  set_disc_port_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5861  break;
5862 
5863  case IOCTL_TX_MSG(GET_DISC_PORT):
5864  bpctl_cmd.status = get_disc_port_fn(pbpctl_dev);
5865  break;
5866 
5867  case IOCTL_TX_MSG(SET_DISC_PORT_PWUP):
5868  bpctl_cmd.status =
5869  set_disc_port_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5870  break;
5871 
5872  case IOCTL_TX_MSG(GET_DISC_PORT_PWUP):
5873  bpctl_cmd.status = get_disc_port_pwup_fn(pbpctl_dev);
5874  break;
5875 #endif
5876  case IOCTL_TX_MSG(SET_BP_FORCE_LINK):
5877  bpctl_cmd.status =
5878  set_bp_force_link_fn(dev_idx, bpctl_cmd.in_param[2]);
5879  break;
5880 
5881  case IOCTL_TX_MSG(GET_BP_FORCE_LINK):
5882  bpctl_cmd.status = get_bp_force_link_fn(dev_idx);
5883  break;
5884 
5885  default:
5886  /* unlock_bpctl(); */
5887 
5888  ret = -EOPNOTSUPP;
5889  /* preempt_enable(); */
5890  /* rcu_read_unlock();*/
5891  spin_unlock_irqrestore(&bpvm_lock, flags);
5892  goto bp_exit;
5893  }
5894  /* unlock_bpctl(); */
5895  /* preempt_enable(); */
5896  bpcmd_exit:
5897  /* rcu_read_unlock(); */
5898  spin_unlock_irqrestore(&bpvm_lock, flags);
5899  if (copy_to_user(argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd)))
5900  ret = -EFAULT;
5901  ret = SUCCESS;
5902  bp_exit:
5903 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
5904  /* unlock_kernel(); */
5905 #endif
5906  /* spin_unlock_irqrestore(&bpvm_lock, flags); */
5907  unlock_bpctl();
5908  /* unlock_kernel(); */
5909  return ret;
5910 }
5911 
5912 struct file_operations Fops = {
5913  .owner = THIS_MODULE,
5914 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
5915  .ioctl = device_ioctl,
5916 #else
5917  .unlocked_ioctl = device_ioctl,
5918 #endif
5919 
5920  .open = device_open,
5921  .release = device_release, /* a.k.a. close */
5922 };
5923 
5924 #ifndef PCI_DEVICE
5925 #define PCI_DEVICE(vend,dev) \
5926  .vendor = (vend), .device = (dev), \
5927  .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
5928 #endif
5929 
5930 #define SILICOM_E1000BP_ETHERNET_DEVICE(device_id) {\
5931  PCI_DEVICE(SILICOM_VID, device_id)}
5932 
5933 typedef enum {
5934  PXG2BPFI,
5935  PXG2BPFIL,
5936  PXG2BPFILX,
5937  PXG2BPFILLX,
5938  PXGBPI,
5939  PXGBPIG,
5940  PXG2TBFI,
5941  PXG4BPI,
5942  PXG4BPFI,
5943  PEG4BPI,
5944  PEG2BPI,
5945  PEG4BPIN,
5946  PEG2BPFI,
5947  PEG2BPFILX,
5948  PMCXG2BPFI,
5949  PMCXG2BPFIN,
5950  PEG4BPII,
5951  PEG4BPFII,
5952  PXG4BPFILX,
5953  PMCXG2BPIN,
5954  PMCXG4BPIN,
5955  PXG2BISC1,
5956  PEG2TBFI,
5957  PXG2TBI,
5958  PXG4BPFID,
5959  PEG4BPFI,
5960  PEG4BPIPT,
5961  PXG6BPI,
5962  PEG4BPIL,
5963  PMCXG2BPIN2,
5964  PMCXG4BPIN2,
5965  PMCX2BPI,
5966  PEG2BPFID,
5967  PEG2BPFIDLX,
5968  PMCX4BPI,
5969  MEG2BPFILN,
5970  MEG2BPFINX,
5971  PEG4BPFILX,
5972  PE10G2BPISR,
5973  PE10G2BPILR,
5974  MHIO8AD,
5975  PE10G2BPICX4,
5976  PEG2BPI5,
5977  PEG6BPI,
5978  PEG4BPFI5,
5979  PEG4BPFI5LX,
5980  MEG2BPFILXLN,
5981  PEG2BPIX1,
5982  MEG2BPFILXNX,
5983  XE10G2BPIT,
5984  XE10G2BPICX4,
5985  XE10G2BPISR,
5986  XE10G2BPILR,
5987  PEG4BPIIO,
5988  XE10G2BPIXR,
5989  PE10GDBISR,
5990  PE10GDBILR,
5991  PEG2BISC6,
5992  PEG6BPIFC,
5993  PE10G2BPTCX4,
5994  PE10G2BPTSR,
5995  PE10G2BPTLR,
5996  PE10G2BPTT,
5997  PEG4BPI6,
5998  PEG4BPFI6,
5999  PEG4BPFI6LX,
6000  PEG4BPFI6ZX,
6001  PEG2BPI6,
6002  PEG2BPFI6,
6003  PEG2BPFI6LX,
6004  PEG2BPFI6ZX,
6005  PEG2BPFI6FLXM,
6006  PEG4BPI6FC,
6007  PEG4BPFI6FC,
6008  PEG4BPFI6FCLX,
6009  PEG4BPFI6FCZX,
6010  PEG6BPI6,
6011  PEG2BPI6SC6,
6012  MEG2BPI6,
6013  XEG2BPI6,
6014  MEG4BPI6,
6015  PEG2BPFI5,
6016  PEG2BPFI5LX,
6017  PXEG4BPFI,
6018  M1EG2BPI6,
6019  M1EG2BPFI6,
6020  M1EG2BPFI6LX,
6021  M1EG2BPFI6ZX,
6022  M1EG4BPI6,
6023  M1EG4BPFI6,
6024  M1EG4BPFI6LX,
6025  M1EG4BPFI6ZX,
6026  M1EG6BPI6,
6027  M1E2G4BPi80,
6028  M1E2G4BPFi80,
6029  M1E2G4BPFi80LX,
6030  M1E2G4BPFi80ZX,
6031  PE210G2SPI9,
6032  M1E10G2BPI9CX4,
6033  M1E10G2BPI9SR,
6034  M1E10G2BPI9LR,
6035  M1E10G2BPI9T,
6036  PE210G2BPI9CX4,
6037  PE210G2BPI9SR,
6038  PE210G2BPI9LR,
6039  PE210G2BPI9T,
6040  M2EG2BPFI6,
6041  M2EG2BPFI6LX,
6042  M2EG2BPFI6ZX,
6043  M2EG4BPI6,
6044  M2EG4BPFI6,
6045  M2EG4BPFI6LX,
6046  M2EG4BPFI6ZX,
6047  M2EG6BPI6,
6048  PEG2DBI6,
6049  PEG2DBFI6,
6050  PEG2DBFI6LX,
6051  PEG2DBFI6ZX,
6052  PE2G4BPi80,
6053  PE2G4BPFi80,
6054  PE2G4BPFi80LX,
6055  PE2G4BPFi80ZX,
6056  PE2G4BPi80L,
6057  M6E2G8BPi80A,
6058 
6059  PE2G2BPi35,
6060  PAC1200BPi35,
6061  PE2G2BPFi35,
6062  PE2G2BPFi35LX,
6063  PE2G2BPFi35ZX,
6064  PE2G4BPi35,
6065  PE2G4BPi35L,
6066  PE2G4BPFi35,
6067  PE2G4BPFi35LX,
6068  PE2G4BPFi35ZX,
6069 
6070  PE2G6BPi35,
6071  PE2G6BPi35CX,
6072 
6073  PE2G2BPi80,
6074  PE2G2BPFi80,
6075  PE2G2BPFi80LX,
6076  PE2G2BPFi80ZX,
6077  M2E10G2BPI9CX4,
6078  M2E10G2BPI9SR,
6079  M2E10G2BPI9LR,
6080  M2E10G2BPI9T,
6081  M6E2G8BPi80,
6082  PE210G2DBi9SR,
6083  PE210G2DBi9SRRB,
6084  PE210G2DBi9LR,
6085  PE210G2DBi9LRRB,
6086  PE310G4DBi940SR,
6087  PE310G4BPi9T,
6088  PE310G4BPi9SR,
6089  PE310G4BPi9LR,
6090  PE210G2BPi40,
6091 } board_t;
6092 
6093 typedef struct _bpmod_info_t {
6094  unsigned int vendor;
6095  unsigned int device;
6096  unsigned int subvendor;
6097  unsigned int subdevice;
6098  unsigned int index;
6099  char *bp_name;
6100 
6101 } bpmod_info_t;
6102 
6103 typedef struct _dev_desc {
6104  char *name;
6105 } dev_desc_t;
6106 
6107 dev_desc_t dev_desc[] = {
6108  {"Silicom Bypass PXG2BPFI-SD series adapter"},
6109  {"Silicom Bypass PXG2BPFIL-SD series adapter"},
6110  {"Silicom Bypass PXG2BPFILX-SD series adapter"},
6111  {"Silicom Bypass PXG2BPFILLX-SD series adapter"},
6112  {"Silicom Bypass PXG2BPI-SD series adapter"},
6113  {"Silicom Bypass PXG2BPIG-SD series adapter"},
6114  {"Silicom Bypass PXG2TBFI-SD series adapter"},
6115  {"Silicom Bypass PXG4BPI-SD series adapter"},
6116  {"Silicom Bypass PXG4BPFI-SD series adapter"},
6117  {"Silicom Bypass PEG4BPI-SD series adapter"},
6118  {"Silicom Bypass PEG2BPI-SD series adapter"},
6119  {"Silicom Bypass PEG4BPIN-SD series adapter"},
6120  {"Silicom Bypass PEG2BPFI-SD series adapter"},
6121  {"Silicom Bypass PEG2BPFI-LX-SD series adapter"},
6122  {"Silicom Bypass PMCX2BPFI-SD series adapter"},
6123  {"Silicom Bypass PMCX2BPFI-N series adapter"},
6124  {"Intel Bypass PEG2BPII series adapter"},
6125  {"Intel Bypass PEG2BPFII series adapter"},
6126  {"Silicom Bypass PXG4BPFILX-SD series adapter"},
6127  {"Silicom Bypass PMCX2BPI-N series adapter"},
6128  {"Silicom Bypass PMCX4BPI-N series adapter"},
6129  {"Silicom Bypass PXG2BISC1-SD series adapter"},
6130  {"Silicom Bypass PEG2TBFI-SD series adapter"},
6131  {"Silicom Bypass PXG2TBI-SD series adapter"},
6132  {"Silicom Bypass PXG4BPFID-SD series adapter"},
6133  {"Silicom Bypass PEG4BPFI-SD series adapter"},
6134  {"Silicom Bypass PEG4BPIPT-SD series adapter"},
6135  {"Silicom Bypass PXG6BPI-SD series adapter"},
6136  {"Silicom Bypass PEG4BPIL-SD series adapter"},
6137  {"Silicom Bypass PMCX2BPI-N2 series adapter"},
6138  {"Silicom Bypass PMCX4BPI-N2 series adapter"},
6139  {"Silicom Bypass PMCX2BPI-SD series adapter"},
6140  {"Silicom Bypass PEG2BPFID-SD series adapter"},
6141  {"Silicom Bypass PEG2BPFIDLX-SD series adapter"},
6142  {"Silicom Bypass PMCX4BPI-SD series adapter"},
6143  {"Silicom Bypass MEG2BPFILN-SD series adapter"},
6144  {"Silicom Bypass MEG2BPFINX-SD series adapter"},
6145  {"Silicom Bypass PEG4BPFILX-SD series adapter"},
6146  {"Silicom Bypass PE10G2BPISR-SD series adapter"},
6147  {"Silicom Bypass PE10G2BPILR-SD series adapter"},
6148  {"Silicom Bypass MHIO8AD-SD series adapter"},
6149  {"Silicom Bypass PE10G2BPICX4-SD series adapter"},
6150  {"Silicom Bypass PEG2BPI5-SD series adapter"},
6151  {"Silicom Bypass PEG6BPI5-SD series adapter"},
6152  {"Silicom Bypass PEG4BPFI5-SD series adapter"},
6153  {"Silicom Bypass PEG4BPFI5LX-SD series adapter"},
6154  {"Silicom Bypass MEG2BPFILXLN-SD series adapter"},
6155  {"Silicom Bypass PEG2BPIX1-SD series adapter"},
6156  {"Silicom Bypass MEG2BPFILXNX-SD series adapter"},
6157  {"Silicom Bypass XE10G2BPIT-SD series adapter"},
6158  {"Silicom Bypass XE10G2BPICX4-SD series adapter"},
6159  {"Silicom Bypass XE10G2BPISR-SD series adapter"},
6160  {"Silicom Bypass XE10G2BPILR-SD series adapter"},
6161  {"Intel Bypass PEG2BPFII0 series adapter"},
6162  {"Silicom Bypass XE10G2BPIXR series adapter"},
6163  {"Silicom Bypass PE10G2DBISR series adapter"},
6164  {"Silicom Bypass PEG2BI5SC6 series adapter"},
6165  {"Silicom Bypass PEG6BPI5FC series adapter"},
6166 
6167  {"Silicom Bypass PE10G2BPTCX4 series adapter"},
6168  {"Silicom Bypass PE10G2BPTSR series adapter"},
6169  {"Silicom Bypass PE10G2BPTLR series adapter"},
6170  {"Silicom Bypass PE10G2BPTT series adapter"},
6171  {"Silicom Bypass PEG4BPI6 series adapter"},
6172  {"Silicom Bypass PEG4BPFI6 series adapter"},
6173  {"Silicom Bypass PEG4BPFI6LX series adapter"},
6174  {"Silicom Bypass PEG4BPFI6ZX series adapter"},
6175  {"Silicom Bypass PEG2BPI6 series adapter"},
6176  {"Silicom Bypass PEG2BPFI6 series adapter"},
6177  {"Silicom Bypass PEG2BPFI6LX series adapter"},
6178  {"Silicom Bypass PEG2BPFI6ZX series adapter"},
6179  {"Silicom Bypass PEG2BPFI6FLXM series adapter"},
6180  {"Silicom Bypass PEG4BPI6FC series adapter"},
6181  {"Silicom Bypass PEG4BPFI6FC series adapter"},
6182  {"Silicom Bypass PEG4BPFI6FCLX series adapter"},
6183  {"Silicom Bypass PEG4BPFI6FCZX series adapter"},
6184  {"Silicom Bypass PEG6BPI6 series adapter"},
6185  {"Silicom Bypass PEG2BPI6SC6 series adapter"},
6186  {"Silicom Bypass MEG2BPI6 series adapter"},
6187  {"Silicom Bypass XEG2BPI6 series adapter"},
6188  {"Silicom Bypass MEG4BPI6 series adapter"},
6189  {"Silicom Bypass PEG2BPFI5-SD series adapter"},
6190  {"Silicom Bypass PEG2BPFI5LX-SD series adapter"},
6191  {"Silicom Bypass PXEG4BPFI-SD series adapter"},
6192  {"Silicom Bypass MxEG2BPI6 series adapter"},
6193  {"Silicom Bypass MxEG2BPFI6 series adapter"},
6194  {"Silicom Bypass MxEG2BPFI6LX series adapter"},
6195  {"Silicom Bypass MxEG2BPFI6ZX series adapter"},
6196  {"Silicom Bypass MxEG4BPI6 series adapter"},
6197  {"Silicom Bypass MxEG4BPFI6 series adapter"},
6198  {"Silicom Bypass MxEG4BPFI6LX series adapter"},
6199  {"Silicom Bypass MxEG4BPFI6ZX series adapter"},
6200  {"Silicom Bypass MxEG6BPI6 series adapter"},
6201  {"Silicom Bypass MxE2G4BPi80 series adapter"},
6202  {"Silicom Bypass MxE2G4BPFi80 series adapter"},
6203  {"Silicom Bypass MxE2G4BPFi80LX series adapter"},
6204  {"Silicom Bypass MxE2G4BPFi80ZX series adapter"},
6205 
6206  {"Silicom Bypass PE210G2SPI9 series adapter"},
6207 
6208  {"Silicom Bypass MxE210G2BPI9CX4 series adapter"},
6209  {"Silicom Bypass MxE210G2BPI9SR series adapter"},
6210  {"Silicom Bypass MxE210G2BPI9LR series adapter"},
6211  {"Silicom Bypass MxE210G2BPI9T series adapter"},
6212 
6213  {"Silicom Bypass PE210G2BPI9CX4 series adapter"},
6214  {"Silicom Bypass PE210G2BPI9SR series adapter"},
6215  {"Silicom Bypass PE210G2BPI9LR series adapter"},
6216  {"Silicom Bypass PE210G2BPI9T series adapter"},
6217 
6218  {"Silicom Bypass M2EG2BPFI6 series adapter"},
6219  {"Silicom Bypass M2EG2BPFI6LX series adapter"},
6220  {"Silicom Bypass M2EG2BPFI6ZX series adapter"},
6221  {"Silicom Bypass M2EG4BPI6 series adapter"},
6222  {"Silicom Bypass M2EG4BPFI6 series adapter"},
6223  {"Silicom Bypass M2EG4BPFI6LX series adapter"},
6224  {"Silicom Bypass M2EG4BPFI6ZX series adapter"},
6225  {"Silicom Bypass M2EG6BPI6 series adapter"},
6226 
6227  {"Silicom Bypass PEG2DBI6 series adapter"},
6228  {"Silicom Bypass PEG2DBFI6 series adapter"},
6229  {"Silicom Bypass PEG2DBFI6LX series adapter"},
6230  {"Silicom Bypass PEG2DBFI6ZX series adapter"},
6231 
6232  {"Silicom Bypass PE2G4BPi80 series adapter"},
6233  {"Silicom Bypass PE2G4BPFi80 series adapter"},
6234  {"Silicom Bypass PE2G4BPFi80LX series adapter"},
6235  {"Silicom Bypass PE2G4BPFi80ZX series adapter"},
6236 
6237  {"Silicom Bypass PE2G4BPi80L series adapter"},
6238  {"Silicom Bypass MxE2G8BPi80A series adapter"},
6239 
6240  {"Silicom Bypass PE2G2BPi35 series adapter"},
6241  {"Silicom Bypass PAC1200BPi35 series adapter"},
6242  {"Silicom Bypass PE2G2BPFi35 series adapter"},
6243  {"Silicom Bypass PE2G2BPFi35LX series adapter"},
6244  {"Silicom Bypass PE2G2BPFi35ZX series adapter"},
6245 
6246  {"Silicom Bypass PE2G4BPi35 series adapter"},
6247  {"Silicom Bypass PE2G4BPi35L series adapter"},
6248  {"Silicom Bypass PE2G4BPFi35 series adapter"},
6249  {"Silicom Bypass PE2G4BPFi35LX series adapter"},
6250  {"Silicom Bypass PE2G4BPFi35ZX series adapter"},
6251 
6252  {"Silicom Bypass PE2G6BPi35 series adapter"},
6253  {"Silicom Bypass PE2G6BPi35CX series adapter"},
6254 
6255  {"Silicom Bypass PE2G2BPi80 series adapter"},
6256  {"Silicom Bypass PE2G2BPFi80 series adapter"},
6257  {"Silicom Bypass PE2G2BPFi80LX series adapter"},
6258  {"Silicom Bypass PE2G2BPFi80ZX series adapter"},
6259 
6260  {"Silicom Bypass M2E10G2BPI9CX4 series adapter"},
6261  {"Silicom Bypass M2E10G2BPI9SR series adapter"},
6262  {"Silicom Bypass M2E10G2BPI9LR series adapter"},
6263  {"Silicom Bypass M2E10G2BPI9T series adapter"},
6264  {"Silicom Bypass MxE2G8BPi80 series adapter"},
6265  {"Silicom Bypass PE210G2DBi9SR series adapter"},
6266  {"Silicom Bypass PE210G2DBi9SRRB series adapter"},
6267  {"Silicom Bypass PE210G2DBi9LR series adapter"},
6268  {"Silicom Bypass PE210G2DBi9LRRB series adapter"},
6269  {"Silicom Bypass PE310G4DBi9-SR series adapter"},
6270  {"Silicom Bypass PE310G4BPi9T series adapter"},
6271  {"Silicom Bypass PE310G4BPi9SR series adapter"},
6272  {"Silicom Bypass PE310G4BPi9LR series adapter"},
6273  {"Silicom Bypass PE210G2BPi40T series adapter"},
6274  {0},
6275 };
6276 
6277 static bpmod_info_t tx_ctl_pci_tbl[] = {
6278  {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFI_SSID, PXG2BPFI,
6279  "PXG2BPFI-SD"},
6280  {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFIL_SSID, PXG2BPFIL,
6281  "PXG2BPFIL-SD"},
6282  {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILX_SSID, PXG2BPFILX,
6283  "PXG2BPFILX-SD"},
6284  {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILLX_SSID, PXG2BPFILLX,
6285  "PXG2BPFILLXSD"},
6286  {0x8086, 0x1010, SILICOM_SVID, SILICOM_PXGBPI_SSID, PXGBPI,
6287  "PXG2BPI-SD"},
6288  {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXGBPIG_SSID, PXGBPIG,
6289  "PXG2BPIG-SD"},
6290  {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2TBFI_SSID, PXG2TBFI,
6291  "PXG2TBFI-SD"},
6292  {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
6293  "PXG4BPI-SD"},
6294  {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
6295  "PXG4BPFI-SD"},
6296  {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFILX_SSID, PXG4BPFILX,
6297  "PXG4BPFILX-SD"},
6298  {0x8086, 0x1079, SILICOM_SVID, SILICOM_PEG4BPI_SSID, PEG4BPI,
6299  "PEXG4BPI-SD"},
6300  {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPI_SSID, PEG2BPI,
6301  "PEG2BPI-SD"},
6302  {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIN_SSID, PEG4BPIN,
6303  "PEG4BPI-SD"},
6304  {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFI_SSID, PEG2BPFI,
6305  "PEG2BPFI-SD"},
6306  {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFILX_SSID, PEG2BPFILX,
6307  "PEG2BPFILX-SD"},
6308  {0x8086, 0x107a, SILICOM_SVID, SILICOM_PMCXG2BPFI_SSID, PMCXG2BPFI,
6309  "PMCX2BPFI-SD"},
6310  {0x8086, 0x107a, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPFIN_SSID,
6311  PMCXG2BPFIN, "PMCX2BPFI-N"},
6312  {0x8086, INTEL_PEG4BPII_PID, 0x8086, INTEL_PEG4BPII_SSID, PEG4BPII,
6313  "PEG4BPII"},
6314  {0x8086, INTEL_PEG4BPIIO_PID, 0x8086, INTEL_PEG4BPIIO_SSID, PEG4BPIIO,
6315  "PEG4BPII0"},
6316  {0x8086, INTEL_PEG4BPFII_PID, 0x8086, INTEL_PEG4BPFII_SSID, PEG4BPFII,
6317  "PEG4BPFII"},
6318  {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN_SSID,
6319  PMCXG2BPIN, "PMCX2BPI-N"},
6320  {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN_SSID,
6321  PMCXG4BPIN, "PMCX4BPI-N"},
6322  {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
6323  "PXG2BISC1-SD"},
6324  {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2TBFI_SSID, PEG2TBFI,
6325  "PEG2TBFI-SD"},
6326  {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
6327  "PXG2TBI-SD"},
6328  {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFID_SSID, PXG4BPFID,
6329  "PXG4BPFID-SD"},
6330  {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
6331  "PEG4BPFI-SD"},
6332  {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIPT_SSID, PEG4BPIPT,
6333  "PEG4BPIPT-SD"},
6334  {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG6BPI_SSID, PXG6BPI,
6335  "PXG6BPI-SD"},
6336  {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6337  SILICOM_PEG4BPIL_SSID /*PCI_ANY_ID */ , PEG4BPIL, "PEG4BPIL-SD"},
6338  {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN2_SSID,
6339  PMCXG2BPIN2, "PMCX2BPI-N2"},
6340  {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN2_SSID,
6341  PMCXG4BPIN2, "PMCX4BPI-N2"},
6342  {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX2BPI_SSID, PMCX2BPI,
6343  "PMCX2BPI-SD"},
6344  {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX4BPI_SSID, PMCX4BPI,
6345  "PMCX4BPI-SD"},
6346  {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFID_SSID, PEG2BPFID,
6347  "PEG2BPFID-SD"},
6348  {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFIDLX_SSID, PEG2BPFIDLX,
6349  "PEG2BPFIDLXSD"},
6350  {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILN_SSID, MEG2BPFILN,
6351  "MEG2BPFILN-SD"},
6352  {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFINX_SSID, MEG2BPFINX,
6353  "MEG2BPFINX-SD"},
6354  {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFILX_SSID, PEG4BPFILX,
6355  "PEG4BPFILX-SD"},
6356  {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPISR_SSID,
6357  PE10G2BPISR, "PE10G2BPISR"},
6358  {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPILR_SSID,
6359  PE10G2BPILR, "PE10G2BPILR"},
6360  {0x8086, 0x10a9, SILICOM_SVID, SILICOM_MHIO8AD_SSID, MHIO8AD,
6361  "MHIO8AD-SD"},
6362  {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPICX4_SSID,
6363  PE10G2BPISR, "PE10G2BPICX4"},
6364  {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6365  SILICOM_PEG2BPI5_SSID /*PCI_ANY_ID */ , PEG2BPI5, "PEG2BPI5-SD"},
6366  {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6367  SILICOM_PEG6BPI_SSID /*PCI_ANY_ID */ , PEG6BPI, "PEG6BPI5"},
6368  {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG4BPFI5_SSID,
6369  PEG4BPFI5, "PEG4BPFI5"},
6370  {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
6371  SILICOM_PEG4BPFI5LX_SSID, PEG4BPFI5LX, "PEG4BPFI5LX"},
6372  {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXLN_SSID, MEG2BPFILXLN,
6373  "MEG2BPFILXLN"},
6374  {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPIX1_SSID, PEG2BPIX1,
6375  "PEG2BPIX1-SD"},
6376  {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXNX_SSID, MEG2BPFILXNX,
6377  "MEG2BPFILXNX"},
6378  {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPIT_SSID, XE10G2BPIT,
6379  "XE10G2BPIT"},
6380  {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPICX4_SSID,
6381  XE10G2BPICX4, "XE10G2BPICX4"},
6382  {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPISR_SSID, XE10G2BPISR,
6383  "XE10G2BPISR"},
6384  {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPILR_SSID, XE10G2BPILR,
6385  "XE10G2BPILR"},
6386  {0x8086, 0x10C6, NOKIA_XE10G2BPIXR_SVID, NOKIA_XE10G2BPIXR_SSID,
6387  XE10G2BPIXR, "XE10G2BPIXR"},
6388  {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBISR_SSID, PE10GDBISR,
6389  "PE10G2DBISR"},
6390  {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBILR_SSID, PE10GDBILR,
6391  "PE10G2DBILR"},
6392  {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6393  SILICOM_PEG2BISC6_SSID /*PCI_ANY_ID */ , PEG2BISC6, "PEG2BI5SC6"},
6394  {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6395  SILICOM_PEG6BPIFC_SSID /*PCI_ANY_ID */ , PEG6BPIFC, "PEG6BPI5FC"},
6396 
6397  {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6398  SILICOM_PE10G2BPTCX4_SSID, PE10G2BPTCX4, "PE10G2BPTCX4"},
6399  {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6400  SILICOM_PE10G2BPTSR_SSID, PE10G2BPTSR, "PE10G2BPTSR"},
6401  {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6402  SILICOM_PE10G2BPTLR_SSID, PE10G2BPTLR, "PE10G2BPTLR"},
6403  {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6404  SILICOM_PE10G2BPTT_SSID, PE10G2BPTT, "PE10G2BPTT"},
6405 
6406  /* {BROADCOM_VID, BROADCOM_PE10G2_PID, PCI_ANY_ID, PCI_ANY_ID, PE10G2BPTCX4, "PE10G2BPTCX4"}, */
6407 
6408  {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6409  SILICOM_PEG4BPI6_SSID /*PCI_ANY_ID */ , PEG4BPI6, "PEG4BPI6"},
6410  {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6411  SILICOM_PEG4BPFI6_SSID /*PCI_ANY_ID */ , PEG4BPFI6, "PEG4BPFI6"},
6412  {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6413  SILICOM_PEG4BPFI6LX_SSID /*PCI_ANY_ID */ , PEG4BPFI6LX, "PEG4BPFI6LX"},
6414  {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6415  SILICOM_PEG4BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6ZX, "PEG4BPFI6ZX"},
6416  {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6417  SILICOM_PEG2BPI6_SSID /*PCI_ANY_ID */ , PEG2BPI6, "PEG2BPI6"},
6418  {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6419  SILICOM_PEG2BPFI6_SSID /*PCI_ANY_ID */ , PEG2BPFI6, "PEG2BPFI6"},
6420  {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6421  SILICOM_PEG2BPFI6LX_SSID /*PCI_ANY_ID */ , PEG2BPFI6LX, "PEG2BPFI6LX"},
6422  {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6423  SILICOM_PEG2BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG2BPFI6ZX, "PEG2BPFI6ZX"},
6424  {0x8086, 0x10e7, SILICOM_SVID /*PCI_ANY_ID */ ,
6425  SILICOM_PEG2BPFI6FLXM_SSID /*PCI_ANY_ID */ , PEG2BPFI6FLXM,
6426  "PEG2BPFI6FLXM"},
6427  {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6428  SILICOM_PEG4BPI6FC_SSID /*PCI_ANY_ID */ , PEG4BPI6FC, "PEG4BPI6FC"},
6429  {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6430  SILICOM_PEG4BPFI6FC_SSID /*PCI_ANY_ID */ , PEG4BPFI6FC, "PEG4BPFI6FC"},
6431  {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6432  SILICOM_PEG4BPFI6FCLX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCLX,
6433  "PEG4BPFI6FCLX"},
6434  {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6435  SILICOM_PEG4BPFI6FCZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCZX,
6436  "PEG4BPFI6FCZX"},
6437  {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6438  SILICOM_PEG6BPI6_SSID /*PCI_ANY_ID */ , PEG6BPI6, "PEG6BPI6"},
6439  {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6440  SILICOM_PEG2BPI6SC6_SSID /*PCI_ANY_ID */ , PEG2BPI6SC6,
6441  "PEG6BPI62SC6"},
6442  {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6443  SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
6444  {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6445  SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
6446  {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6447  SILICOM_MEG4BPI6_SSID /*PCI_ANY_ID */ , MEG4BPI6, "MEG4BPI6"},
6448 
6449  {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG2BPFI5_SSID,
6450  PEG2BPFI5, "PEG2BPFI5"},
6451  {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
6452  SILICOM_PEG2BPFI5LX_SSID, PEG2BPFI5LX, "PEG2BPFI5LX"},
6453 
6454  {0x8086, 0x105f, SILICOM_SVID, SILICOM_PXEG4BPFI_SSID, PXEG4BPFI,
6455  "PXEG4BPFI-SD"},
6456 
6457  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6458  SILICOM_M1EG2BPI6_SSID /*PCI_ANY_ID */ , M1EG2BPI6, "MxEG2BPI6"},
6459 
6460  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6461  SILICOM_M1EG2BPFI6_SSID /*PCI_ANY_ID */ , M1EG2BPFI6, "MxEG2BPFI6"},
6462  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6463  SILICOM_M1EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6LX,
6464  "MxEG2BPFI6LX"},
6465  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6466  SILICOM_M1EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6ZX,
6467  "MxEG2BPFI6ZX"},
6468 
6469  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6470  SILICOM_M1EG4BPI6_SSID /*PCI_ANY_ID */ , M1EG4BPI6, "MxEG4BPI6"},
6471 
6472  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6473  SILICOM_M1EG4BPFI6_SSID /*PCI_ANY_ID */ , M1EG4BPFI6, "MxEG4BPFI6"},
6474  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6475  SILICOM_M1EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6LX,
6476  "MxEG4BPFI6LX"},
6477  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6478  SILICOM_M1EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6ZX,
6479  "MxEG4BPFI6ZX"},
6480 
6481  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6482  SILICOM_M1EG6BPI6_SSID /*PCI_ANY_ID */ , M1EG6BPI6, "MxEG6BPI6"},
6483 
6484  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6485  SILICOM_M1E2G4BPi80_SSID /*PCI_ANY_ID */ , M1E2G4BPi80, "MxE2G4BPi80"},
6486  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6487  SILICOM_M1E2G4BPFi80_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80,
6488  "MxE2G4BPFi80"},
6489  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6490  SILICOM_M1E2G4BPFi80LX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80LX,
6491  "MxE2G4BPFi80LX"},
6492  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6493  SILICOM_M1E2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80ZX,
6494  "MxE2G4BPFi80ZX"},
6495 
6496  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6497  SILICOM_M2EG2BPFI6_SSID /*PCI_ANY_ID */ , M2EG2BPFI6, "M2EG2BPFI6"},
6498  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6499  SILICOM_M2EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6LX,
6500  "M2EG2BPFI6LX"},
6501  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6502  SILICOM_M2EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6ZX,
6503  "M2EG2BPFI6ZX"},
6504 
6505  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6506  SILICOM_M2EG4BPI6_SSID /*PCI_ANY_ID */ , M2EG4BPI6, "M2EG4BPI6"},
6507 
6508  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6509  SILICOM_M2EG4BPFI6_SSID /*PCI_ANY_ID */ , M2EG4BPFI6, "M2EG4BPFI6"},
6510  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6511  SILICOM_M2EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6LX,
6512  "M2EG4BPFI6LX"},
6513  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6514  SILICOM_M2EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6ZX,
6515  "M2EG4BPFI6ZX"},
6516 
6517  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6518  SILICOM_M2EG6BPI6_SSID /*PCI_ANY_ID */ , M2EG6BPI6, "M2EG6BPI6"},
6519 
6520  {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6521  SILICOM_PEG2DBI6_SSID /*PCI_ANY_ID */ , PEG2DBI6, "PEG2DBI6"},
6522  {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6523  SILICOM_PEG2DBFI6_SSID /*PCI_ANY_ID */ , PEG2DBFI6, "PEG2DBFI6"},
6524  {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6525  SILICOM_PEG2DBFI6LX_SSID /*PCI_ANY_ID */ , PEG2DBFI6LX, "PEG2DBFI6LX"},
6526  {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6527  SILICOM_PEG2DBFI6ZX_SSID /*PCI_ANY_ID */ , PEG2DBFI6ZX, "PEG2DBFI6ZX"},
6528 
6529  {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6530  SILICOM_PE210G2DBi9SR_SSID, PE210G2DBi9SR, "PE210G2DBi9SR"},
6531  {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6532  SILICOM_PE210G2DBi9LR_SSID, PE210G2DBi9LR, "PE210G2DBi9LR"},
6533  {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6534  SILICOM_PE310G4DBi940SR_SSID, PE310G4DBi940SR, "PE310G4DBi9SR"},
6535 
6536  {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6537  SILICOM_PE310G4BPi9T_SSID, PE310G4BPi9T, "PE310G4BPi9T"},
6538  {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6539  SILICOM_PE310G4BPi9SR_SSID, PE310G4BPi9SR, "PE310G4BPi9SR"},
6540  {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6541  SILICOM_PE310G4BPi9LR_SSID, PE310G4BPi9LR, "PE310G4BPi9LR"},
6542 
6543  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6544  SILICOM_PE2G4BPi80_SSID /*PCI_ANY_ID */ , PE2G4BPi80, "PE2G4BPi80"},
6545  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6546  SILICOM_PE2G4BPFi80_SSID /*PCI_ANY_ID */ , PE2G4BPFi80, "PE2G4BPFi80"},
6547  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6548  SILICOM_PE2G4BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80LX,
6549  "PE2G4BPFi80LX"},
6550  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6551  SILICOM_PE2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80ZX,
6552  "PE2G4BPFi80ZX"},
6553 
6554  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6555  SILICOM_PE2G4BPi80L_SSID /*PCI_ANY_ID */ , PE2G4BPi80L, "PE2G4BPi80L"},
6556 
6557  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6558  SILICOM_M6E2G8BPi80A_SSID /*PCI_ANY_ID */ , M6E2G8BPi80A,
6559  "MxE2G8BPi80A"},
6560 
6561  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6562  SILICOM_PE2G2BPi35_SSID /*PCI_ANY_ID */ , PE2G2BPi35, "PE2G2BPi35"},
6563  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6564  SILICOM_PAC1200BPi35_SSID /*PCI_ANY_ID */ , PAC1200BPi35,
6565  "PAC1200BPi35"},
6566 
6567  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6568  SILICOM_PE2G2BPFi35_SSID /*PCI_ANY_ID */ , PE2G2BPFi35, "PE2G2BPFi35"},
6569  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6570  SILICOM_PE2G2BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35LX,
6571  "PE2G2BPFi35LX"},
6572  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6573  SILICOM_PE2G2BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35ZX,
6574  "PE2G2BPFi35ZX"},
6575 
6576  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6577  SILICOM_PE2G4BPi35_SSID /*PCI_ANY_ID */ , PE2G4BPi35, "PE2G4BPi35"},
6578 
6579  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6580  SILICOM_PE2G4BPi35L_SSID /*PCI_ANY_ID */ , PE2G4BPi35L, "PE2G4BPi35L"},
6581 
6582  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6583  SILICOM_PE2G4BPFi35_SSID /*PCI_ANY_ID */ , PE2G4BPFi35, "PE2G4BPFi35"},
6584  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6585  SILICOM_PE2G4BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35LX,
6586  "PE2G4BPFi35LX"},
6587  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6588  SILICOM_PE2G4BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35ZX,
6589  "PE2G4BPFi35ZX"},
6590 
6591  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6592  SILICOM_PE2G6BPi35_SSID /*PCI_ANY_ID */ , PE2G6BPi35, "PE2G6BPi35"},
6593 
6594 
6595  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa0, PE2G6BPi35CX,
6596  "PE2G6BPi35CX"},
6597  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa1, PE2G6BPi35CX,
6598  "PE2G6BPi35CX"},
6599  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa2, PE2G6BPi35CX,
6600  "PE2G6BPi35CX"},
6601  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa3, PE2G6BPi35CX,
6602  "PE2G6BPi35CX"},
6603  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa4, PE2G6BPi35CX,
6604  "PE2G6BPi35CX"},
6605  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa5, PE2G6BPi35CX,
6606  "PE2G6BPi35CX"},
6607  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa6, PE2G6BPi35CX,
6608  "PE2G6BPi35CX"},
6609  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa7, PE2G6BPi35CX,
6610  "PE2G6BPi35CX"},
6611  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa8, PE2G6BPi35CX,
6612  "PE2G6BPi35CX"},
6613  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa9, PE2G6BPi35CX,
6614  "PE2G6BPi35CX"},
6615  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaa, PE2G6BPi35CX,
6616  "PE2G6BPi35CX"},
6617  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaab, PE2G6BPi35CX,
6618  "PE2G6BPi35CX"},
6619  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaac, PE2G6BPi35CX,
6620  "PE2G6BPi35CX"},
6621  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaad, PE2G6BPi35CX,
6622  "PE2G6BPi35CX"},
6623  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaae, PE2G6BPi35CX,
6624  "PE2G6BPi35CX"},
6625  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaf, PE2G6BPi35CX,
6626  "PE2G6BPi35CX"},
6627  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab0, PE2G6BPi35CX,
6628  "PE2G6BPi35CX"},
6629  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab1, PE2G6BPi35CX,
6630  "PE2G6BPi35CX"},
6631  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab2, PE2G6BPi35CX,
6632  "PE2G6BPi35CX"},
6633  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab3, PE2G6BPi35CX,
6634  "PE2G6BPi35CX"},
6635  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab4, PE2G6BPi35CX,
6636  "PE2G6BPi35CX"},
6637  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab5, PE2G6BPi35CX,
6638  "PE2G6BPi35CX"},
6639  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab6, PE2G6BPi35CX,
6640  "PE2G6BPi35CX"},
6641  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab7, PE2G6BPi35CX,
6642  "PE2G6BPi35CX"},
6643  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab8, PE2G6BPi35CX,
6644  "PE2G6BPi35CX"},
6645  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab9, PE2G6BPi35CX,
6646  "PE2G6BPi35CX"},
6647  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaba, PE2G6BPi35CX,
6648  "PE2G6BPi35CX"},
6649  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabb, PE2G6BPi35CX,
6650  "PE2G6BPi35CX"},
6651  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabc, PE2G6BPi35CX,
6652  "PE2G6BPi35CX"},
6653  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabd, PE2G6BPi35CX,
6654  "PE2G6BPi35CX"},
6655  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabe, PE2G6BPi35CX,
6656  "PE2G6BPi35CX"},
6657  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabf, PE2G6BPi35CX,
6658  "PE2G6BPi35CX"},
6659 
6660  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6661  SILICOM_PE2G2BPi80_SSID /*PCI_ANY_ID */ , PE2G2BPi80, "PE2G2BPi80"},
6662  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6663  SILICOM_PE2G2BPFi80_SSID /*PCI_ANY_ID */ , PE2G2BPFi80, "PE2G2BPFi80"},
6664  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6665  SILICOM_PE2G2BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80LX,
6666  "PE2G2BPFi80LX"},
6667  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6668  SILICOM_PE2G2BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80ZX,
6669  "PE2G2BPFi80ZX"},
6670 
6671  {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6672  SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
6673  {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6674  SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
6675 
6676 #if 0
6677  {0x8086, 0x10fb, 0x8086, INTEL_PE210G2SPI9_SSID, PE210G2SPI9,
6678  "PE210G2SPI9"},
6679 #endif
6680  {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6681  SILICOM_M1E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M1E10G2BPI9CX4,
6682  "MxE210G2BPI9CX4"},
6683  {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6684  SILICOM_M1E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9SR,
6685  "MxE210G2BPI9SR"},
6686  {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6687  SILICOM_M1E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9LR,
6688  "MxE210G2BPI9LR"},
6689  {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6690  SILICOM_M1E10G2BPI9T_SSID /*PCI_ANY_ID */ , M1E10G2BPI9T,
6691  "MxE210G2BPI9T"},
6692 
6693  {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6694  SILICOM_M2E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M2E10G2BPI9CX4,
6695  "M2E10G2BPI9CX4"},
6696  {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6697  SILICOM_M2E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9SR,
6698  "M2E10G2BPI9SR"},
6699  {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6700  SILICOM_M2E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9LR,
6701  "M2E10G2BPI9LR"},
6702  {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6703  SILICOM_M2E10G2BPI9T_SSID /*PCI_ANY_ID */ , M2E10G2BPI9T,
6704  "M2E10G2BPI9T"},
6705 
6706  {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9CX4_SSID,
6707  PE210G2BPI9CX4, "PE210G2BPI9CX4"},
6708  {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9SR_SSID,
6709  PE210G2BPI9SR, "PE210G2BPI9SR"},
6710  {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9LR_SSID,
6711  PE210G2BPI9LR, "PE210G2BPI9LR"},
6712  {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9T_SSID, PE210G2BPI9T,
6713  "PE210G2BPI9T"},
6714 
6715 #if 0
6716  {0x1374, 0x2c, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
6717  "PXG4BPI-SD"},
6718 
6719  {0x1374, 0x2d, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
6720  "PXG4BPFI-SD"},
6721 
6722  {0x1374, 0x3f, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
6723  "PXG2TBI-SD"},
6724 
6725  {0x1374, 0x3d, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
6726  "PXG2BISC1-SD"},
6727 
6728  {0x1374, 0x40, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
6729  "PEG4BPFI-SD"},
6730 
6731 #ifdef BP_SELF_TEST
6732  {0x1374, 0x28, SILICOM_SVID, 0x28, PXGBPI, "PXG2BPI-SD"},
6733 #endif
6734 #endif
6735  {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6736  SILICOM_M6E2G8BPi80_SSID /*PCI_ANY_ID */ , M6E2G8BPi80, "MxE2G8BPi80"},
6737  {0x8086, 0x1528, SILICOM_SVID /*PCI_ANY_ID */ ,
6738  SILICOM_PE210G2BPi40_SSID /*PCI_ANY_ID */ , PE210G2BPi40,
6739  "PE210G2BPi40T"},
6740 
6741  /* required last entry */
6742  {0,}
6743 };
6744 
6745 /*
6746 * Initialize the module - Register the character device
6747 */
6748 
6749 static int __init bypass_init_module(void)
6750 {
6751  int ret_val, idx, idx_dev = 0;
6752  struct pci_dev *pdev1 = NULL;
6753  unsigned long mmio_start, mmio_len;
6754 
6755  printk(BP_MOD_DESCR " v" BP_MOD_VER "\n");
6756  ret_val = register_chrdev(major_num, DEVICE_NAME, &Fops);
6757  if (ret_val < 0) {
6758  printk("%s failed with %d\n", DEVICE_NAME, ret_val);
6759  return ret_val;
6760  }
6761  major_num = ret_val; /* dynamic */
6762  for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6763  while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6764  tx_ctl_pci_tbl[idx].device,
6765  tx_ctl_pci_tbl[idx].subvendor,
6766  tx_ctl_pci_tbl[idx].subdevice,
6767  pdev1))) {
6768 
6769  device_num++;
6770  }
6771  }
6772  if (!device_num) {
6773  printk("No such device\n");
6774  unregister_chrdev(major_num, DEVICE_NAME);
6775  return -1;
6776  }
6777 
6778  bpctl_dev_arr = kmalloc((device_num) * sizeof(bpctl_dev_t), GFP_KERNEL);
6779 
6780  if (!bpctl_dev_arr) {
6781  printk("Allocation error\n");
6782  unregister_chrdev(major_num, DEVICE_NAME);
6783  return -1;
6784  }
6785  memset(bpctl_dev_arr, 0, ((device_num) * sizeof(bpctl_dev_t)));
6786 
6787  pdev1 = NULL;
6788  for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6789  while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6790  tx_ctl_pci_tbl[idx].device,
6791  tx_ctl_pci_tbl[idx].subvendor,
6792  tx_ctl_pci_tbl[idx].subdevice,
6793  pdev1))) {
6794  bpctl_dev_arr[idx_dev].pdev = pdev1;
6795 
6796  mmio_start = pci_resource_start(pdev1, 0);
6797  mmio_len = pci_resource_len(pdev1, 0);
6798 
6799  bpctl_dev_arr[idx_dev].desc =
6800  dev_desc[tx_ctl_pci_tbl[idx].index].name;
6801  bpctl_dev_arr[idx_dev].name =
6802  tx_ctl_pci_tbl[idx].bp_name;
6803  bpctl_dev_arr[idx_dev].device =
6804  tx_ctl_pci_tbl[idx].device;
6805  bpctl_dev_arr[idx_dev].vendor =
6806  tx_ctl_pci_tbl[idx].vendor;
6807  bpctl_dev_arr[idx_dev].subdevice =
6808  tx_ctl_pci_tbl[idx].subdevice;
6809  bpctl_dev_arr[idx_dev].subvendor =
6810  tx_ctl_pci_tbl[idx].subvendor;
6811  /* bpctl_dev_arr[idx_dev].pdev=pdev1; */
6812  bpctl_dev_arr[idx_dev].func = PCI_FUNC(pdev1->devfn);
6813  bpctl_dev_arr[idx_dev].slot = PCI_SLOT(pdev1->devfn);
6814  bpctl_dev_arr[idx_dev].bus = pdev1->bus->number;
6815  bpctl_dev_arr[idx_dev].mem_map =
6816  (unsigned long)ioremap(mmio_start, mmio_len);
6817 #ifdef BP_SYNC_FLAG
6818  spin_lock_init(&bpctl_dev_arr[idx_dev].bypass_wr_lock);
6819 #endif
6820  if (BP10G9_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6821  bpctl_dev_arr[idx_dev].bp_10g9 = 1;
6822  if (BP10G_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6823  bpctl_dev_arr[idx_dev].bp_10g = 1;
6824  if (PEG540_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice)) {
6825 
6826  bpctl_dev_arr[idx_dev].bp_540 = 1;
6827  }
6828  if (PEGF5_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6829  bpctl_dev_arr[idx_dev].bp_fiber5 = 1;
6830  if (PEG80_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6831  bpctl_dev_arr[idx_dev].bp_i80 = 1;
6832  if (PEGF80_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6833  bpctl_dev_arr[idx_dev].bp_i80 = 1;
6834  if ((bpctl_dev_arr[idx_dev].subdevice & 0xa00) == 0xa00)
6835  bpctl_dev_arr[idx_dev].bp_i80 = 1;
6836  if (BP10GB_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice)) {
6837  if (bpctl_dev_arr[idx_dev].ifindex == 0) {
6838  unregister_chrdev(major_num,
6839  DEVICE_NAME);
6840  printk
6841  ("Please load network driver for %s adapter!\n",
6842  bpctl_dev_arr[idx_dev].name);
6843  return -1;
6844  }
6845 
6846  if (bpctl_dev_arr[idx_dev].ndev) {
6847  if (!
6848  (bpctl_dev_arr[idx_dev].ndev->
6849  flags & IFF_UP)) {
6850  if (!
6851  (bpctl_dev_arr[idx_dev].
6852  ndev->flags & IFF_UP)) {
6853  unregister_chrdev
6854  (major_num,
6855  DEVICE_NAME);
6856  printk
6857  ("Please bring up network interfaces for %s adapter!\n",
6858  bpctl_dev_arr
6859  [idx_dev].name);
6860  return -1;
6861  }
6862 
6863  }
6864  }
6865  bpctl_dev_arr[idx_dev].bp_10gb = 1;
6866  }
6867 
6868  if (!bpctl_dev_arr[idx_dev].bp_10g9) {
6869 
6870  if (is_bypass_fn(&bpctl_dev_arr[idx_dev])) {
6871  printk(KERN_INFO "%s found, ",
6872  bpctl_dev_arr[idx_dev].name);
6873  if ((OLD_IF_SERIES
6874  (bpctl_dev_arr[idx_dev].subdevice))
6875  ||
6876  (INTEL_IF_SERIES
6877  (bpctl_dev_arr[idx_dev].
6878  subdevice)))
6879  bpctl_dev_arr[idx_dev].
6880  bp_fw_ver = 0xff;
6881  else
6882  bpctl_dev_arr[idx_dev].
6883  bp_fw_ver =
6884  bypass_fw_ver(&bpctl_dev_arr
6885  [idx_dev]);
6886  if ((bpctl_dev_arr[idx_dev].bp_10gb ==
6887  1)
6888  && (bpctl_dev_arr[idx_dev].
6889  bp_fw_ver == 0xff)) {
6890  int cnt = 100;
6891  while (cnt--) {
6892  iounmap((void
6893  *)
6894  (bpctl_dev_arr
6895  [idx_dev].
6896  mem_map));
6897  mmio_start =
6898  pci_resource_start
6899  (pdev1, 0);
6900  mmio_len =
6901  pci_resource_len
6902  (pdev1, 0);
6903 
6904  bpctl_dev_arr[idx_dev].
6905  mem_map =
6906  (unsigned long)
6907  ioremap(mmio_start,
6908  mmio_len);
6909 
6910  bpctl_dev_arr[idx_dev].
6911  bp_fw_ver =
6912  bypass_fw_ver
6913  (&bpctl_dev_arr
6914  [idx_dev]);
6915  if (bpctl_dev_arr
6916  [idx_dev].
6917  bp_fw_ver == 0xa8)
6918  break;
6919 
6920  }
6921  }
6922  /* bpctl_dev_arr[idx_dev].bp_fw_ver=0xa8; */
6923  printk("firmware version: 0x%x\n",
6924  bpctl_dev_arr[idx_dev].
6925  bp_fw_ver);
6926  }
6927  bpctl_dev_arr[idx_dev].wdt_status =
6928  WDT_STATUS_UNKNOWN;
6929  bpctl_dev_arr[idx_dev].reset_time = 0;
6930  atomic_set(&bpctl_dev_arr[idx_dev].wdt_busy, 0);
6931  bpctl_dev_arr[idx_dev].bp_status_un = 1;
6932 
6933  bypass_caps_init(&bpctl_dev_arr[idx_dev]);
6934 
6935  init_bypass_wd_auto(&bpctl_dev_arr[idx_dev]);
6936  init_bypass_tpl_auto(&bpctl_dev_arr[idx_dev]);
6937  if (NOKIA_SERIES
6938  (bpctl_dev_arr[idx_dev].subdevice))
6939  reset_cont(&bpctl_dev_arr[idx_dev]);
6940  }
6941 #ifdef BP_SELF_TEST
6942  if ((bpctl_dev_arr[idx_dev].bp_tx_data =
6943  kmalloc(BPTEST_DATA_LEN, GFP_KERNEL))) {
6944 
6945  memset(bpctl_dev_arr[idx_dev].bp_tx_data, 0x0,
6946  BPTEST_DATA_LEN);
6947 
6948  memset(bpctl_dev_arr[idx_dev].bp_tx_data, 0xff,
6949  6);
6950  memset(bpctl_dev_arr[idx_dev].bp_tx_data + 6,
6951  0x0, 1);
6952  memset(bpctl_dev_arr[idx_dev].bp_tx_data + 7,
6953  0xaa, 5);
6954 
6955 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9))
6956  bpctl_dev_arr[idx_dev].bp_tx_data[12] =
6957  (ETH_P_BPTEST >> 8) & 0xff;
6958  bpctl_dev_arr[idx_dev].bp_tx_data[13] =
6959  ETH_P_BPTEST & 0xff;
6960 #else
6961  *(__be16 *) (bpctl_dev_arr[idx_dev].bp_tx_data +
6962  12) = htons(ETH_P_BPTEST);
6963 #endif
6964 
6965  } else
6966  printk("bp_ctl: Memory allocation error!\n");
6967 #endif
6968  idx_dev++;
6969 
6970  }
6971  }
6972  if_scan_init();
6973 
6974  sema_init(&bpctl_sema, 1);
6975  spin_lock_init(&bpvm_lock);
6976  {
6977 
6978  bpctl_dev_t *pbpctl_dev_c = NULL;
6979  for (idx_dev = 0;
6980  ((bpctl_dev_arr[idx_dev].pdev != NULL)
6981  && (idx_dev < device_num)); idx_dev++) {
6982  if (bpctl_dev_arr[idx_dev].bp_10g9) {
6983  pbpctl_dev_c =
6984  get_status_port_fn(&bpctl_dev_arr[idx_dev]);
6985  if (is_bypass_fn(&bpctl_dev_arr[idx_dev])) {
6986  printk(KERN_INFO "%s found, ",
6987  bpctl_dev_arr[idx_dev].name);
6988  bpctl_dev_arr[idx_dev].bp_fw_ver =
6989  bypass_fw_ver(&bpctl_dev_arr
6990  [idx_dev]);
6991  printk("firmware version: 0x%x\n",
6992  bpctl_dev_arr[idx_dev].
6993  bp_fw_ver);
6994 
6995  }
6996  bpctl_dev_arr[idx_dev].wdt_status =
6997  WDT_STATUS_UNKNOWN;
6998  bpctl_dev_arr[idx_dev].reset_time = 0;
6999  atomic_set(&bpctl_dev_arr[idx_dev].wdt_busy, 0);
7000  bpctl_dev_arr[idx_dev].bp_status_un = 1;
7001 
7002  bypass_caps_init(&bpctl_dev_arr[idx_dev]);
7003 
7004  init_bypass_wd_auto(&bpctl_dev_arr[idx_dev]);
7005  init_bypass_tpl_auto(&bpctl_dev_arr[idx_dev]);
7006 
7007  }
7008 
7009  }
7010  }
7011 
7012 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7013  inter_module_register("is_bypass_sd", THIS_MODULE, &is_bypass_sd);
7014  inter_module_register("get_bypass_slave_sd", THIS_MODULE,
7015  &get_bypass_slave_sd);
7016  inter_module_register("get_bypass_caps_sd", THIS_MODULE,
7017  &get_bypass_caps_sd);
7018  inter_module_register("get_wd_set_caps_sd", THIS_MODULE,
7019  &get_wd_set_caps_sd);
7020  inter_module_register("set_bypass_sd", THIS_MODULE, &set_bypass_sd);
7021  inter_module_register("get_bypass_sd", THIS_MODULE, &get_bypass_sd);
7022  inter_module_register("get_bypass_change_sd", THIS_MODULE,
7023  &get_bypass_change_sd);
7024  inter_module_register("set_dis_bypass_sd", THIS_MODULE,
7025  &set_dis_bypass_sd);
7026  inter_module_register("get_dis_bypass_sd", THIS_MODULE,
7027  &get_dis_bypass_sd);
7028  inter_module_register("set_bypass_pwoff_sd", THIS_MODULE,
7029  &set_bypass_pwoff_sd);
7030  inter_module_register("get_bypass_pwoff_sd", THIS_MODULE,
7031  &get_bypass_pwoff_sd);
7032  inter_module_register("set_bypass_pwup_sd", THIS_MODULE,
7033  &set_bypass_pwup_sd);
7034  inter_module_register("get_bypass_pwup_sd", THIS_MODULE,
7035  &get_bypass_pwup_sd);
7036  inter_module_register("get_bypass_wd_sd", THIS_MODULE,
7037  &get_bypass_wd_sd);
7038  inter_module_register("set_bypass_wd_sd", THIS_MODULE,
7039  &set_bypass_wd_sd);
7040  inter_module_register("get_wd_expire_time_sd", THIS_MODULE,
7041  &get_wd_expire_time_sd);
7042  inter_module_register("reset_bypass_wd_timer_sd", THIS_MODULE,
7043  &reset_bypass_wd_timer_sd);
7044  inter_module_register("set_std_nic_sd", THIS_MODULE, &set_std_nic_sd);
7045  inter_module_register("get_std_nic_sd", THIS_MODULE, &get_std_nic_sd);
7046  inter_module_register("set_tx_sd", THIS_MODULE, &set_tx_sd);
7047  inter_module_register("get_tx_sd", THIS_MODULE, &get_tx_sd);
7048  inter_module_register("set_tpl_sd", THIS_MODULE, &set_tpl_sd);
7049  inter_module_register("get_tpl_sd", THIS_MODULE, &get_tpl_sd);
7050 
7051  inter_module_register("set_bp_hw_reset_sd", THIS_MODULE,
7052  &set_bp_hw_reset_sd);
7053  inter_module_register("get_bp_hw_reset_sd", THIS_MODULE,
7054  &get_bp_hw_reset_sd);
7055 
7056  inter_module_register("set_tap_sd", THIS_MODULE, &set_tap_sd);
7057  inter_module_register("get_tap_sd", THIS_MODULE, &get_tap_sd);
7058  inter_module_register("get_tap_change_sd", THIS_MODULE,
7059  &get_tap_change_sd);
7060  inter_module_register("set_dis_tap_sd", THIS_MODULE, &set_dis_tap_sd);
7061  inter_module_register("get_dis_tap_sd", THIS_MODULE, &get_dis_tap_sd);
7062  inter_module_register("set_tap_pwup_sd", THIS_MODULE, &set_tap_pwup_sd);
7063  inter_module_register("get_tap_pwup_sd", THIS_MODULE, &get_tap_pwup_sd);
7064  inter_module_register("set_bp_disc_sd", THIS_MODULE, &set_bp_disc_sd);
7065  inter_module_register("get_bp_disc_sd", THIS_MODULE, &get_bp_disc_sd);
7066  inter_module_register("get_bp_disc_change_sd", THIS_MODULE,
7067  &get_bp_disc_change_sd);
7068  inter_module_register("set_bp_dis_disc_sd", THIS_MODULE,
7069  &set_bp_dis_disc_sd);
7070  inter_module_register("get_bp_dis_disc_sd", THIS_MODULE,
7071  &get_bp_dis_disc_sd);
7072  inter_module_register("set_bp_disc_pwup_sd", THIS_MODULE,
7073  &set_bp_disc_pwup_sd);
7074  inter_module_register("get_bp_disc_pwup_sd", THIS_MODULE,
7075  &get_bp_disc_pwup_sd);
7076  inter_module_register("set_wd_exp_mode_sd", THIS_MODULE,
7077  &set_wd_exp_mode_sd);
7078  inter_module_register("get_wd_exp_mode_sd", THIS_MODULE,
7079  &get_wd_exp_mode_sd);
7080  inter_module_register("set_wd_autoreset_sd", THIS_MODULE,
7081  &set_wd_autoreset_sd);
7082  inter_module_register("get_wd_autoreset_sd", THIS_MODULE,
7083  &get_wd_autoreset_sd);
7084  inter_module_register("get_bypass_info_sd", THIS_MODULE,
7085  &get_bypass_info_sd);
7086  inter_module_register("bp_if_scan_sd", THIS_MODULE, &bp_if_scan_sd);
7087 
7088 #endif
7089  register_netdevice_notifier(&bp_notifier_block);
7090 #ifdef BP_PROC_SUPPORT
7091  {
7092  int i = 0;
7093  /* unsigned long flags; */
7094  /* rcu_read_lock(); */
7095  bp_proc_create();
7096  for (i = 0; i < device_num; i++) {
7097  if (bpctl_dev_arr[i].ifindex) {
7098  /* spin_lock_irqsave(&bpvm_lock, flags); */
7099  bypass_proc_remove_dev_sd(&bpctl_dev_arr[i]);
7100  bypass_proc_create_dev_sd(&bpctl_dev_arr[i]);
7101  /* spin_unlock_irqrestore(&bpvm_lock, flags); */
7102  }
7103 
7104  }
7105  /* rcu_read_unlock(); */
7106  }
7107 #endif
7108 
7109  return 0;
7110 }
7111 
7112 /*
7113 * Cleanup - unregister the appropriate file from /proc
7114 */
7115 static void __exit bypass_cleanup_module(void)
7116 {
7117  int i;
7118 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23))
7119  int ret;
7120 #endif
7121  unregister_netdevice_notifier(&bp_notifier_block);
7122 
7123 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7124  inter_module_unregister("is_bypass_sd");
7125  inter_module_unregister("get_bypass_slave_sd");
7126  inter_module_unregister("get_bypass_caps_sd");
7127  inter_module_unregister("get_wd_set_caps_sd");
7128  inter_module_unregister("set_bypass_sd");
7129  inter_module_unregister("get_bypass_sd");
7130  inter_module_unregister("get_bypass_change_sd");
7131  inter_module_unregister("set_dis_bypass_sd");
7132  inter_module_unregister("get_dis_bypass_sd");
7133  inter_module_unregister("set_bypass_pwoff_sd");
7134  inter_module_unregister("get_bypass_pwoff_sd");
7135  inter_module_unregister("set_bypass_pwup_sd");
7136  inter_module_unregister("get_bypass_pwup_sd");
7137  inter_module_unregister("set_bypass_wd_sd");
7138  inter_module_unregister("get_bypass_wd_sd");
7139  inter_module_unregister("get_wd_expire_time_sd");
7140  inter_module_unregister("reset_bypass_wd_timer_sd");
7141  inter_module_unregister("set_std_nic_sd");
7142  inter_module_unregister("get_std_nic_sd");
7143  inter_module_unregister("set_tx_sd");
7144  inter_module_unregister("get_tx_sd");
7145  inter_module_unregister("set_tpl_sd");
7146  inter_module_unregister("get_tpl_sd");
7147  inter_module_unregister("set_tap_sd");
7148  inter_module_unregister("get_tap_sd");
7149  inter_module_unregister("get_tap_change_sd");
7150  inter_module_unregister("set_dis_tap_sd");
7151  inter_module_unregister("get_dis_tap_sd");
7152  inter_module_unregister("set_tap_pwup_sd");
7153  inter_module_unregister("get_tap_pwup_sd");
7154  inter_module_unregister("set_bp_disc_sd");
7155  inter_module_unregister("get_bp_disc_sd");
7156  inter_module_unregister("get_bp_disc_change_sd");
7157  inter_module_unregister("set_bp_dis_disc_sd");
7158  inter_module_unregister("get_bp_dis_disc_sd");
7159  inter_module_unregister("set_bp_disc_pwup_sd");
7160  inter_module_unregister("get_bp_disc_pwup_sd");
7161  inter_module_unregister("set_wd_exp_mode_sd");
7162  inter_module_unregister("get_wd_exp_mode_sd");
7163  inter_module_unregister("set_wd_autoreset_sd");
7164  inter_module_unregister("get_wd_autoreset_sd");
7165  inter_module_unregister("get_bypass_info_sd");
7166  inter_module_unregister("bp_if_scan_sd");
7167 
7168 #endif
7169 
7170  for (i = 0; i < device_num; i++) {
7171  /* unsigned long flags; */
7172 #ifdef BP_PROC_SUPPORT
7173 /* spin_lock_irqsave(&bpvm_lock, flags);
7174  rcu_read_lock(); */
7175  bypass_proc_remove_dev_sd(&bpctl_dev_arr[i]);
7176 /* spin_unlock_irqrestore(&bpvm_lock, flags);
7177  rcu_read_unlock(); */
7178 #endif
7179  remove_bypass_wd_auto(&bpctl_dev_arr[i]);
7180  bpctl_dev_arr[i].reset_time = 0;
7181 
7182  remove_bypass_tpl_auto(&bpctl_dev_arr[i]);
7183  }
7184 
7185  /* unmap all devices */
7186  for (i = 0; i < device_num; i++) {
7187 #ifdef BP_SELF_TEST
7188  if (bpctl_dev_arr[i].bp_tx_data)
7189  kfree(bpctl_dev_arr[i].bp_tx_data);
7190 #endif
7191  iounmap((void *)(bpctl_dev_arr[i].mem_map));
7192  }
7193 
7194  /* free all devices space */
7195  if (bpctl_dev_arr)
7196  kfree(bpctl_dev_arr);
7197 
7198 /*
7199 * Unregister the device
7200 */
7201 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23))
7202  ret = unregister_chrdev(major_num, DEVICE_NAME);
7203 /*
7204 * If there's an error, report it
7205 */
7206  if (ret < 0)
7207  printk("Error in module_unregister_chrdev: %d\n", ret);
7208 #else
7209  unregister_chrdev(major_num, DEVICE_NAME);
7210 
7211 #endif
7212 }
7213 
7214 module_init(bypass_init_module);
7215 module_exit(bypass_cleanup_module);
7216 
7217 int is_bypass_sd(int ifindex)
7218 {
7219  return is_bypass(get_dev_idx_p(ifindex));
7220 }
7221 
7222 int set_bypass_sd(int ifindex, int bypass_mode)
7223 {
7224 
7225  return set_bypass_fn(get_dev_idx_p(ifindex), bypass_mode);
7226 }
7227 
7228 int get_bypass_sd(int ifindex)
7229 {
7230 
7231  return get_bypass_fn(get_dev_idx_p(ifindex));
7232 }
7233 
7234 int get_bypass_change_sd(int ifindex)
7235 {
7236 
7237  return get_bypass_change_fn(get_dev_idx_p(ifindex));
7238 }
7239 
7240 int set_dis_bypass_sd(int ifindex, int dis_param)
7241 {
7242  return set_dis_bypass_fn(get_dev_idx_p(ifindex), dis_param);
7243 }
7244 
7245 int get_dis_bypass_sd(int ifindex)
7246 {
7247 
7248  return get_dis_bypass_fn(get_dev_idx_p(ifindex));
7249 }
7250 
7251 int set_bypass_pwoff_sd(int ifindex, int bypass_mode)
7252 {
7253  return set_bypass_pwoff_fn(get_dev_idx_p(ifindex), bypass_mode);
7254 
7255 }
7256 
7257 int get_bypass_pwoff_sd(int ifindex)
7258 {
7259  return get_bypass_pwoff_fn(get_dev_idx_p(ifindex));
7260 
7261 }
7262 
7263 int set_bypass_pwup_sd(int ifindex, int bypass_mode)
7264 {
7265  return set_bypass_pwup_fn(get_dev_idx_p(ifindex), bypass_mode);
7266 
7267 }
7268 
7269 int get_bypass_pwup_sd(int ifindex)
7270 {
7271  return get_bypass_pwup_fn(get_dev_idx_p(ifindex));
7272 
7273 }
7274 
7275 int set_bypass_wd_sd(int if_index, int ms_timeout, int *ms_timeout_set)
7276 {
7277  if ((is_bypass(get_dev_idx_p(if_index))) <= 0)
7278  return BP_NOT_CAP;
7279  *ms_timeout_set = set_bypass_wd_fn(get_dev_idx_p(if_index), ms_timeout);
7280  return 0;
7281 }
7282 
7283 int get_bypass_wd_sd(int ifindex, int *timeout)
7284 {
7285  return get_bypass_wd_fn(get_dev_idx_p(ifindex), timeout);
7286 
7287 }
7288 
7289 int get_wd_expire_time_sd(int ifindex, int *time_left)
7290 {
7291  return get_wd_expire_time_fn(get_dev_idx_p(ifindex), time_left);
7292 }
7293 
7294 int reset_bypass_wd_timer_sd(int ifindex)
7295 {
7296  return reset_bypass_wd_timer_fn(get_dev_idx_p(ifindex));
7297 
7298 }
7299 
7300 int get_wd_set_caps_sd(int ifindex)
7301 {
7302  return get_wd_set_caps_fn(get_dev_idx_p(ifindex));
7303 
7304 }
7305 
7306 int set_std_nic_sd(int ifindex, int nic_mode)
7307 {
7308  return set_std_nic_fn(get_dev_idx_p(ifindex), nic_mode);
7309 
7310 }
7311 
7312 int get_std_nic_sd(int ifindex)
7313 {
7314  return get_std_nic_fn(get_dev_idx_p(ifindex));
7315 
7316 }
7317 
7318 int set_tap_sd(int ifindex, int tap_mode)
7319 {
7320  return set_tap_fn(get_dev_idx_p(ifindex), tap_mode);
7321 
7322 }
7323 
7324 int get_tap_sd(int ifindex)
7325 {
7326  return get_tap_fn(get_dev_idx_p(ifindex));
7327 
7328 }
7329 
7330 int set_tap_pwup_sd(int ifindex, int tap_mode)
7331 {
7332  return set_tap_pwup_fn(get_dev_idx_p(ifindex), tap_mode);
7333 
7334 }
7335 
7336 int get_tap_pwup_sd(int ifindex)
7337 {
7338  return get_tap_pwup_fn(get_dev_idx_p(ifindex));
7339 
7340 }
7341 
7342 int get_tap_change_sd(int ifindex)
7343 {
7344  return get_tap_change_fn(get_dev_idx_p(ifindex));
7345 
7346 }
7347 
7348 int set_dis_tap_sd(int ifindex, int dis_param)
7349 {
7350  return set_dis_tap_fn(get_dev_idx_p(ifindex), dis_param);
7351 
7352 }
7353 
7354 int get_dis_tap_sd(int ifindex)
7355 {
7356  return get_dis_tap_fn(get_dev_idx_p(ifindex));
7357 
7358 }
7359 
7360 int set_bp_disc_sd(int ifindex, int disc_mode)
7361 {
7362  return set_disc_fn(get_dev_idx_p(ifindex), disc_mode);
7363 
7364 }
7365 
7366 int get_bp_disc_sd(int ifindex)
7367 {
7368  return get_disc_fn(get_dev_idx_p(ifindex));
7369 
7370 }
7371 
7372 int set_bp_disc_pwup_sd(int ifindex, int disc_mode)
7373 {
7374  return set_disc_pwup_fn(get_dev_idx_p(ifindex), disc_mode);
7375 
7376 }
7377 
7378 int get_bp_disc_pwup_sd(int ifindex)
7379 {
7380  return get_disc_pwup_fn(get_dev_idx_p(ifindex));
7381 
7382 }
7383 
7384 int get_bp_disc_change_sd(int ifindex)
7385 {
7386  return get_disc_change_fn(get_dev_idx_p(ifindex));
7387 
7388 }
7389 
7390 int set_bp_dis_disc_sd(int ifindex, int dis_param)
7391 {
7392  return set_dis_disc_fn(get_dev_idx_p(ifindex), dis_param);
7393 
7394 }
7395 
7396 int get_bp_dis_disc_sd(int ifindex)
7397 {
7398  return get_dis_disc_fn(get_dev_idx_p(ifindex));
7399 
7400 }
7401 
7402 int get_wd_exp_mode_sd(int ifindex)
7403 {
7404  return get_wd_exp_mode_fn(get_dev_idx_p(ifindex));
7405 }
7406 
7407 int set_wd_exp_mode_sd(int ifindex, int param)
7408 {
7409  return set_wd_exp_mode_fn(get_dev_idx_p(ifindex), param);
7410 
7411 }
7412 
7413 int reset_cont_sd(int ifindex)
7414 {
7415  return reset_cont_fn(get_dev_idx_p(ifindex));
7416 
7417 }
7418 
7419 int set_tx_sd(int ifindex, int tx_state)
7420 {
7421  return set_tx_fn(get_dev_idx_p(ifindex), tx_state);
7422 
7423 }
7424 
7425 int set_tpl_sd(int ifindex, int tpl_state)
7426 {
7427  return set_tpl_fn(get_dev_idx_p(ifindex), tpl_state);
7428 
7429 }
7430 
7431 int set_bp_hw_reset_sd(int ifindex, int status)
7432 {
7433  return set_bp_hw_reset_fn(get_dev_idx_p(ifindex), status);
7434 
7435 }
7436 
7437 int set_wd_autoreset_sd(int ifindex, int param)
7438 {
7439  return set_wd_autoreset_fn(get_dev_idx_p(ifindex), param);
7440 
7441 }
7442 
7443 int get_wd_autoreset_sd(int ifindex)
7444 {
7445  return get_wd_autoreset_fn(get_dev_idx_p(ifindex));
7446 
7447 }
7448 
7449 int get_bypass_caps_sd(int ifindex)
7450 {
7451  return get_bypass_caps_fn(get_dev_idx_p(ifindex));
7452 }
7453 
7454 int get_bypass_slave_sd(int ifindex)
7455 {
7456  bpctl_dev_t *pbpctl_dev_out;
7457  int ret = get_bypass_slave_fn(get_dev_idx_p(ifindex), &pbpctl_dev_out);
7458  if (ret == 1)
7459  return pbpctl_dev_out->ifindex;
7460  return -1;
7461 
7462 }
7463 
7464 int get_tx_sd(int ifindex)
7465 {
7466  return get_tx_fn(get_dev_idx_p(ifindex));
7467 
7468 }
7469 
7470 int get_tpl_sd(int ifindex)
7471 {
7472  return get_tpl_fn(get_dev_idx_p(ifindex));
7473 
7474 }
7475 
7476 int get_bp_hw_reset_sd(int ifindex)
7477 {
7478  return get_bp_hw_reset_fn(get_dev_idx_p(ifindex));
7479 
7480 }
7481 
7482 int get_bypass_info_sd(int ifindex, struct bp_info *bp_info)
7483 {
7484  return get_bypass_info_fn(get_dev_idx_p(ifindex), bp_info->prod_name, &bp_info->fw_ver);
7485 }
7486 
7487 int bp_if_scan_sd(void)
7488 {
7489  if_scan_init();
7490  return 0;
7491 }
7492 
7493 EXPORT_SYMBOL_NOVERS(is_bypass_sd);
7494 EXPORT_SYMBOL_NOVERS(get_bypass_slave_sd);
7495 EXPORT_SYMBOL_NOVERS(get_bypass_caps_sd);
7496 EXPORT_SYMBOL_NOVERS(get_wd_set_caps_sd);
7497 EXPORT_SYMBOL_NOVERS(set_bypass_sd);
7498 EXPORT_SYMBOL_NOVERS(get_bypass_sd);
7499 EXPORT_SYMBOL_NOVERS(get_bypass_change_sd);
7500 EXPORT_SYMBOL_NOVERS(set_dis_bypass_sd);
7501 EXPORT_SYMBOL_NOVERS(get_dis_bypass_sd);
7502 EXPORT_SYMBOL_NOVERS(set_bypass_pwoff_sd);
7503 EXPORT_SYMBOL_NOVERS(get_bypass_pwoff_sd);
7504 EXPORT_SYMBOL_NOVERS(set_bypass_pwup_sd);
7505 EXPORT_SYMBOL_NOVERS(get_bypass_pwup_sd);
7506 EXPORT_SYMBOL_NOVERS(set_bypass_wd_sd);
7507 EXPORT_SYMBOL_NOVERS(get_bypass_wd_sd);
7508 EXPORT_SYMBOL_NOVERS(get_wd_expire_time_sd);
7509 EXPORT_SYMBOL_NOVERS(reset_bypass_wd_timer_sd);
7510 EXPORT_SYMBOL_NOVERS(set_std_nic_sd);
7511 EXPORT_SYMBOL_NOVERS(get_std_nic_sd);
7512 EXPORT_SYMBOL_NOVERS(set_tx_sd);
7513 EXPORT_SYMBOL_NOVERS(get_tx_sd);
7514 EXPORT_SYMBOL_NOVERS(set_tpl_sd);
7515 EXPORT_SYMBOL_NOVERS(get_tpl_sd);
7516 EXPORT_SYMBOL_NOVERS(set_bp_hw_reset_sd);
7517 EXPORT_SYMBOL_NOVERS(get_bp_hw_reset_sd);
7518 EXPORT_SYMBOL_NOVERS(set_tap_sd);
7519 EXPORT_SYMBOL_NOVERS(get_tap_sd);
7520 EXPORT_SYMBOL_NOVERS(get_tap_change_sd);
7521 EXPORT_SYMBOL_NOVERS(set_dis_tap_sd);
7522 EXPORT_SYMBOL_NOVERS(get_dis_tap_sd);
7523 EXPORT_SYMBOL_NOVERS(set_tap_pwup_sd);
7524 EXPORT_SYMBOL_NOVERS(get_tap_pwup_sd);
7525 EXPORT_SYMBOL_NOVERS(set_wd_exp_mode_sd);
7526 EXPORT_SYMBOL_NOVERS(get_wd_exp_mode_sd);
7527 EXPORT_SYMBOL_NOVERS(set_wd_autoreset_sd);
7528 EXPORT_SYMBOL_NOVERS(get_wd_autoreset_sd);
7529 EXPORT_SYMBOL_NOVERS(set_bp_disc_sd);
7530 EXPORT_SYMBOL_NOVERS(get_bp_disc_sd);
7531 EXPORT_SYMBOL_NOVERS(get_bp_disc_change_sd);
7532 EXPORT_SYMBOL_NOVERS(set_bp_dis_disc_sd);
7533 EXPORT_SYMBOL_NOVERS(get_bp_dis_disc_sd);
7534 EXPORT_SYMBOL_NOVERS(set_bp_disc_pwup_sd);
7535 EXPORT_SYMBOL_NOVERS(get_bp_disc_pwup_sd);
7536 EXPORT_SYMBOL_NOVERS(get_bypass_info_sd);
7537 EXPORT_SYMBOL_NOVERS(bp_if_scan_sd);
7538 
7539 #define BP_PROC_DIR "bypass"
7540 
7541 #define GPIO6_SET_ENTRY_SD "gpio6_set"
7542 #define GPIO6_CLEAR_ENTRY_SD "gpio6_clear"
7543 
7544 #define GPIO7_SET_ENTRY_SD "gpio7_set"
7545 #define GPIO7_CLEAR_ENTRY_SD "gpio7_clear"
7546 
7547 #define PULSE_SET_ENTRY_SD "pulse_set"
7548 #define ZERO_SET_ENTRY_SD "zero_set"
7549 #define PULSE_GET1_ENTRY_SD "pulse_get1"
7550 #define PULSE_GET2_ENTRY_SD "pulse_get2"
7551 
7552 #define CMND_ON_ENTRY_SD "cmnd_on"
7553 #define CMND_OFF_ENTRY_SD "cmnd_off"
7554 #define RESET_CONT_ENTRY_SD "reset_cont"
7555 
7556  /*COMMANDS*/
7557 #define BYPASS_INFO_ENTRY_SD "bypass_info"
7558 #define BYPASS_SLAVE_ENTRY_SD "bypass_slave"
7559 #define BYPASS_CAPS_ENTRY_SD "bypass_caps"
7560 #define WD_SET_CAPS_ENTRY_SD "wd_set_caps"
7561 #define BYPASS_ENTRY_SD "bypass"
7562 #define BYPASS_CHANGE_ENTRY_SD "bypass_change"
7563 #define BYPASS_WD_ENTRY_SD "bypass_wd"
7564 #define WD_EXPIRE_TIME_ENTRY_SD "wd_expire_time"
7565 #define RESET_BYPASS_WD_ENTRY_SD "reset_bypass_wd"
7566 #define DIS_BYPASS_ENTRY_SD "dis_bypass"
7567 #define BYPASS_PWUP_ENTRY_SD "bypass_pwup"
7568 #define BYPASS_PWOFF_ENTRY_SD "bypass_pwoff"
7569 #define STD_NIC_ENTRY_SD "std_nic"
7570 #define STD_NIC_ENTRY_SD "std_nic"
7571 #define TAP_ENTRY_SD "tap"
7572 #define TAP_CHANGE_ENTRY_SD "tap_change"
7573 #define DIS_TAP_ENTRY_SD "dis_tap"
7574 #define TAP_PWUP_ENTRY_SD "tap_pwup"
7575 #define TWO_PORT_LINK_ENTRY_SD "two_port_link"
7576 #define WD_EXP_MODE_ENTRY_SD "wd_exp_mode"
7577 #define WD_AUTORESET_ENTRY_SD "wd_autoreset"
7578 #define TPL_ENTRY_SD "tpl"
7579 #define WAIT_AT_PWUP_ENTRY_SD "wait_at_pwup"
7580 #define HW_RESET_ENTRY_SD "hw_reset"
7581 #define DISC_ENTRY_SD "disc"
7582 #define DISC_CHANGE_ENTRY_SD "disc_change"
7583 #define DIS_DISC_ENTRY_SD "dis_disc"
7584 #define DISC_PWUP_ENTRY_SD "disc_pwup"
7585 static struct proc_dir_entry *bp_procfs_dir;
7586 
7587 static struct proc_dir_entry *proc_getdir(char *name,
7588  struct proc_dir_entry *proc_dir)
7589 {
7590  struct proc_dir_entry *pde = proc_dir;
7591 
7592  for (pde = pde->subdir; pde; pde = pde->next) {
7593  if (pde->namelen && (strcmp(name, pde->name) == 0)) {
7594  /* directory exists */
7595  break;
7596  }
7597  }
7598  if (pde == (struct proc_dir_entry *)0) {
7599  /* create the directory */
7600 #if (LINUX_VERSION_CODE > 0x20300)
7601  pde = proc_mkdir(name, proc_dir);
7602 #else
7603  pde = create_proc_entry(name, S_IFDIR, proc_dir);
7604 #endif
7605  if (pde == (struct proc_dir_entry *)0) {
7606 
7607  return pde;
7608  }
7609  }
7610 
7611  return pde;
7612 }
7613 
7614 int bp_proc_create(void)
7615 {
7616  bp_procfs_dir = proc_getdir(BP_PROC_DIR, init_net.proc_net);
7617  if (bp_procfs_dir == (struct proc_dir_entry *)0) {
7618  printk(KERN_DEBUG
7619  "Could not create procfs nicinfo directory %s\n",
7620  BP_PROC_DIR);
7621  return -1;
7622  }
7623  return 0;
7624 }
7625 
7626 int
7627 bypass_proc_create_entry_sd(struct pfs_unit_sd *pfs_unit_curr,
7628  char *proc_name,
7629  write_proc_t *write_proc,
7630  read_proc_t *read_proc,
7631  struct proc_dir_entry *parent_pfs, void *data)
7632 {
7633  strcpy(pfs_unit_curr->proc_name, proc_name);
7634  pfs_unit_curr->proc_entry = create_proc_entry(pfs_unit_curr->proc_name,
7635  S_IFREG | S_IRUSR |
7636  S_IWUSR | S_IRGRP |
7637  S_IROTH, parent_pfs);
7638  if (pfs_unit_curr->proc_entry == NULL)
7639  return -1;
7640 
7641  pfs_unit_curr->proc_entry->read_proc = read_proc;
7642  pfs_unit_curr->proc_entry->write_proc = write_proc;
7643  pfs_unit_curr->proc_entry->data = data;
7644 
7645  return 0;
7646 
7647 }
7648 
7649 int
7650 get_bypass_info_pfs(char *page, char **start, off_t off, int count,
7651  int *eof, void *data)
7652 {
7653  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7654  int len = 0;
7655 
7656  len += sprintf(page, "Name\t\t\t%s\n", pbp_device_block->name);
7657  len +=
7658  sprintf(page + len, "Firmware version\t0x%x\n",
7659  pbp_device_block->bp_fw_ver);
7660 
7661  *eof = 1;
7662  return len;
7663 }
7664 
7665 int
7666 get_bypass_slave_pfs(char *page, char **start, off_t off, int count,
7667  int *eof, void *data)
7668 {
7669  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7670 
7671  int len = 0;
7672  bpctl_dev_t *pbp_device_block_slave = NULL;
7673  int idx_dev = 0;
7674  struct net_device *net_slave_dev = NULL;
7675 
7676  if ((pbp_device_block->func == 0) || (pbp_device_block->func == 2)) {
7677  for (idx_dev = 0;
7678  ((bpctl_dev_arr[idx_dev].pdev != NULL)
7679  && (idx_dev < device_num)); idx_dev++) {
7680  if ((bpctl_dev_arr[idx_dev].bus ==
7681  pbp_device_block->bus)
7682  && (bpctl_dev_arr[idx_dev].slot ==
7683  pbp_device_block->slot)) {
7684  if ((pbp_device_block->func == 0)
7685  && (bpctl_dev_arr[idx_dev].func == 1)) {
7686  pbp_device_block_slave =
7687  &bpctl_dev_arr[idx_dev];
7688  break;
7689  }
7690  if ((pbp_device_block->func == 2) &&
7691  (bpctl_dev_arr[idx_dev].func == 3)) {
7692  pbp_device_block_slave =
7693  &bpctl_dev_arr[idx_dev];
7694  break;
7695  }
7696  }
7697  }
7698  } else
7699  pbp_device_block_slave = pbp_device_block;
7700  if (!pbp_device_block_slave) {
7701  len = sprintf(page, "fail\n");
7702  *eof = 1;
7703  return len;
7704  }
7705  net_slave_dev = pbp_device_block_slave->ndev;
7706  if (net_slave_dev) {
7707  if (net_slave_dev)
7708  len = sprintf(page, "%s\n", net_slave_dev->name);
7709  else
7710  len = sprintf(page, "fail\n");
7711 
7712  }
7713 
7714  *eof = 1;
7715  return len;
7716 }
7717 
7718 int
7719 get_bypass_caps_pfs(char *page, char **start, off_t off, int count,
7720  int *eof, void *data)
7721 {
7722  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7723 
7724  int len = 0, ret = 0;
7725 
7726  ret = get_bypass_caps_fn(pbp_device_block);
7727  if (ret == BP_NOT_CAP)
7728  len = sprintf(page, "-1\n");
7729  else
7730  len = sprintf(page, "0x%x\n", ret);
7731  *eof = 1;
7732  return len;
7733 
7734 }
7735 
7736 int
7737 get_wd_set_caps_pfs(char *page, char **start, off_t off, int count,
7738  int *eof, void *data)
7739 {
7740  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7741 
7742  int len = 0, ret = 0;
7743 
7744  ret = get_wd_set_caps_fn(pbp_device_block);
7745  if (ret == BP_NOT_CAP)
7746  len = sprintf(page, "-1\n");
7747  else
7748  len = sprintf(page, "0x%x\n", ret);
7749  *eof = 1;
7750  return len;
7751 }
7752 
7753 int
7754 set_bypass_pfs(struct file *file, const char *buffer,
7755  unsigned long count, void *data)
7756 {
7757 
7758  char kbuf[256];
7759  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7760 
7761  int bypass_param = 0, length = 0;
7762 
7763  if (count > (sizeof(kbuf) - 1))
7764  return -1;
7765 
7766  if (copy_from_user(&kbuf, buffer, count)) {
7767  return -1;
7768  }
7769 
7770  kbuf[count] = '\0';
7771  length = strlen(kbuf);
7772  if (kbuf[length - 1] == '\n')
7773  kbuf[--length] = '\0';
7774 
7775  if (strcmp(kbuf, "on") == 0)
7776  bypass_param = 1;
7777  else if (strcmp(kbuf, "off") == 0)
7778  bypass_param = 0;
7779 
7780  set_bypass_fn(pbp_device_block, bypass_param);
7781 
7782  return count;
7783 }
7784 
7785 int
7786 set_tap_pfs(struct file *file, const char *buffer,
7787  unsigned long count, void *data)
7788 {
7789 
7790  char kbuf[256];
7791  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7792 
7793  int tap_param = 0, length = 0;
7794 
7795  if (count > (sizeof(kbuf) - 1))
7796  return -1;
7797 
7798  if (copy_from_user(&kbuf, buffer, count)) {
7799  return -1;
7800  }
7801 
7802  kbuf[count] = '\0';
7803  length = strlen(kbuf);
7804  if (kbuf[length - 1] == '\n')
7805  kbuf[--length] = '\0';
7806 
7807  if (strcmp(kbuf, "on") == 0)
7808  tap_param = 1;
7809  else if (strcmp(kbuf, "off") == 0)
7810  tap_param = 0;
7811 
7812  set_tap_fn(pbp_device_block, tap_param);
7813 
7814  return count;
7815 }
7816 
7817 int
7818 set_disc_pfs(struct file *file, const char *buffer,
7819  unsigned long count, void *data)
7820 {
7821 
7822  char kbuf[256];
7823  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7824 
7825  int tap_param = 0, length = 0;
7826 
7827  if (count > (sizeof(kbuf) - 1))
7828  return -1;
7829 
7830  if (copy_from_user(&kbuf, buffer, count)) {
7831  return -1;
7832  }
7833 
7834  kbuf[count] = '\0';
7835  length = strlen(kbuf);
7836  if (kbuf[length - 1] == '\n')
7837  kbuf[--length] = '\0';
7838 
7839  if (strcmp(kbuf, "on") == 0)
7840  tap_param = 1;
7841  else if (strcmp(kbuf, "off") == 0)
7842  tap_param = 0;
7843 
7844  set_disc_fn(pbp_device_block, tap_param);
7845 
7846  return count;
7847 }
7848 
7849 int
7850 get_bypass_pfs(char *page, char **start, off_t off, int count,
7851  int *eof, void *data)
7852 {
7853  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7854 
7855  int len = 0, ret = 0;
7856 
7857  ret = get_bypass_fn(pbp_device_block);
7858  if (ret == BP_NOT_CAP)
7859  len = sprintf(page, "fail\n");
7860  else if (ret == 1)
7861  len = sprintf(page, "on\n");
7862  else if (ret == 0)
7863  len = sprintf(page, "off\n");
7864 
7865  *eof = 1;
7866  return len;
7867 }
7868 
7869 int
7870 get_tap_pfs(char *page, char **start, off_t off, int count,
7871  int *eof, void *data)
7872 {
7873  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7874 
7875  int len = 0, ret = 0;
7876 
7877  ret = get_tap_fn(pbp_device_block);
7878  if (ret == BP_NOT_CAP)
7879  len = sprintf(page, "fail\n");
7880  else if (ret == 1)
7881  len = sprintf(page, "on\n");
7882  else if (ret == 0)
7883  len = sprintf(page, "off\n");
7884 
7885  *eof = 1;
7886  return len;
7887 }
7888 
7889 int
7890 get_disc_pfs(char *page, char **start, off_t off, int count,
7891  int *eof, void *data)
7892 {
7893  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7894 
7895  int len = 0, ret = 0;
7896 
7897  ret = get_disc_fn(pbp_device_block);
7898  if (ret == BP_NOT_CAP)
7899  len = sprintf(page, "fail\n");
7900  else if (ret == 1)
7901  len = sprintf(page, "on\n");
7902  else if (ret == 0)
7903  len = sprintf(page, "off\n");
7904 
7905  *eof = 1;
7906  return len;
7907 }
7908 
7909 int
7910 get_bypass_change_pfs(char *page, char **start, off_t off, int count,
7911  int *eof, void *data)
7912 {
7913  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7914 
7915  int len = 0, ret = 0;
7916 
7917  ret = get_bypass_change_fn(pbp_device_block);
7918  if (ret == 1)
7919  len = sprintf(page, "on\n");
7920  else if (ret == 0)
7921  len = sprintf(page, "off\n");
7922  else
7923  len = sprintf(page, "fail\n");
7924 
7925  *eof = 1;
7926  return len;
7927 }
7928 
7929 int
7930 get_tap_change_pfs(char *page, char **start, off_t off, int count,
7931  int *eof, void *data)
7932 {
7933  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7934 
7935  int len = 0, ret = 0;
7936 
7937  ret = get_tap_change_fn(pbp_device_block);
7938  if (ret == 1)
7939  len = sprintf(page, "on\n");
7940  else if (ret == 0)
7941  len = sprintf(page, "off\n");
7942  else
7943  len = sprintf(page, "fail\n");
7944 
7945  *eof = 1;
7946  return len;
7947 }
7948 
7949 int
7950 get_disc_change_pfs(char *page, char **start, off_t off, int count,
7951  int *eof, void *data)
7952 {
7953  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7954 
7955  int len = 0, ret = 0;
7956 
7957  ret = get_disc_change_fn(pbp_device_block);
7958  if (ret == 1)
7959  len = sprintf(page, "on\n");
7960  else if (ret == 0)
7961  len = sprintf(page, "off\n");
7962  else
7963  len = sprintf(page, "fail\n");
7964 
7965  *eof = 1;
7966  return len;
7967 }
7968 
7969 #define isdigit(c) (c >= '0' && c <= '9')
7970 __inline static int atoi(char **s)
7971 {
7972  int i = 0;
7973  while (isdigit(**s))
7974  i = i * 10 + *((*s)++) - '0';
7975  return i;
7976 }
7977 
7978 int
7979 set_bypass_wd_pfs(struct file *file, const char *buffer,
7980  unsigned long count, void *data)
7981 {
7982  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7983  int timeout;
7984  int ret;
7985 
7986  ret = kstrtoint_from_user(buffer, count, 10, &timeout);
7987  if (ret)
7988  return ret;
7989  set_bypass_wd_fn(pbp_device_block, timeout);
7990 
7991  return count;
7992 }
7993 
7994 int
7995 get_bypass_wd_pfs(char *page, char **start, off_t off, int count,
7996  int *eof, void *data)
7997 {
7998  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7999 
8000  int len = 0, ret = 0, timeout = 0;
8001 
8002  ret = get_bypass_wd_fn(pbp_device_block, &timeout);
8003  if (ret == BP_NOT_CAP)
8004  len = sprintf(page, "fail\n");
8005  else if (timeout == -1)
8006  len = sprintf(page, "unknown\n");
8007  else if (timeout == 0)
8008  len = sprintf(page, "disable\n");
8009  else
8010  len = sprintf(page, "%d\n", timeout);
8011 
8012  *eof = 1;
8013  return len;
8014 }
8015 
8016 int
8017 get_wd_expire_time_pfs(char *page, char **start, off_t off, int count,
8018  int *eof, void *data)
8019 {
8020  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8021 
8022  int len = 0, ret = 0, timeout = 0;
8023 
8024  ret = get_wd_expire_time_fn(pbp_device_block, &timeout);
8025  if (ret == BP_NOT_CAP)
8026  len = sprintf(page, "fail\n");
8027  else if (timeout == -1)
8028  len = sprintf(page, "expire\n");
8029  else if (timeout == 0)
8030  len = sprintf(page, "disable\n");
8031 
8032  else
8033  len = sprintf(page, "%d\n", timeout);
8034  *eof = 1;
8035  return len;
8036 }
8037 
8038 int
8039 get_tpl_pfs(char *page, char **start, off_t off, int count,
8040  int *eof, void *data)
8041 {
8042  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8043 
8044  int len = 0, ret = 0;
8045 
8046  ret = get_tpl_fn(pbp_device_block);
8047  if (ret == BP_NOT_CAP)
8048  len = sprintf(page, "fail\n");
8049  else if (ret == 1)
8050  len = sprintf(page, "on\n");
8051  else if (ret == 0)
8052  len = sprintf(page, "off\n");
8053 
8054  *eof = 1;
8055  return len;
8056 }
8057 
8058 #ifdef PMC_FIX_FLAG
8059 int
8060 get_wait_at_pwup_pfs(char *page, char **start, off_t off, int count,
8061  int *eof, void *data)
8062 {
8063  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8064 
8065  int len = 0, ret = 0;
8066 
8067  ret = get_bp_wait_at_pwup_fn(pbp_device_block);
8068  if (ret == BP_NOT_CAP)
8069  len = sprintf(page, "fail\n");
8070  else if (ret == 1)
8071  len = sprintf(page, "on\n");
8072  else if (ret == 0)
8073  len = sprintf(page, "off\n");
8074 
8075  *eof = 1;
8076  return len;
8077 }
8078 
8079 int
8080 get_hw_reset_pfs(char *page, char **start, off_t off, int count,
8081  int *eof, void *data)
8082 {
8083  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8084 
8085  int len = 0, ret = 0;
8086 
8087  ret = get_bp_hw_reset_fn(pbp_device_block);
8088  if (ret == BP_NOT_CAP)
8089  len = sprintf(page, "fail\n");
8090  else if (ret == 1)
8091  len = sprintf(page, "on\n");
8092  else if (ret == 0)
8093  len = sprintf(page, "off\n");
8094 
8095  *eof = 1;
8096  return len;
8097 }
8098 
8099 #endif /*PMC_WAIT_FLAG */
8100 
8101 int
8102 reset_bypass_wd_pfs(char *page, char **start, off_t off, int count,
8103  int *eof, void *data)
8104 {
8105  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8106 
8107  int len = 0, ret = 0;
8108 
8109  ret = reset_bypass_wd_timer_fn(pbp_device_block);
8110  if (ret == BP_NOT_CAP)
8111  len = sprintf(page, "fail\n");
8112  else if (ret == 0)
8113  len = sprintf(page, "disable\n");
8114  else if (ret == 1)
8115  len = sprintf(page, "success\n");
8116 
8117  *eof = 1;
8118  return len;
8119 }
8120 
8121 int
8122 set_dis_bypass_pfs(struct file *file, const char *buffer,
8123  unsigned long count, void *data)
8124 {
8125 
8126  char kbuf[256];
8127  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8128 
8129  int bypass_param = 0, length = 0;
8130 
8131  if (count >= sizeof(kbuf))
8132  return -EINVAL;
8133 
8134  if (copy_from_user(&kbuf, buffer, count)) {
8135  return -1;
8136  }
8137 
8138  kbuf[count] = '\0';
8139  length = strlen(kbuf);
8140  if (kbuf[length - 1] == '\n')
8141  kbuf[--length] = '\0';
8142 
8143  if (strcmp(kbuf, "on") == 0)
8144  bypass_param = 1;
8145  else if (strcmp(kbuf, "off") == 0)
8146  bypass_param = 0;
8147 
8148  set_dis_bypass_fn(pbp_device_block, bypass_param);
8149 
8150  return count;
8151 }
8152 
8153 int
8154 set_dis_tap_pfs(struct file *file, const char *buffer,
8155  unsigned long count, void *data)
8156 {
8157 
8158  char kbuf[256];
8159  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8160 
8161  int tap_param = 0, length = 0;
8162 
8163  if (count >= sizeof(kbuf))
8164  return -EINVAL;
8165 
8166  if (copy_from_user(&kbuf, buffer, count)) {
8167  return -1;
8168  }
8169 
8170  kbuf[count] = '\0';
8171  length = strlen(kbuf);
8172  if (kbuf[length - 1] == '\n')
8173  kbuf[--length] = '\0';
8174 
8175  if (strcmp(kbuf, "on") == 0)
8176  tap_param = 1;
8177  else if (strcmp(kbuf, "off") == 0)
8178  tap_param = 0;
8179 
8180  set_dis_tap_fn(pbp_device_block, tap_param);
8181 
8182  return count;
8183 }
8184 
8185 int
8186 set_dis_disc_pfs(struct file *file, const char *buffer,
8187  unsigned long count, void *data)
8188 {
8189 
8190  char kbuf[256];
8191  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8192 
8193  int tap_param = 0, length = 0;
8194 
8195  if (count >= sizeof(kbuf))
8196  return -EINVAL;
8197 
8198  if (copy_from_user(&kbuf, buffer, count)) {
8199  return -1;
8200  }
8201 
8202  kbuf[count] = '\0';
8203  length = strlen(kbuf);
8204  if (kbuf[length - 1] == '\n')
8205  kbuf[--length] = '\0';
8206 
8207  if (strcmp(kbuf, "on") == 0)
8208  tap_param = 1;
8209  else if (strcmp(kbuf, "off") == 0)
8210  tap_param = 0;
8211 
8212  set_dis_disc_fn(pbp_device_block, tap_param);
8213 
8214  return count;
8215 }
8216 
8217 int
8218 get_dis_bypass_pfs(char *page, char **start, off_t off, int count,
8219  int *eof, void *data)
8220 {
8221  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8222 
8223  int len = 0, ret = 0;
8224 
8225  ret = get_dis_bypass_fn(pbp_device_block);
8226  if (ret == BP_NOT_CAP)
8227  len = sprintf(page, "fail\n");
8228  else if (ret == 0)
8229  len = sprintf(page, "off\n");
8230  else
8231  len = sprintf(page, "on\n");
8232 
8233  *eof = 1;
8234  return len;
8235 }
8236 
8237 int
8238 get_dis_tap_pfs(char *page, char **start, off_t off, int count,
8239  int *eof, void *data)
8240 {
8241  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8242 
8243  int len = 0, ret = 0;
8244 
8245  ret = get_dis_tap_fn(pbp_device_block);
8246  if (ret == BP_NOT_CAP)
8247  len = sprintf(page, "fail\n");
8248  else if (ret == 0)
8249  len = sprintf(page, "off\n");
8250  else
8251  len = sprintf(page, "on\n");
8252 
8253  *eof = 1;
8254  return len;
8255 }
8256 
8257 int
8258 get_dis_disc_pfs(char *page, char **start, off_t off, int count,
8259  int *eof, void *data)
8260 {
8261  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8262 
8263  int len = 0, ret = 0;
8264 
8265  ret = get_dis_disc_fn(pbp_device_block);
8266  if (ret == BP_NOT_CAP)
8267  len = sprintf(page, "fail\n");
8268  else if (ret == 0)
8269  len = sprintf(page, "off\n");
8270  else
8271  len = sprintf(page, "on\n");
8272 
8273  *eof = 1;
8274  return len;
8275 }
8276 
8277 int
8278 set_bypass_pwup_pfs(struct file *file, const char *buffer,
8279  unsigned long count, void *data)
8280 {
8281 
8282  char kbuf[256];
8283  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8284 
8285  int bypass_param = 0, length = 0;
8286 
8287  if (count >= sizeof(kbuf))
8288  return -EINVAL;
8289 
8290  if (copy_from_user(&kbuf, buffer, count)) {
8291  return -1;
8292  }
8293 
8294  kbuf[count] = '\0';
8295  length = strlen(kbuf);
8296  if (kbuf[length - 1] == '\n')
8297  kbuf[--length] = '\0';
8298 
8299  if (strcmp(kbuf, "on") == 0)
8300  bypass_param = 1;
8301  else if (strcmp(kbuf, "off") == 0)
8302  bypass_param = 0;
8303 
8304  set_bypass_pwup_fn(pbp_device_block, bypass_param);
8305 
8306  return count;
8307 }
8308 
8309 int
8310 set_bypass_pwoff_pfs(struct file *file, const char *buffer,
8311  unsigned long count, void *data)
8312 {
8313 
8314  char kbuf[256];
8315  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8316 
8317  int bypass_param = 0, length = 0;
8318 
8319  if (count >= sizeof(kbuf))
8320  return -EINVAL;
8321 
8322  if (copy_from_user(&kbuf, buffer, count)) {
8323  return -1;
8324  }
8325 
8326  kbuf[count] = '\0';
8327  length = strlen(kbuf);
8328  if (kbuf[length - 1] == '\n')
8329  kbuf[--length] = '\0';
8330 
8331  if (strcmp(kbuf, "on") == 0)
8332  bypass_param = 1;
8333  else if (strcmp(kbuf, "off") == 0)
8334  bypass_param = 0;
8335 
8336  set_bypass_pwoff_fn(pbp_device_block, bypass_param);
8337 
8338  return count;
8339 }
8340 
8341 int
8342 set_tap_pwup_pfs(struct file *file, const char *buffer,
8343  unsigned long count, void *data)
8344 {
8345 
8346  char kbuf[256];
8347  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8348 
8349  int tap_param = 0, length = 0;
8350 
8351  if (count >= sizeof(kbuf))
8352  return -EINVAL;
8353 
8354  if (copy_from_user(&kbuf, buffer, count)) {
8355  return -1;
8356  }
8357 
8358  kbuf[count] = '\0';
8359  length = strlen(kbuf);
8360  if (kbuf[length - 1] == '\n')
8361  kbuf[--length] = '\0';
8362 
8363  if (strcmp(kbuf, "on") == 0)
8364  tap_param = 1;
8365  else if (strcmp(kbuf, "off") == 0)
8366  tap_param = 0;
8367 
8368  set_tap_pwup_fn(pbp_device_block, tap_param);
8369 
8370  return count;
8371 }
8372 
8373 int
8374 set_disc_pwup_pfs(struct file *file, const char *buffer,
8375  unsigned long count, void *data)
8376 {
8377 
8378  char kbuf[256];
8379  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8380 
8381  int tap_param = 0, length = 0;
8382 
8383  if (count >= sizeof(kbuf))
8384  return -EINVAL;
8385 
8386  if (copy_from_user(&kbuf, buffer, count)) {
8387  return -1;
8388  }
8389 
8390  kbuf[count] = '\0';
8391  length = strlen(kbuf);
8392  if (kbuf[length - 1] == '\n')
8393  kbuf[--length] = '\0';
8394 
8395  if (strcmp(kbuf, "on") == 0)
8396  tap_param = 1;
8397  else if (strcmp(kbuf, "off") == 0)
8398  tap_param = 0;
8399 
8400  set_disc_pwup_fn(pbp_device_block, tap_param);
8401 
8402  return count;
8403 }
8404 
8405 int
8406 get_bypass_pwup_pfs(char *page, char **start, off_t off, int count,
8407  int *eof, void *data)
8408 {
8409  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8410 
8411  int len = 0, ret = 0;
8412 
8413  ret = get_bypass_pwup_fn(pbp_device_block);
8414  if (ret == BP_NOT_CAP)
8415  len = sprintf(page, "fail\n");
8416  else if (ret == 0)
8417  len = sprintf(page, "off\n");
8418  else
8419  len = sprintf(page, "on\n");
8420 
8421  *eof = 1;
8422  return len;
8423 }
8424 
8425 int
8426 get_bypass_pwoff_pfs(char *page, char **start, off_t off, int count,
8427  int *eof, void *data)
8428 {
8429  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8430 
8431  int len = 0, ret = 0;
8432 
8433  ret = get_bypass_pwoff_fn(pbp_device_block);
8434  if (ret == BP_NOT_CAP)
8435  len = sprintf(page, "fail\n");
8436  else if (ret == 0)
8437  len = sprintf(page, "off\n");
8438  else
8439  len = sprintf(page, "on\n");
8440 
8441  *eof = 1;
8442  return len;
8443 }
8444 
8445 int
8446 get_tap_pwup_pfs(char *page, char **start, off_t off, int count,
8447  int *eof, void *data)
8448 {
8449  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8450 
8451  int len = 0, ret = 0;
8452 
8453  ret = get_tap_pwup_fn(pbp_device_block);
8454  if (ret == BP_NOT_CAP)
8455  len = sprintf(page, "fail\n");
8456  else if (ret == 0)
8457  len = sprintf(page, "off\n");
8458  else
8459  len = sprintf(page, "on\n");
8460 
8461  *eof = 1;
8462  return len;
8463 }
8464 
8465 int
8466 get_disc_pwup_pfs(char *page, char **start, off_t off, int count,
8467  int *eof, void *data)
8468 {
8469  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8470 
8471  int len = 0, ret = 0;
8472 
8473  ret = get_disc_pwup_fn(pbp_device_block);
8474  if (ret == BP_NOT_CAP)
8475  len = sprintf(page, "fail\n");
8476  else if (ret == 0)
8477  len = sprintf(page, "off\n");
8478  else
8479  len = sprintf(page, "on\n");
8480 
8481  *eof = 1;
8482  return len;
8483 }
8484 
8485 int
8486 set_std_nic_pfs(struct file *file, const char *buffer,
8487  unsigned long count, void *data)
8488 {
8489 
8490  char kbuf[256];
8491  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8492 
8493  int bypass_param = 0, length = 0;
8494 
8495  if (count >= sizeof(kbuf))
8496  return -EINVAL;
8497 
8498  if (copy_from_user(&kbuf, buffer, count)) {
8499  return -1;
8500  }
8501 
8502  kbuf[count] = '\0';
8503  length = strlen(kbuf);
8504  if (kbuf[length - 1] == '\n')
8505  kbuf[--length] = '\0';
8506 
8507  if (strcmp(kbuf, "on") == 0)
8508  bypass_param = 1;
8509  else if (strcmp(kbuf, "off") == 0)
8510  bypass_param = 0;
8511 
8512  set_std_nic_fn(pbp_device_block, bypass_param);
8513 
8514  return count;
8515 }
8516 
8517 int
8518 get_std_nic_pfs(char *page, char **start, off_t off, int count,
8519  int *eof, void *data)
8520 {
8521  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8522 
8523  int len = 0, ret = 0;
8524 
8525  ret = get_std_nic_fn(pbp_device_block);
8526  if (ret == BP_NOT_CAP)
8527  len = sprintf(page, "fail\n");
8528  else if (ret == 0)
8529  len = sprintf(page, "off\n");
8530  else
8531  len = sprintf(page, "on\n");
8532 
8533  *eof = 1;
8534  return len;
8535 }
8536 
8537 int
8538 get_wd_exp_mode_pfs(char *page, char **start, off_t off, int count,
8539  int *eof, void *data)
8540 {
8541  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8542 
8543  int len = 0, ret = 0;
8544 
8545  ret = get_wd_exp_mode_fn(pbp_device_block);
8546  if (ret == 1)
8547  len = sprintf(page, "tap\n");
8548  else if (ret == 0)
8549  len = sprintf(page, "bypass\n");
8550  else if (ret == 2)
8551  len = sprintf(page, "disc\n");
8552 
8553  else
8554  len = sprintf(page, "fail\n");
8555 
8556  *eof = 1;
8557  return len;
8558 }
8559 
8560 int
8561 set_wd_exp_mode_pfs(struct file *file, const char *buffer,
8562  unsigned long count, void *data)
8563 {
8564 
8565  char kbuf[256];
8566  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8567 
8568  int bypass_param = 0, length = 0;
8569 
8570  if (count > (sizeof(kbuf) - 1))
8571  return -1;
8572 
8573  if (copy_from_user(&kbuf, buffer, count)) {
8574  return -1;
8575  }
8576 
8577  kbuf[count] = '\0';
8578  length = strlen(kbuf);
8579  if (kbuf[length - 1] == '\n')
8580  kbuf[--length] = '\0';
8581 
8582  if (strcmp(kbuf, "tap") == 0)
8583  bypass_param = 1;
8584  else if (strcmp(kbuf, "bypass") == 0)
8585  bypass_param = 0;
8586  else if (strcmp(kbuf, "disc") == 0)
8587  bypass_param = 2;
8588 
8589  set_wd_exp_mode_fn(pbp_device_block, bypass_param);
8590 
8591  return count;
8592 }
8593 
8594 int
8595 get_wd_autoreset_pfs(char *page, char **start, off_t off, int count,
8596  int *eof, void *data)
8597 {
8598  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8599 
8600  int len = 0, ret = 0;
8601 
8602  ret = get_wd_autoreset_fn(pbp_device_block);
8603  if (ret >= 0)
8604  len = sprintf(page, "%d\n", ret);
8605  else
8606  len = sprintf(page, "fail\n");
8607 
8608  *eof = 1;
8609  return len;
8610 }
8611 
8612 int
8613 set_wd_autoreset_pfs(struct file *file, const char *buffer,
8614  unsigned long count, void *data)
8615 {
8616  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8617  int timeout;
8618  int ret;
8619 
8620  ret = kstrtoint_from_user(buffer, count, 10, &timeout);
8621  if (ret)
8622  return ret;
8623  set_wd_autoreset_fn(pbp_device_block, timeout);
8624 
8625  return count;
8626 }
8627 
8628 int
8629 set_tpl_pfs(struct file *file, const char *buffer,
8630  unsigned long count, void *data)
8631 {
8632 
8633  char kbuf[256];
8634  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8635 
8636  int tpl_param = 0, length = 0;
8637 
8638  if (count > (sizeof(kbuf) - 1))
8639  return -1;
8640 
8641  if (copy_from_user(&kbuf, buffer, count)) {
8642  return -1;
8643  }
8644 
8645  kbuf[count] = '\0';
8646  length = strlen(kbuf);
8647  if (kbuf[length - 1] == '\n')
8648  kbuf[--length] = '\0';
8649 
8650  if (strcmp(kbuf, "on") == 0)
8651  tpl_param = 1;
8652  else if (strcmp(kbuf, "off") == 0)
8653  tpl_param = 0;
8654 
8655  set_tpl_fn(pbp_device_block, tpl_param);
8656 
8657  return count;
8658 }
8659 
8660 #ifdef PMC_FIX_FLAG
8661 int
8662 set_wait_at_pwup_pfs(struct file *file, const char *buffer,
8663  unsigned long count, void *data)
8664 {
8665 
8666  char kbuf[256];
8667  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8668 
8669  int tpl_param = 0, length = 0;
8670 
8671  if (count > (sizeof(kbuf) - 1))
8672  return -1;
8673 
8674  if (copy_from_user(&kbuf, buffer, count)) {
8675  return -1;
8676  }
8677 
8678  kbuf[count] = '\0';
8679  length = strlen(kbuf);
8680  if (kbuf[length - 1] == '\n')
8681  kbuf[--length] = '\0';
8682 
8683  if (strcmp(kbuf, "on") == 0)
8684  tpl_param = 1;
8685  else if (strcmp(kbuf, "off") == 0)
8686  tpl_param = 0;
8687 
8688  set_bp_wait_at_pwup_fn(pbp_device_block, tpl_param);
8689 
8690  return count;
8691 }
8692 
8693 int
8694 set_hw_reset_pfs(struct file *file, const char *buffer,
8695  unsigned long count, void *data)
8696 {
8697 
8698  char kbuf[256];
8699  bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8700 
8701  int tpl_param = 0, length = 0;
8702 
8703  if (count > (sizeof(kbuf) - 1))
8704  return -1;
8705 
8706  if (copy_from_user(&kbuf, buffer, count)) {
8707  return -1;
8708  }
8709 
8710  kbuf[count] = '\0';
8711  length = strlen(kbuf);
8712  if (kbuf[length - 1] == '\n')
8713  kbuf[--length] = '\0';
8714 
8715  if (strcmp(kbuf, "on") == 0)
8716  tpl_param = 1;
8717  else if (strcmp(kbuf, "off") == 0)
8718  tpl_param = 0;
8719 
8720  set_bp_hw_reset_fn(pbp_device_block, tpl_param);
8721 
8722  return count;
8723 }
8724 
8725 #endif /*PMC_FIX_FLAG */
8726 
8727 int bypass_proc_create_dev_sd(bpctl_dev_t *pbp_device_block)
8728 {
8729  struct bypass_pfs_sd *current_pfs = &(pbp_device_block->bypass_pfs_set);
8730  static struct proc_dir_entry *procfs_dir = NULL;
8731  int ret = 0;
8732 
8733  if (!pbp_device_block->ndev)
8734  return -1;
8735  sprintf(current_pfs->dir_name, "bypass_%s",
8736  pbp_device_block->ndev->name);
8737 
8738  if (!bp_procfs_dir)
8739  return -1;
8740 
8741  /* create device proc dir */
8742  procfs_dir = proc_getdir(current_pfs->dir_name, bp_procfs_dir);
8743  if (procfs_dir == 0) {
8744  printk(KERN_DEBUG "Could not create procfs directory %s\n",
8745  current_pfs->dir_name);
8746  return -1;
8747  }
8748  current_pfs->bypass_entry = procfs_dir;
8749 
8750  if (bypass_proc_create_entry_sd(&(current_pfs->bypass_info), BYPASS_INFO_ENTRY_SD, NULL, /* write */
8751  get_bypass_info_pfs, /* read */
8752  procfs_dir, pbp_device_block))
8753  ret = -1;
8754 
8755  if (pbp_device_block->bp_caps & SW_CTL_CAP) {
8756 
8757  /* Create set param proc's */
8758  if (bypass_proc_create_entry_sd(&(current_pfs->bypass_slave), BYPASS_SLAVE_ENTRY_SD, NULL, /* write */
8759  get_bypass_slave_pfs, /* read */
8760  procfs_dir, pbp_device_block))
8761  ret = -1;
8762 
8763  if (bypass_proc_create_entry_sd(&(current_pfs->bypass_caps), BYPASS_CAPS_ENTRY_SD, NULL, /* write */
8764  get_bypass_caps_pfs, /* read */
8765  procfs_dir, pbp_device_block))
8766  ret = -1;
8767 
8768  if (bypass_proc_create_entry_sd(&(current_pfs->wd_set_caps), WD_SET_CAPS_ENTRY_SD, NULL, /* write */
8769  get_wd_set_caps_pfs, /* read */
8770  procfs_dir, pbp_device_block))
8771  ret = -1;
8772  if (bypass_proc_create_entry_sd(&(current_pfs->bypass_wd), BYPASS_WD_ENTRY_SD, set_bypass_wd_pfs, /* write */
8773  get_bypass_wd_pfs, /* read */
8774  procfs_dir, pbp_device_block))
8775  ret = -1;
8776 
8777  if (bypass_proc_create_entry_sd(&(current_pfs->wd_expire_time), WD_EXPIRE_TIME_ENTRY_SD, NULL, /* write */
8778  get_wd_expire_time_pfs, /* read */
8779  procfs_dir, pbp_device_block))
8780  ret = -1;
8781 
8782  if (bypass_proc_create_entry_sd(&(current_pfs->reset_bypass_wd), RESET_BYPASS_WD_ENTRY_SD, NULL, /* write */
8783  reset_bypass_wd_pfs, /* read */
8784  procfs_dir, pbp_device_block))
8785  ret = -1;
8786 
8787  if (bypass_proc_create_entry_sd(&(current_pfs->std_nic), STD_NIC_ENTRY_SD, set_std_nic_pfs, /* write */
8788  get_std_nic_pfs, /* read */
8789  procfs_dir, pbp_device_block))
8790  ret = -1;
8791 
8792  if (pbp_device_block->bp_caps & BP_CAP) {
8793  if (bypass_proc_create_entry_sd(&(current_pfs->bypass), BYPASS_ENTRY_SD, set_bypass_pfs, /* write */
8794  get_bypass_pfs, /* read */
8795  procfs_dir,
8796  pbp_device_block))
8797  ret = -1;
8798 
8799  if (bypass_proc_create_entry_sd(&(current_pfs->dis_bypass), DIS_BYPASS_ENTRY_SD, set_dis_bypass_pfs, /* write */
8800  get_dis_bypass_pfs, /* read */
8801  procfs_dir,
8802  pbp_device_block))
8803  ret = -1;
8804 
8805  if (bypass_proc_create_entry_sd(&(current_pfs->bypass_pwup), BYPASS_PWUP_ENTRY_SD, set_bypass_pwup_pfs, /* write */
8806  get_bypass_pwup_pfs, /* read */
8807  procfs_dir,
8808  pbp_device_block))
8809  ret = -1;
8810  if (bypass_proc_create_entry_sd(&(current_pfs->bypass_pwoff), BYPASS_PWOFF_ENTRY_SD, set_bypass_pwoff_pfs, /* write */
8811  get_bypass_pwoff_pfs, /* read */
8812  procfs_dir,
8813  pbp_device_block))
8814  ret = -1;
8815 
8816  if (bypass_proc_create_entry_sd(&(current_pfs->bypass_change), BYPASS_CHANGE_ENTRY_SD, NULL, /* write */
8817  get_bypass_change_pfs, /* read */
8818  procfs_dir,
8819  pbp_device_block))
8820  ret = -1;
8821  }
8822 
8823  if (pbp_device_block->bp_caps & TAP_CAP) {
8824 
8825  if (bypass_proc_create_entry_sd(&(current_pfs->tap), TAP_ENTRY_SD, set_tap_pfs, /* write */
8826  get_tap_pfs, /* read */
8827  procfs_dir,
8828  pbp_device_block))
8829  ret = -1;
8830 
8831  if (bypass_proc_create_entry_sd(&(current_pfs->dis_tap), DIS_TAP_ENTRY_SD, set_dis_tap_pfs, /* write */
8832  get_dis_tap_pfs, /* read */
8833  procfs_dir,
8834  pbp_device_block))
8835  ret = -1;
8836 
8837  if (bypass_proc_create_entry_sd(&(current_pfs->tap_pwup), TAP_PWUP_ENTRY_SD, set_tap_pwup_pfs, /* write */
8838  get_tap_pwup_pfs, /* read */
8839  procfs_dir,
8840  pbp_device_block))
8841  ret = -1;
8842 
8843  if (bypass_proc_create_entry_sd(&(current_pfs->tap_change), TAP_CHANGE_ENTRY_SD, NULL, /* write */
8844  get_tap_change_pfs, /* read */
8845  procfs_dir,
8846  pbp_device_block))
8847  ret = -1;
8848  }
8849  if (pbp_device_block->bp_caps & DISC_CAP) {
8850 
8851  if (bypass_proc_create_entry_sd(&(current_pfs->tap), DISC_ENTRY_SD, set_disc_pfs, /* write */
8852  get_disc_pfs, /* read */
8853  procfs_dir,
8854  pbp_device_block))
8855  ret = -1;
8856 #if 1
8857 
8858  if (bypass_proc_create_entry_sd(&(current_pfs->dis_tap), DIS_DISC_ENTRY_SD, set_dis_disc_pfs, /* write */
8859  get_dis_disc_pfs, /* read */
8860  procfs_dir,
8861  pbp_device_block))
8862  ret = -1;
8863 #endif
8864 
8865  if (bypass_proc_create_entry_sd(&(current_pfs->tap_pwup), DISC_PWUP_ENTRY_SD, set_disc_pwup_pfs, /* write */
8866  get_disc_pwup_pfs, /* read */
8867  procfs_dir,
8868  pbp_device_block))
8869  ret = -1;
8870 
8871  if (bypass_proc_create_entry_sd(&(current_pfs->tap_change), DISC_CHANGE_ENTRY_SD, NULL, /* write */
8872  get_disc_change_pfs, /* read */
8873  procfs_dir,
8874  pbp_device_block))
8875  ret = -1;
8876  }
8877 
8878  if (bypass_proc_create_entry_sd(&(current_pfs->wd_exp_mode), WD_EXP_MODE_ENTRY_SD, set_wd_exp_mode_pfs, /* write */
8879  get_wd_exp_mode_pfs, /* read */
8880  procfs_dir, pbp_device_block))
8881  ret = -1;
8882 
8883  if (bypass_proc_create_entry_sd(&(current_pfs->wd_autoreset), WD_AUTORESET_ENTRY_SD, set_wd_autoreset_pfs, /* write */
8884  get_wd_autoreset_pfs, /* read */
8885  procfs_dir, pbp_device_block))
8886  ret = -1;
8887  if (bypass_proc_create_entry_sd(&(current_pfs->tpl), TPL_ENTRY_SD, set_tpl_pfs, /* write */
8888  get_tpl_pfs, /* read */
8889  procfs_dir, pbp_device_block))
8890  ret = -1;
8891 #ifdef PMC_FIX_FLAG
8892  if (bypass_proc_create_entry_sd(&(current_pfs->tpl), WAIT_AT_PWUP_ENTRY_SD, set_wait_at_pwup_pfs, /* write */
8893  get_wait_at_pwup_pfs, /* read */
8894  procfs_dir, pbp_device_block))
8895  ret = -1;
8896  if (bypass_proc_create_entry_sd(&(current_pfs->tpl), HW_RESET_ENTRY_SD, set_hw_reset_pfs, /* write */
8897  get_hw_reset_pfs, /* read */
8898  procfs_dir, pbp_device_block))
8899  ret = -1;
8900 
8901 #endif
8902 
8903  }
8904  if (ret < 0)
8905  printk(KERN_DEBUG "Create proc entry failed\n");
8906 
8907  return ret;
8908 }
8909 
8910 int bypass_proc_remove_dev_sd(bpctl_dev_t *pbp_device_block)
8911 {
8912 
8913  struct bypass_pfs_sd *current_pfs = &pbp_device_block->bypass_pfs_set;
8914  struct proc_dir_entry *pde = current_pfs->bypass_entry, *pde_curr =
8915  NULL;
8916  char name[256];
8917 
8918  if (!pde)
8919  return 0;
8920  for (pde = pde->subdir; pde;) {
8921  strcpy(name, pde->name);
8922  pde_curr = pde;
8923  pde = pde->next;
8924  remove_proc_entry(name, current_pfs->bypass_entry);
8925  }
8926  if (!pde)
8927  remove_proc_entry(current_pfs->dir_name, bp_procfs_dir);
8928  current_pfs->bypass_entry = NULL;
8929 
8930  return 0;
8931 }
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