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mv643xx_eth.c
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1 /*
2  * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3  * Copyright (C) 2002 Matthew Dharm <[email protected]>
4  *
5  * Based on the 64360 driver from:
6  * Copyright (C) 2002 Rabeeh Khoury <[email protected]>
7  * Rabeeh Khoury <[email protected]>
8  *
9  * Copyright (C) 2003 PMC-Sierra, Inc.,
10  * written by Manish Lachwani
11  *
12  * Copyright (C) 2003 Ralf Baechle <[email protected]>
13  *
14  * Copyright (C) 2004-2006 MontaVista Software, Inc.
15  * Dale Farnsworth <[email protected]>
16  *
17  * Copyright (C) 2004 Steven J. Hill <[email protected]>
18  * <[email protected]>
19  *
20  * Copyright (C) 2007-2008 Marvell Semiconductor
21  * Lennert Buytenhek <[email protected]>
22  *
23  * This program is free software; you can redistribute it and/or
24  * modify it under the terms of the GNU General Public License
25  * as published by the Free Software Foundation; either version 2
26  * of the License, or (at your option) any later version.
27  *
28  * This program is distributed in the hope that it will be useful,
29  * but WITHOUT ANY WARRANTY; without even the implied warranty of
30  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31  * GNU General Public License for more details.
32  *
33  * You should have received a copy of the GNU General Public License
34  * along with this program; if not, write to the Free Software
35  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36  */
37 
38 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
39 
40 #include <linux/init.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/in.h>
43 #include <linux/ip.h>
44 #include <linux/tcp.h>
45 #include <linux/udp.h>
46 #include <linux/etherdevice.h>
47 #include <linux/delay.h>
48 #include <linux/ethtool.h>
49 #include <linux/platform_device.h>
50 #include <linux/module.h>
51 #include <linux/kernel.h>
52 #include <linux/spinlock.h>
53 #include <linux/workqueue.h>
54 #include <linux/phy.h>
55 #include <linux/mv643xx_eth.h>
56 #include <linux/io.h>
57 #include <linux/types.h>
58 #include <linux/inet_lro.h>
59 #include <linux/slab.h>
60 #include <linux/clk.h>
61 
62 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
63 static char mv643xx_eth_driver_version[] = "1.4";
64 
65 
66 /*
67  * Registers shared between all ports.
68  */
69 #define PHY_ADDR 0x0000
70 #define SMI_REG 0x0004
71 #define SMI_BUSY 0x10000000
72 #define SMI_READ_VALID 0x08000000
73 #define SMI_OPCODE_READ 0x04000000
74 #define SMI_OPCODE_WRITE 0x00000000
75 #define ERR_INT_CAUSE 0x0080
76 #define ERR_INT_SMI_DONE 0x00000010
77 #define ERR_INT_MASK 0x0084
78 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
79 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
80 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
81 #define WINDOW_BAR_ENABLE 0x0290
82 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
83 
84 /*
85  * Main per-port registers. These live at offset 0x0400 for
86  * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
87  */
88 #define PORT_CONFIG 0x0000
89 #define UNICAST_PROMISCUOUS_MODE 0x00000001
90 #define PORT_CONFIG_EXT 0x0004
91 #define MAC_ADDR_LOW 0x0014
92 #define MAC_ADDR_HIGH 0x0018
93 #define SDMA_CONFIG 0x001c
94 #define TX_BURST_SIZE_16_64BIT 0x01000000
95 #define TX_BURST_SIZE_4_64BIT 0x00800000
96 #define BLM_TX_NO_SWAP 0x00000020
97 #define BLM_RX_NO_SWAP 0x00000010
98 #define RX_BURST_SIZE_16_64BIT 0x00000008
99 #define RX_BURST_SIZE_4_64BIT 0x00000004
100 #define PORT_SERIAL_CONTROL 0x003c
101 #define SET_MII_SPEED_TO_100 0x01000000
102 #define SET_GMII_SPEED_TO_1000 0x00800000
103 #define SET_FULL_DUPLEX_MODE 0x00200000
104 #define MAX_RX_PACKET_9700BYTE 0x000a0000
105 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
106 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
107 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
108 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
109 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
110 #define FORCE_LINK_PASS 0x00000002
111 #define SERIAL_PORT_ENABLE 0x00000001
112 #define PORT_STATUS 0x0044
113 #define TX_FIFO_EMPTY 0x00000400
114 #define TX_IN_PROGRESS 0x00000080
115 #define PORT_SPEED_MASK 0x00000030
116 #define PORT_SPEED_1000 0x00000010
117 #define PORT_SPEED_100 0x00000020
118 #define PORT_SPEED_10 0x00000000
119 #define FLOW_CONTROL_ENABLED 0x00000008
120 #define FULL_DUPLEX 0x00000004
121 #define LINK_UP 0x00000002
122 #define TXQ_COMMAND 0x0048
123 #define TXQ_FIX_PRIO_CONF 0x004c
124 #define TX_BW_RATE 0x0050
125 #define TX_BW_MTU 0x0058
126 #define TX_BW_BURST 0x005c
127 #define INT_CAUSE 0x0060
128 #define INT_TX_END 0x07f80000
129 #define INT_TX_END_0 0x00080000
130 #define INT_RX 0x000003fc
131 #define INT_RX_0 0x00000004
132 #define INT_EXT 0x00000002
133 #define INT_CAUSE_EXT 0x0064
134 #define INT_EXT_LINK_PHY 0x00110000
135 #define INT_EXT_TX 0x000000ff
136 #define INT_MASK 0x0068
137 #define INT_MASK_EXT 0x006c
138 #define TX_FIFO_URGENT_THRESHOLD 0x0074
139 #define RX_DISCARD_FRAME_CNT 0x0084
140 #define RX_OVERRUN_FRAME_CNT 0x0088
141 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
142 #define TX_BW_RATE_MOVED 0x00e0
143 #define TX_BW_MTU_MOVED 0x00e8
144 #define TX_BW_BURST_MOVED 0x00ec
145 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
146 #define RXQ_COMMAND 0x0280
147 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
148 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
149 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
150 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
151 
152 /*
153  * Misc per-port registers.
154  */
155 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
156 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
157 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
158 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
159 
160 
161 /*
162  * SDMA configuration register default value.
163  */
164 #if defined(__BIG_ENDIAN)
165 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
166  (RX_BURST_SIZE_4_64BIT | \
167  TX_BURST_SIZE_4_64BIT)
168 #elif defined(__LITTLE_ENDIAN)
169 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
170  (RX_BURST_SIZE_4_64BIT | \
171  BLM_RX_NO_SWAP | \
172  BLM_TX_NO_SWAP | \
173  TX_BURST_SIZE_4_64BIT)
174 #else
175 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
176 #endif
177 
178 
179 /*
180  * Misc definitions.
181  */
182 #define DEFAULT_RX_QUEUE_SIZE 128
183 #define DEFAULT_TX_QUEUE_SIZE 256
184 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
185 
186 
187 /*
188  * RX/TX descriptors.
189  */
190 #if defined(__BIG_ENDIAN)
191 struct rx_desc {
192  u16 byte_cnt; /* Descriptor buffer byte count */
193  u16 buf_size; /* Buffer size */
194  u32 cmd_sts; /* Descriptor command status */
195  u32 next_desc_ptr; /* Next descriptor pointer */
196  u32 buf_ptr; /* Descriptor buffer pointer */
197 };
198 
199 struct tx_desc {
200  u16 byte_cnt; /* buffer byte count */
201  u16 l4i_chk; /* CPU provided TCP checksum */
202  u32 cmd_sts; /* Command/status field */
203  u32 next_desc_ptr; /* Pointer to next descriptor */
204  u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 };
206 #elif defined(__LITTLE_ENDIAN)
207 struct rx_desc {
208  u32 cmd_sts; /* Descriptor command status */
209  u16 buf_size; /* Buffer size */
210  u16 byte_cnt; /* Descriptor buffer byte count */
211  u32 buf_ptr; /* Descriptor buffer pointer */
212  u32 next_desc_ptr; /* Next descriptor pointer */
213 };
214 
215 struct tx_desc {
216  u32 cmd_sts; /* Command/status field */
217  u16 l4i_chk; /* CPU provided TCP checksum */
218  u16 byte_cnt; /* buffer byte count */
219  u32 buf_ptr; /* pointer to buffer for this descriptor*/
220  u32 next_desc_ptr; /* Pointer to next descriptor */
221 };
222 #else
223 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
224 #endif
225 
226 /* RX & TX descriptor command */
227 #define BUFFER_OWNED_BY_DMA 0x80000000
228 
229 /* RX & TX descriptor status */
230 #define ERROR_SUMMARY 0x00000001
231 
232 /* RX descriptor status */
233 #define LAYER_4_CHECKSUM_OK 0x40000000
234 #define RX_ENABLE_INTERRUPT 0x20000000
235 #define RX_FIRST_DESC 0x08000000
236 #define RX_LAST_DESC 0x04000000
237 #define RX_IP_HDR_OK 0x02000000
238 #define RX_PKT_IS_IPV4 0x01000000
239 #define RX_PKT_IS_ETHERNETV2 0x00800000
240 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
241 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
242 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
243 
244 /* TX descriptor command */
245 #define TX_ENABLE_INTERRUPT 0x00800000
246 #define GEN_CRC 0x00400000
247 #define TX_FIRST_DESC 0x00200000
248 #define TX_LAST_DESC 0x00100000
249 #define ZERO_PADDING 0x00080000
250 #define GEN_IP_V4_CHECKSUM 0x00040000
251 #define GEN_TCP_UDP_CHECKSUM 0x00020000
252 #define UDP_FRAME 0x00010000
253 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
254 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
255 
256 #define TX_IHL_SHIFT 11
257 
258 
259 /* global *******************************************************************/
260 struct mv643xx_eth_shared_private {
261  /*
262  * Ethernet controller base address.
263  */
264  void __iomem *base;
265 
266  /*
267  * Points at the right SMI instance to use.
268  */
269  struct mv643xx_eth_shared_private *smi;
270 
271  /*
272  * Provides access to local SMI interface.
273  */
274  struct mii_bus *smi_bus;
275 
276  /*
277  * If we have access to the error interrupt pin (which is
278  * somewhat misnamed as it not only reflects internal errors
279  * but also reflects SMI completion), use that to wait for
280  * SMI access completion instead of polling the SMI busy bit.
281  */
282  int err_interrupt;
283  wait_queue_head_t smi_busy_wait;
284 
285  /*
286  * Per-port MBUS window access register value.
287  */
288  u32 win_protect;
289 
290  /*
291  * Hardware-specific parameters.
292  */
293  int extended_rx_coal_limit;
294  int tx_bw_control;
295  int tx_csum_limit;
296 
297 };
298 
299 #define TX_BW_CONTROL_ABSENT 0
300 #define TX_BW_CONTROL_OLD_LAYOUT 1
301 #define TX_BW_CONTROL_NEW_LAYOUT 2
302 
303 static int mv643xx_eth_open(struct net_device *dev);
304 static int mv643xx_eth_stop(struct net_device *dev);
305 
306 
307 /* per-port *****************************************************************/
308 struct mib_counters {
309  u64 good_octets_received;
310  u32 bad_octets_received;
311  u32 internal_mac_transmit_err;
312  u32 good_frames_received;
313  u32 bad_frames_received;
314  u32 broadcast_frames_received;
315  u32 multicast_frames_received;
316  u32 frames_64_octets;
317  u32 frames_65_to_127_octets;
318  u32 frames_128_to_255_octets;
319  u32 frames_256_to_511_octets;
320  u32 frames_512_to_1023_octets;
321  u32 frames_1024_to_max_octets;
322  u64 good_octets_sent;
323  u32 good_frames_sent;
324  u32 excessive_collision;
325  u32 multicast_frames_sent;
326  u32 broadcast_frames_sent;
327  u32 unrec_mac_control_received;
328  u32 fc_sent;
329  u32 good_fc_received;
330  u32 bad_fc_received;
331  u32 undersize_received;
332  u32 fragments_received;
333  u32 oversize_received;
334  u32 jabber_received;
335  u32 mac_receive_error;
336  u32 bad_crc_event;
337  u32 collision;
338  u32 late_collision;
339  /* Non MIB hardware counters */
340  u32 rx_discard;
341  u32 rx_overrun;
342 };
343 
344 struct lro_counters {
345  u32 lro_aggregated;
346  u32 lro_flushed;
347  u32 lro_no_desc;
348 };
349 
350 struct rx_queue {
351  int index;
352 
353  int rx_ring_size;
354 
355  int rx_desc_count;
356  int rx_curr_desc;
357  int rx_used_desc;
358 
359  struct rx_desc *rx_desc_area;
360  dma_addr_t rx_desc_dma;
361  int rx_desc_area_size;
362  struct sk_buff **rx_skb;
363 
364  struct net_lro_mgr lro_mgr;
365  struct net_lro_desc lro_arr[8];
366 };
367 
368 struct tx_queue {
369  int index;
370 
371  int tx_ring_size;
372 
373  int tx_desc_count;
374  int tx_curr_desc;
375  int tx_used_desc;
376 
377  struct tx_desc *tx_desc_area;
378  dma_addr_t tx_desc_dma;
379  int tx_desc_area_size;
380 
381  struct sk_buff_head tx_skb;
382 
383  unsigned long tx_packets;
384  unsigned long tx_bytes;
385  unsigned long tx_dropped;
386 };
387 
388 struct mv643xx_eth_private {
389  struct mv643xx_eth_shared_private *shared;
390  void __iomem *base;
391  int port_num;
392 
393  struct net_device *dev;
394 
395  struct phy_device *phy;
396 
397  struct timer_list mib_counters_timer;
398  spinlock_t mib_counters_lock;
399  struct mib_counters mib_counters;
400 
401  struct lro_counters lro_counters;
402 
403  struct work_struct tx_timeout_task;
404 
405  struct napi_struct napi;
406  u32 int_mask;
407  u8 oom;
408  u8 work_link;
409  u8 work_tx;
410  u8 work_tx_end;
411  u8 work_rx;
412  u8 work_rx_refill;
413 
414  int skb_size;
415 
416  /*
417  * RX state.
418  */
419  int rx_ring_size;
420  unsigned long rx_desc_sram_addr;
421  int rx_desc_sram_size;
422  int rxq_count;
423  struct timer_list rx_oom;
424  struct rx_queue rxq[8];
425 
426  /*
427  * TX state.
428  */
429  int tx_ring_size;
430  unsigned long tx_desc_sram_addr;
431  int tx_desc_sram_size;
432  int txq_count;
433  struct tx_queue txq[8];
434 
435  /*
436  * Hardware-specific parameters.
437  */
438 #if defined(CONFIG_HAVE_CLK)
439  struct clk *clk;
440 #endif
441  unsigned int t_clk;
442 };
443 
444 
445 /* port register accessors **************************************************/
446 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
447 {
448  return readl(mp->shared->base + offset);
449 }
450 
451 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
452 {
453  return readl(mp->base + offset);
454 }
455 
456 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
457 {
458  writel(data, mp->shared->base + offset);
459 }
460 
461 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
462 {
463  writel(data, mp->base + offset);
464 }
465 
466 
467 /* rxq/txq helper functions *************************************************/
468 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
469 {
470  return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
471 }
472 
473 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
474 {
475  return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
476 }
477 
478 static void rxq_enable(struct rx_queue *rxq)
479 {
480  struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
481  wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
482 }
483 
484 static void rxq_disable(struct rx_queue *rxq)
485 {
486  struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
487  u8 mask = 1 << rxq->index;
488 
489  wrlp(mp, RXQ_COMMAND, mask << 8);
490  while (rdlp(mp, RXQ_COMMAND) & mask)
491  udelay(10);
492 }
493 
494 static void txq_reset_hw_ptr(struct tx_queue *txq)
495 {
496  struct mv643xx_eth_private *mp = txq_to_mp(txq);
497  u32 addr;
498 
499  addr = (u32)txq->tx_desc_dma;
500  addr += txq->tx_curr_desc * sizeof(struct tx_desc);
501  wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
502 }
503 
504 static void txq_enable(struct tx_queue *txq)
505 {
506  struct mv643xx_eth_private *mp = txq_to_mp(txq);
507  wrlp(mp, TXQ_COMMAND, 1 << txq->index);
508 }
509 
510 static void txq_disable(struct tx_queue *txq)
511 {
512  struct mv643xx_eth_private *mp = txq_to_mp(txq);
513  u8 mask = 1 << txq->index;
514 
515  wrlp(mp, TXQ_COMMAND, mask << 8);
516  while (rdlp(mp, TXQ_COMMAND) & mask)
517  udelay(10);
518 }
519 
520 static void txq_maybe_wake(struct tx_queue *txq)
521 {
522  struct mv643xx_eth_private *mp = txq_to_mp(txq);
523  struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
524 
525  if (netif_tx_queue_stopped(nq)) {
526  __netif_tx_lock(nq, smp_processor_id());
527  if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
528  netif_tx_wake_queue(nq);
529  __netif_tx_unlock(nq);
530  }
531 }
532 
533 
534 /* rx napi ******************************************************************/
535 static int
536 mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
537  u64 *hdr_flags, void *priv)
538 {
539  unsigned long cmd_sts = (unsigned long)priv;
540 
541  /*
542  * Make sure that this packet is Ethernet II, is not VLAN
543  * tagged, is IPv4, has a valid IP header, and is TCP.
544  */
545  if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
546  RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
547  RX_PKT_IS_VLAN_TAGGED)) !=
548  (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
549  RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
550  return -1;
551 
552  skb_reset_network_header(skb);
553  skb_set_transport_header(skb, ip_hdrlen(skb));
554  *iphdr = ip_hdr(skb);
555  *tcph = tcp_hdr(skb);
556  *hdr_flags = LRO_IPV4 | LRO_TCP;
557 
558  return 0;
559 }
560 
561 static int rxq_process(struct rx_queue *rxq, int budget)
562 {
563  struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
564  struct net_device_stats *stats = &mp->dev->stats;
565  int lro_flush_needed;
566  int rx;
567 
568  lro_flush_needed = 0;
569  rx = 0;
570  while (rx < budget && rxq->rx_desc_count) {
571  struct rx_desc *rx_desc;
572  unsigned int cmd_sts;
573  struct sk_buff *skb;
574  u16 byte_cnt;
575 
576  rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
577 
578  cmd_sts = rx_desc->cmd_sts;
579  if (cmd_sts & BUFFER_OWNED_BY_DMA)
580  break;
581  rmb();
582 
583  skb = rxq->rx_skb[rxq->rx_curr_desc];
584  rxq->rx_skb[rxq->rx_curr_desc] = NULL;
585 
586  rxq->rx_curr_desc++;
587  if (rxq->rx_curr_desc == rxq->rx_ring_size)
588  rxq->rx_curr_desc = 0;
589 
590  dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
591  rx_desc->buf_size, DMA_FROM_DEVICE);
592  rxq->rx_desc_count--;
593  rx++;
594 
595  mp->work_rx_refill |= 1 << rxq->index;
596 
597  byte_cnt = rx_desc->byte_cnt;
598 
599  /*
600  * Update statistics.
601  *
602  * Note that the descriptor byte count includes 2 dummy
603  * bytes automatically inserted by the hardware at the
604  * start of the packet (which we don't count), and a 4
605  * byte CRC at the end of the packet (which we do count).
606  */
607  stats->rx_packets++;
608  stats->rx_bytes += byte_cnt - 2;
609 
610  /*
611  * In case we received a packet without first / last bits
612  * on, or the error summary bit is set, the packet needs
613  * to be dropped.
614  */
615  if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
616  != (RX_FIRST_DESC | RX_LAST_DESC))
617  goto err;
618 
619  /*
620  * The -4 is for the CRC in the trailer of the
621  * received packet
622  */
623  skb_put(skb, byte_cnt - 2 - 4);
624 
625  if (cmd_sts & LAYER_4_CHECKSUM_OK)
626  skb->ip_summed = CHECKSUM_UNNECESSARY;
627  skb->protocol = eth_type_trans(skb, mp->dev);
628 
629  if (skb->dev->features & NETIF_F_LRO &&
630  skb->ip_summed == CHECKSUM_UNNECESSARY) {
631  lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
632  lro_flush_needed = 1;
633  } else
634  netif_receive_skb(skb);
635 
636  continue;
637 
638 err:
639  stats->rx_dropped++;
640 
641  if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
642  (RX_FIRST_DESC | RX_LAST_DESC)) {
643  if (net_ratelimit())
644  netdev_err(mp->dev,
645  "received packet spanning multiple descriptors\n");
646  }
647 
648  if (cmd_sts & ERROR_SUMMARY)
649  stats->rx_errors++;
650 
651  dev_kfree_skb(skb);
652  }
653 
654  if (lro_flush_needed)
655  lro_flush_all(&rxq->lro_mgr);
656 
657  if (rx < budget)
658  mp->work_rx &= ~(1 << rxq->index);
659 
660  return rx;
661 }
662 
663 static int rxq_refill(struct rx_queue *rxq, int budget)
664 {
665  struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
666  int refilled;
667 
668  refilled = 0;
669  while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
670  struct sk_buff *skb;
671  int rx;
672  struct rx_desc *rx_desc;
673  int size;
674 
675  skb = netdev_alloc_skb(mp->dev, mp->skb_size);
676 
677  if (skb == NULL) {
678  mp->oom = 1;
679  goto oom;
680  }
681 
682  if (SKB_DMA_REALIGN)
683  skb_reserve(skb, SKB_DMA_REALIGN);
684 
685  refilled++;
686  rxq->rx_desc_count++;
687 
688  rx = rxq->rx_used_desc++;
689  if (rxq->rx_used_desc == rxq->rx_ring_size)
690  rxq->rx_used_desc = 0;
691 
692  rx_desc = rxq->rx_desc_area + rx;
693 
694  size = skb->end - skb->data;
695  rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
696  skb->data, size,
697  DMA_FROM_DEVICE);
698  rx_desc->buf_size = size;
699  rxq->rx_skb[rx] = skb;
700  wmb();
701  rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
702  wmb();
703 
704  /*
705  * The hardware automatically prepends 2 bytes of
706  * dummy data to each received packet, so that the
707  * IP header ends up 16-byte aligned.
708  */
709  skb_reserve(skb, 2);
710  }
711 
712  if (refilled < budget)
713  mp->work_rx_refill &= ~(1 << rxq->index);
714 
715 oom:
716  return refilled;
717 }
718 
719 
720 /* tx ***********************************************************************/
721 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
722 {
723  int frag;
724 
725  for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
726  const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
727 
728  if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
729  return 1;
730  }
731 
732  return 0;
733 }
734 
735 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
736 {
737  struct mv643xx_eth_private *mp = txq_to_mp(txq);
738  int nr_frags = skb_shinfo(skb)->nr_frags;
739  int frag;
740 
741  for (frag = 0; frag < nr_frags; frag++) {
742  skb_frag_t *this_frag;
743  int tx_index;
744  struct tx_desc *desc;
745 
746  this_frag = &skb_shinfo(skb)->frags[frag];
747  tx_index = txq->tx_curr_desc++;
748  if (txq->tx_curr_desc == txq->tx_ring_size)
749  txq->tx_curr_desc = 0;
750  desc = &txq->tx_desc_area[tx_index];
751 
752  /*
753  * The last fragment will generate an interrupt
754  * which will free the skb on TX completion.
755  */
756  if (frag == nr_frags - 1) {
757  desc->cmd_sts = BUFFER_OWNED_BY_DMA |
758  ZERO_PADDING | TX_LAST_DESC |
759  TX_ENABLE_INTERRUPT;
760  } else {
761  desc->cmd_sts = BUFFER_OWNED_BY_DMA;
762  }
763 
764  desc->l4i_chk = 0;
765  desc->byte_cnt = skb_frag_size(this_frag);
766  desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
767  this_frag, 0,
768  skb_frag_size(this_frag),
769  DMA_TO_DEVICE);
770  }
771 }
772 
773 static inline __be16 sum16_as_be(__sum16 sum)
774 {
775  return (__force __be16)sum;
776 }
777 
778 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
779 {
780  struct mv643xx_eth_private *mp = txq_to_mp(txq);
781  int nr_frags = skb_shinfo(skb)->nr_frags;
782  int tx_index;
783  struct tx_desc *desc;
784  u32 cmd_sts;
785  u16 l4i_chk;
786  int length;
787 
788  cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
789  l4i_chk = 0;
790 
791  if (skb->ip_summed == CHECKSUM_PARTIAL) {
792  int hdr_len;
793  int tag_bytes;
794 
795  BUG_ON(skb->protocol != htons(ETH_P_IP) &&
796  skb->protocol != htons(ETH_P_8021Q));
797 
798  hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
799  tag_bytes = hdr_len - ETH_HLEN;
800  if (skb->len - hdr_len > mp->shared->tx_csum_limit ||
801  unlikely(tag_bytes & ~12)) {
802  if (skb_checksum_help(skb) == 0)
803  goto no_csum;
804  kfree_skb(skb);
805  return 1;
806  }
807 
808  if (tag_bytes & 4)
809  cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
810  if (tag_bytes & 8)
811  cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
812 
813  cmd_sts |= GEN_TCP_UDP_CHECKSUM |
814  GEN_IP_V4_CHECKSUM |
815  ip_hdr(skb)->ihl << TX_IHL_SHIFT;
816 
817  switch (ip_hdr(skb)->protocol) {
818  case IPPROTO_UDP:
819  cmd_sts |= UDP_FRAME;
820  l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
821  break;
822  case IPPROTO_TCP:
823  l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
824  break;
825  default:
826  BUG();
827  }
828  } else {
829 no_csum:
830  /* Errata BTS #50, IHL must be 5 if no HW checksum */
831  cmd_sts |= 5 << TX_IHL_SHIFT;
832  }
833 
834  tx_index = txq->tx_curr_desc++;
835  if (txq->tx_curr_desc == txq->tx_ring_size)
836  txq->tx_curr_desc = 0;
837  desc = &txq->tx_desc_area[tx_index];
838 
839  if (nr_frags) {
840  txq_submit_frag_skb(txq, skb);
841  length = skb_headlen(skb);
842  } else {
843  cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
844  length = skb->len;
845  }
846 
847  desc->l4i_chk = l4i_chk;
848  desc->byte_cnt = length;
849  desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
850  length, DMA_TO_DEVICE);
851 
852  __skb_queue_tail(&txq->tx_skb, skb);
853 
854  skb_tx_timestamp(skb);
855 
856  /* ensure all other descriptors are written before first cmd_sts */
857  wmb();
858  desc->cmd_sts = cmd_sts;
859 
860  /* clear TX_END status */
861  mp->work_tx_end &= ~(1 << txq->index);
862 
863  /* ensure all descriptors are written before poking hardware */
864  wmb();
865  txq_enable(txq);
866 
867  txq->tx_desc_count += nr_frags + 1;
868 
869  return 0;
870 }
871 
872 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
873 {
874  struct mv643xx_eth_private *mp = netdev_priv(dev);
875  int length, queue;
876  struct tx_queue *txq;
877  struct netdev_queue *nq;
878 
879  queue = skb_get_queue_mapping(skb);
880  txq = mp->txq + queue;
881  nq = netdev_get_tx_queue(dev, queue);
882 
883  if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
884  txq->tx_dropped++;
885  netdev_printk(KERN_DEBUG, dev,
886  "failed to linearize skb with tiny unaligned fragment\n");
887  return NETDEV_TX_BUSY;
888  }
889 
890  if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
891  if (net_ratelimit())
892  netdev_err(dev, "tx queue full?!\n");
893  kfree_skb(skb);
894  return NETDEV_TX_OK;
895  }
896 
897  length = skb->len;
898 
899  if (!txq_submit_skb(txq, skb)) {
900  int entries_left;
901 
902  txq->tx_bytes += length;
903  txq->tx_packets++;
904 
905  entries_left = txq->tx_ring_size - txq->tx_desc_count;
906  if (entries_left < MAX_SKB_FRAGS + 1)
907  netif_tx_stop_queue(nq);
908  }
909 
910  return NETDEV_TX_OK;
911 }
912 
913 
914 /* tx napi ******************************************************************/
915 static void txq_kick(struct tx_queue *txq)
916 {
917  struct mv643xx_eth_private *mp = txq_to_mp(txq);
918  struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
919  u32 hw_desc_ptr;
920  u32 expected_ptr;
921 
922  __netif_tx_lock(nq, smp_processor_id());
923 
924  if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
925  goto out;
926 
927  hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
928  expected_ptr = (u32)txq->tx_desc_dma +
929  txq->tx_curr_desc * sizeof(struct tx_desc);
930 
931  if (hw_desc_ptr != expected_ptr)
932  txq_enable(txq);
933 
934 out:
935  __netif_tx_unlock(nq);
936 
937  mp->work_tx_end &= ~(1 << txq->index);
938 }
939 
940 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
941 {
942  struct mv643xx_eth_private *mp = txq_to_mp(txq);
943  struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
944  int reclaimed;
945 
946  __netif_tx_lock(nq, smp_processor_id());
947 
948  reclaimed = 0;
949  while (reclaimed < budget && txq->tx_desc_count > 0) {
950  int tx_index;
951  struct tx_desc *desc;
952  u32 cmd_sts;
953  struct sk_buff *skb;
954 
955  tx_index = txq->tx_used_desc;
956  desc = &txq->tx_desc_area[tx_index];
957  cmd_sts = desc->cmd_sts;
958 
959  if (cmd_sts & BUFFER_OWNED_BY_DMA) {
960  if (!force)
961  break;
962  desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
963  }
964 
965  txq->tx_used_desc = tx_index + 1;
966  if (txq->tx_used_desc == txq->tx_ring_size)
967  txq->tx_used_desc = 0;
968 
969  reclaimed++;
970  txq->tx_desc_count--;
971 
972  skb = NULL;
973  if (cmd_sts & TX_LAST_DESC)
974  skb = __skb_dequeue(&txq->tx_skb);
975 
976  if (cmd_sts & ERROR_SUMMARY) {
977  netdev_info(mp->dev, "tx error\n");
978  mp->dev->stats.tx_errors++;
979  }
980 
981  if (cmd_sts & TX_FIRST_DESC) {
982  dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
983  desc->byte_cnt, DMA_TO_DEVICE);
984  } else {
985  dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
986  desc->byte_cnt, DMA_TO_DEVICE);
987  }
988 
989  dev_kfree_skb(skb);
990  }
991 
992  __netif_tx_unlock(nq);
993 
994  if (reclaimed < budget)
995  mp->work_tx &= ~(1 << txq->index);
996 
997  return reclaimed;
998 }
999 
1000 
1001 /* tx rate control **********************************************************/
1002 /*
1003  * Set total maximum TX rate (shared by all TX queues for this port)
1004  * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1005  */
1006 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1007 {
1008  int token_rate;
1009  int mtu;
1010  int bucket_size;
1011 
1012  token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1013  if (token_rate > 1023)
1014  token_rate = 1023;
1015 
1016  mtu = (mp->dev->mtu + 255) >> 8;
1017  if (mtu > 63)
1018  mtu = 63;
1019 
1020  bucket_size = (burst + 255) >> 8;
1021  if (bucket_size > 65535)
1022  bucket_size = 65535;
1023 
1024  switch (mp->shared->tx_bw_control) {
1025  case TX_BW_CONTROL_OLD_LAYOUT:
1026  wrlp(mp, TX_BW_RATE, token_rate);
1027  wrlp(mp, TX_BW_MTU, mtu);
1028  wrlp(mp, TX_BW_BURST, bucket_size);
1029  break;
1030  case TX_BW_CONTROL_NEW_LAYOUT:
1031  wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1032  wrlp(mp, TX_BW_MTU_MOVED, mtu);
1033  wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1034  break;
1035  }
1036 }
1037 
1038 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1039 {
1040  struct mv643xx_eth_private *mp = txq_to_mp(txq);
1041  int token_rate;
1042  int bucket_size;
1043 
1044  token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1045  if (token_rate > 1023)
1046  token_rate = 1023;
1047 
1048  bucket_size = (burst + 255) >> 8;
1049  if (bucket_size > 65535)
1050  bucket_size = 65535;
1051 
1052  wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1053  wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1054 }
1055 
1056 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1057 {
1058  struct mv643xx_eth_private *mp = txq_to_mp(txq);
1059  int off;
1060  u32 val;
1061 
1062  /*
1063  * Turn on fixed priority mode.
1064  */
1065  off = 0;
1066  switch (mp->shared->tx_bw_control) {
1067  case TX_BW_CONTROL_OLD_LAYOUT:
1068  off = TXQ_FIX_PRIO_CONF;
1069  break;
1070  case TX_BW_CONTROL_NEW_LAYOUT:
1071  off = TXQ_FIX_PRIO_CONF_MOVED;
1072  break;
1073  }
1074 
1075  if (off) {
1076  val = rdlp(mp, off);
1077  val |= 1 << txq->index;
1078  wrlp(mp, off, val);
1079  }
1080 }
1081 
1082 
1083 /* mii management interface *************************************************/
1084 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1085 {
1086  struct mv643xx_eth_shared_private *msp = dev_id;
1087 
1088  if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1089  writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1090  wake_up(&msp->smi_busy_wait);
1091  return IRQ_HANDLED;
1092  }
1093 
1094  return IRQ_NONE;
1095 }
1096 
1097 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1098 {
1099  return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1100 }
1101 
1102 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1103 {
1104  if (msp->err_interrupt == NO_IRQ) {
1105  int i;
1106 
1107  for (i = 0; !smi_is_done(msp); i++) {
1108  if (i == 10)
1109  return -ETIMEDOUT;
1110  msleep(10);
1111  }
1112 
1113  return 0;
1114  }
1115 
1116  if (!smi_is_done(msp)) {
1117  wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1118  msecs_to_jiffies(100));
1119  if (!smi_is_done(msp))
1120  return -ETIMEDOUT;
1121  }
1122 
1123  return 0;
1124 }
1125 
1126 static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
1127 {
1128  struct mv643xx_eth_shared_private *msp = bus->priv;
1129  void __iomem *smi_reg = msp->base + SMI_REG;
1130  int ret;
1131 
1132  if (smi_wait_ready(msp)) {
1133  pr_warn("SMI bus busy timeout\n");
1134  return -ETIMEDOUT;
1135  }
1136 
1137  writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1138 
1139  if (smi_wait_ready(msp)) {
1140  pr_warn("SMI bus busy timeout\n");
1141  return -ETIMEDOUT;
1142  }
1143 
1144  ret = readl(smi_reg);
1145  if (!(ret & SMI_READ_VALID)) {
1146  pr_warn("SMI bus read not valid\n");
1147  return -ENODEV;
1148  }
1149 
1150  return ret & 0xffff;
1151 }
1152 
1153 static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1154 {
1155  struct mv643xx_eth_shared_private *msp = bus->priv;
1156  void __iomem *smi_reg = msp->base + SMI_REG;
1157 
1158  if (smi_wait_ready(msp)) {
1159  pr_warn("SMI bus busy timeout\n");
1160  return -ETIMEDOUT;
1161  }
1162 
1163  writel(SMI_OPCODE_WRITE | (reg << 21) |
1164  (addr << 16) | (val & 0xffff), smi_reg);
1165 
1166  if (smi_wait_ready(msp)) {
1167  pr_warn("SMI bus busy timeout\n");
1168  return -ETIMEDOUT;
1169  }
1170 
1171  return 0;
1172 }
1173 
1174 
1175 /* statistics ***************************************************************/
1176 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1177 {
1178  struct mv643xx_eth_private *mp = netdev_priv(dev);
1179  struct net_device_stats *stats = &dev->stats;
1180  unsigned long tx_packets = 0;
1181  unsigned long tx_bytes = 0;
1182  unsigned long tx_dropped = 0;
1183  int i;
1184 
1185  for (i = 0; i < mp->txq_count; i++) {
1186  struct tx_queue *txq = mp->txq + i;
1187 
1188  tx_packets += txq->tx_packets;
1189  tx_bytes += txq->tx_bytes;
1190  tx_dropped += txq->tx_dropped;
1191  }
1192 
1193  stats->tx_packets = tx_packets;
1194  stats->tx_bytes = tx_bytes;
1195  stats->tx_dropped = tx_dropped;
1196 
1197  return stats;
1198 }
1199 
1200 static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
1201 {
1202  u32 lro_aggregated = 0;
1203  u32 lro_flushed = 0;
1204  u32 lro_no_desc = 0;
1205  int i;
1206 
1207  for (i = 0; i < mp->rxq_count; i++) {
1208  struct rx_queue *rxq = mp->rxq + i;
1209 
1210  lro_aggregated += rxq->lro_mgr.stats.aggregated;
1211  lro_flushed += rxq->lro_mgr.stats.flushed;
1212  lro_no_desc += rxq->lro_mgr.stats.no_desc;
1213  }
1214 
1215  mp->lro_counters.lro_aggregated = lro_aggregated;
1216  mp->lro_counters.lro_flushed = lro_flushed;
1217  mp->lro_counters.lro_no_desc = lro_no_desc;
1218 }
1219 
1220 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1221 {
1222  return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1223 }
1224 
1225 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1226 {
1227  int i;
1228 
1229  for (i = 0; i < 0x80; i += 4)
1230  mib_read(mp, i);
1231 
1232  /* Clear non MIB hw counters also */
1233  rdlp(mp, RX_DISCARD_FRAME_CNT);
1234  rdlp(mp, RX_OVERRUN_FRAME_CNT);
1235 }
1236 
1237 static void mib_counters_update(struct mv643xx_eth_private *mp)
1238 {
1239  struct mib_counters *p = &mp->mib_counters;
1240 
1241  spin_lock_bh(&mp->mib_counters_lock);
1242  p->good_octets_received += mib_read(mp, 0x00);
1243  p->bad_octets_received += mib_read(mp, 0x08);
1244  p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1245  p->good_frames_received += mib_read(mp, 0x10);
1246  p->bad_frames_received += mib_read(mp, 0x14);
1247  p->broadcast_frames_received += mib_read(mp, 0x18);
1248  p->multicast_frames_received += mib_read(mp, 0x1c);
1249  p->frames_64_octets += mib_read(mp, 0x20);
1250  p->frames_65_to_127_octets += mib_read(mp, 0x24);
1251  p->frames_128_to_255_octets += mib_read(mp, 0x28);
1252  p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1253  p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1254  p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1255  p->good_octets_sent += mib_read(mp, 0x38);
1256  p->good_frames_sent += mib_read(mp, 0x40);
1257  p->excessive_collision += mib_read(mp, 0x44);
1258  p->multicast_frames_sent += mib_read(mp, 0x48);
1259  p->broadcast_frames_sent += mib_read(mp, 0x4c);
1260  p->unrec_mac_control_received += mib_read(mp, 0x50);
1261  p->fc_sent += mib_read(mp, 0x54);
1262  p->good_fc_received += mib_read(mp, 0x58);
1263  p->bad_fc_received += mib_read(mp, 0x5c);
1264  p->undersize_received += mib_read(mp, 0x60);
1265  p->fragments_received += mib_read(mp, 0x64);
1266  p->oversize_received += mib_read(mp, 0x68);
1267  p->jabber_received += mib_read(mp, 0x6c);
1268  p->mac_receive_error += mib_read(mp, 0x70);
1269  p->bad_crc_event += mib_read(mp, 0x74);
1270  p->collision += mib_read(mp, 0x78);
1271  p->late_collision += mib_read(mp, 0x7c);
1272  /* Non MIB hardware counters */
1273  p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1274  p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1275  spin_unlock_bh(&mp->mib_counters_lock);
1276 
1277  mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1278 }
1279 
1280 static void mib_counters_timer_wrapper(unsigned long _mp)
1281 {
1282  struct mv643xx_eth_private *mp = (void *)_mp;
1283 
1284  mib_counters_update(mp);
1285 }
1286 
1287 
1288 /* interrupt coalescing *****************************************************/
1289 /*
1290  * Hardware coalescing parameters are set in units of 64 t_clk
1291  * cycles. I.e.:
1292  *
1293  * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1294  *
1295  * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1296  *
1297  * In the ->set*() methods, we round the computed register value
1298  * to the nearest integer.
1299  */
1300 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1301 {
1302  u32 val = rdlp(mp, SDMA_CONFIG);
1303  u64 temp;
1304 
1305  if (mp->shared->extended_rx_coal_limit)
1306  temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1307  else
1308  temp = (val & 0x003fff00) >> 8;
1309 
1310  temp *= 64000000;
1311  do_div(temp, mp->t_clk);
1312 
1313  return (unsigned int)temp;
1314 }
1315 
1316 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1317 {
1318  u64 temp;
1319  u32 val;
1320 
1321  temp = (u64)usec * mp->t_clk;
1322  temp += 31999999;
1323  do_div(temp, 64000000);
1324 
1325  val = rdlp(mp, SDMA_CONFIG);
1326  if (mp->shared->extended_rx_coal_limit) {
1327  if (temp > 0xffff)
1328  temp = 0xffff;
1329  val &= ~0x023fff80;
1330  val |= (temp & 0x8000) << 10;
1331  val |= (temp & 0x7fff) << 7;
1332  } else {
1333  if (temp > 0x3fff)
1334  temp = 0x3fff;
1335  val &= ~0x003fff00;
1336  val |= (temp & 0x3fff) << 8;
1337  }
1338  wrlp(mp, SDMA_CONFIG, val);
1339 }
1340 
1341 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1342 {
1343  u64 temp;
1344 
1345  temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1346  temp *= 64000000;
1347  do_div(temp, mp->t_clk);
1348 
1349  return (unsigned int)temp;
1350 }
1351 
1352 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1353 {
1354  u64 temp;
1355 
1356  temp = (u64)usec * mp->t_clk;
1357  temp += 31999999;
1358  do_div(temp, 64000000);
1359 
1360  if (temp > 0x3fff)
1361  temp = 0x3fff;
1362 
1363  wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1364 }
1365 
1366 
1367 /* ethtool ******************************************************************/
1368 struct mv643xx_eth_stats {
1369  char stat_string[ETH_GSTRING_LEN];
1370  int sizeof_stat;
1371  int netdev_off;
1372  int mp_off;
1373 };
1374 
1375 #define SSTAT(m) \
1376  { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1377  offsetof(struct net_device, stats.m), -1 }
1378 
1379 #define MIBSTAT(m) \
1380  { #m, FIELD_SIZEOF(struct mib_counters, m), \
1381  -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1382 
1383 #define LROSTAT(m) \
1384  { #m, FIELD_SIZEOF(struct lro_counters, m), \
1385  -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1386 
1387 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1388  SSTAT(rx_packets),
1389  SSTAT(tx_packets),
1390  SSTAT(rx_bytes),
1391  SSTAT(tx_bytes),
1392  SSTAT(rx_errors),
1393  SSTAT(tx_errors),
1394  SSTAT(rx_dropped),
1395  SSTAT(tx_dropped),
1396  MIBSTAT(good_octets_received),
1397  MIBSTAT(bad_octets_received),
1398  MIBSTAT(internal_mac_transmit_err),
1399  MIBSTAT(good_frames_received),
1400  MIBSTAT(bad_frames_received),
1401  MIBSTAT(broadcast_frames_received),
1402  MIBSTAT(multicast_frames_received),
1403  MIBSTAT(frames_64_octets),
1404  MIBSTAT(frames_65_to_127_octets),
1405  MIBSTAT(frames_128_to_255_octets),
1406  MIBSTAT(frames_256_to_511_octets),
1407  MIBSTAT(frames_512_to_1023_octets),
1408  MIBSTAT(frames_1024_to_max_octets),
1409  MIBSTAT(good_octets_sent),
1410  MIBSTAT(good_frames_sent),
1411  MIBSTAT(excessive_collision),
1412  MIBSTAT(multicast_frames_sent),
1413  MIBSTAT(broadcast_frames_sent),
1414  MIBSTAT(unrec_mac_control_received),
1415  MIBSTAT(fc_sent),
1416  MIBSTAT(good_fc_received),
1417  MIBSTAT(bad_fc_received),
1418  MIBSTAT(undersize_received),
1419  MIBSTAT(fragments_received),
1420  MIBSTAT(oversize_received),
1421  MIBSTAT(jabber_received),
1422  MIBSTAT(mac_receive_error),
1423  MIBSTAT(bad_crc_event),
1424  MIBSTAT(collision),
1425  MIBSTAT(late_collision),
1426  MIBSTAT(rx_discard),
1427  MIBSTAT(rx_overrun),
1428  LROSTAT(lro_aggregated),
1429  LROSTAT(lro_flushed),
1430  LROSTAT(lro_no_desc),
1431 };
1432 
1433 static int
1434 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1435  struct ethtool_cmd *cmd)
1436 {
1437  int err;
1438 
1439  err = phy_read_status(mp->phy);
1440  if (err == 0)
1441  err = phy_ethtool_gset(mp->phy, cmd);
1442 
1443  /*
1444  * The MAC does not support 1000baseT_Half.
1445  */
1446  cmd->supported &= ~SUPPORTED_1000baseT_Half;
1447  cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1448 
1449  return err;
1450 }
1451 
1452 static int
1453 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1454  struct ethtool_cmd *cmd)
1455 {
1456  u32 port_status;
1457 
1458  port_status = rdlp(mp, PORT_STATUS);
1459 
1460  cmd->supported = SUPPORTED_MII;
1461  cmd->advertising = ADVERTISED_MII;
1462  switch (port_status & PORT_SPEED_MASK) {
1463  case PORT_SPEED_10:
1464  ethtool_cmd_speed_set(cmd, SPEED_10);
1465  break;
1466  case PORT_SPEED_100:
1467  ethtool_cmd_speed_set(cmd, SPEED_100);
1468  break;
1469  case PORT_SPEED_1000:
1470  ethtool_cmd_speed_set(cmd, SPEED_1000);
1471  break;
1472  default:
1473  cmd->speed = -1;
1474  break;
1475  }
1476  cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1477  cmd->port = PORT_MII;
1478  cmd->phy_address = 0;
1479  cmd->transceiver = XCVR_INTERNAL;
1480  cmd->autoneg = AUTONEG_DISABLE;
1481  cmd->maxtxpkt = 1;
1482  cmd->maxrxpkt = 1;
1483 
1484  return 0;
1485 }
1486 
1487 static int
1488 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1489 {
1490  struct mv643xx_eth_private *mp = netdev_priv(dev);
1491 
1492  if (mp->phy != NULL)
1493  return mv643xx_eth_get_settings_phy(mp, cmd);
1494  else
1495  return mv643xx_eth_get_settings_phyless(mp, cmd);
1496 }
1497 
1498 static int
1499 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1500 {
1501  struct mv643xx_eth_private *mp = netdev_priv(dev);
1502 
1503  if (mp->phy == NULL)
1504  return -EINVAL;
1505 
1506  /*
1507  * The MAC does not support 1000baseT_Half.
1508  */
1509  cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1510 
1511  return phy_ethtool_sset(mp->phy, cmd);
1512 }
1513 
1514 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1515  struct ethtool_drvinfo *drvinfo)
1516 {
1517  strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1518  sizeof(drvinfo->driver));
1519  strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1520  sizeof(drvinfo->version));
1521  strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1522  strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1523  drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1524 }
1525 
1526 static int mv643xx_eth_nway_reset(struct net_device *dev)
1527 {
1528  struct mv643xx_eth_private *mp = netdev_priv(dev);
1529 
1530  if (mp->phy == NULL)
1531  return -EINVAL;
1532 
1533  return genphy_restart_aneg(mp->phy);
1534 }
1535 
1536 static int
1537 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1538 {
1539  struct mv643xx_eth_private *mp = netdev_priv(dev);
1540 
1541  ec->rx_coalesce_usecs = get_rx_coal(mp);
1542  ec->tx_coalesce_usecs = get_tx_coal(mp);
1543 
1544  return 0;
1545 }
1546 
1547 static int
1548 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1549 {
1550  struct mv643xx_eth_private *mp = netdev_priv(dev);
1551 
1552  set_rx_coal(mp, ec->rx_coalesce_usecs);
1553  set_tx_coal(mp, ec->tx_coalesce_usecs);
1554 
1555  return 0;
1556 }
1557 
1558 static void
1559 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1560 {
1561  struct mv643xx_eth_private *mp = netdev_priv(dev);
1562 
1563  er->rx_max_pending = 4096;
1564  er->tx_max_pending = 4096;
1565 
1566  er->rx_pending = mp->rx_ring_size;
1567  er->tx_pending = mp->tx_ring_size;
1568 }
1569 
1570 static int
1571 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1572 {
1573  struct mv643xx_eth_private *mp = netdev_priv(dev);
1574 
1575  if (er->rx_mini_pending || er->rx_jumbo_pending)
1576  return -EINVAL;
1577 
1578  mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1579  mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1580 
1581  if (netif_running(dev)) {
1582  mv643xx_eth_stop(dev);
1583  if (mv643xx_eth_open(dev)) {
1584  netdev_err(dev,
1585  "fatal error on re-opening device after ring param change\n");
1586  return -ENOMEM;
1587  }
1588  }
1589 
1590  return 0;
1591 }
1592 
1593 
1594 static int
1595 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1596 {
1597  struct mv643xx_eth_private *mp = netdev_priv(dev);
1598  bool rx_csum = features & NETIF_F_RXCSUM;
1599 
1600  wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1601 
1602  return 0;
1603 }
1604 
1605 static void mv643xx_eth_get_strings(struct net_device *dev,
1606  uint32_t stringset, uint8_t *data)
1607 {
1608  int i;
1609 
1610  if (stringset == ETH_SS_STATS) {
1611  for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1612  memcpy(data + i * ETH_GSTRING_LEN,
1613  mv643xx_eth_stats[i].stat_string,
1614  ETH_GSTRING_LEN);
1615  }
1616  }
1617 }
1618 
1619 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1620  struct ethtool_stats *stats,
1621  uint64_t *data)
1622 {
1623  struct mv643xx_eth_private *mp = netdev_priv(dev);
1624  int i;
1625 
1626  mv643xx_eth_get_stats(dev);
1627  mib_counters_update(mp);
1628  mv643xx_eth_grab_lro_stats(mp);
1629 
1630  for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1631  const struct mv643xx_eth_stats *stat;
1632  void *p;
1633 
1634  stat = mv643xx_eth_stats + i;
1635 
1636  if (stat->netdev_off >= 0)
1637  p = ((void *)mp->dev) + stat->netdev_off;
1638  else
1639  p = ((void *)mp) + stat->mp_off;
1640 
1641  data[i] = (stat->sizeof_stat == 8) ?
1642  *(uint64_t *)p : *(uint32_t *)p;
1643  }
1644 }
1645 
1646 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1647 {
1648  if (sset == ETH_SS_STATS)
1649  return ARRAY_SIZE(mv643xx_eth_stats);
1650 
1651  return -EOPNOTSUPP;
1652 }
1653 
1654 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1655  .get_settings = mv643xx_eth_get_settings,
1656  .set_settings = mv643xx_eth_set_settings,
1657  .get_drvinfo = mv643xx_eth_get_drvinfo,
1658  .nway_reset = mv643xx_eth_nway_reset,
1659  .get_link = ethtool_op_get_link,
1660  .get_coalesce = mv643xx_eth_get_coalesce,
1661  .set_coalesce = mv643xx_eth_set_coalesce,
1662  .get_ringparam = mv643xx_eth_get_ringparam,
1663  .set_ringparam = mv643xx_eth_set_ringparam,
1664  .get_strings = mv643xx_eth_get_strings,
1665  .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1666  .get_sset_count = mv643xx_eth_get_sset_count,
1667  .get_ts_info = ethtool_op_get_ts_info,
1668 };
1669 
1670 
1671 /* address handling *********************************************************/
1672 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1673 {
1674  unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1675  unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1676 
1677  addr[0] = (mac_h >> 24) & 0xff;
1678  addr[1] = (mac_h >> 16) & 0xff;
1679  addr[2] = (mac_h >> 8) & 0xff;
1680  addr[3] = mac_h & 0xff;
1681  addr[4] = (mac_l >> 8) & 0xff;
1682  addr[5] = mac_l & 0xff;
1683 }
1684 
1685 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1686 {
1687  wrlp(mp, MAC_ADDR_HIGH,
1688  (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1689  wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1690 }
1691 
1692 static u32 uc_addr_filter_mask(struct net_device *dev)
1693 {
1694  struct netdev_hw_addr *ha;
1695  u32 nibbles;
1696 
1697  if (dev->flags & IFF_PROMISC)
1698  return 0;
1699 
1700  nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1701  netdev_for_each_uc_addr(ha, dev) {
1702  if (memcmp(dev->dev_addr, ha->addr, 5))
1703  return 0;
1704  if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1705  return 0;
1706 
1707  nibbles |= 1 << (ha->addr[5] & 0x0f);
1708  }
1709 
1710  return nibbles;
1711 }
1712 
1713 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1714 {
1715  struct mv643xx_eth_private *mp = netdev_priv(dev);
1716  u32 port_config;
1717  u32 nibbles;
1718  int i;
1719 
1720  uc_addr_set(mp, dev->dev_addr);
1721 
1722  port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1723 
1724  nibbles = uc_addr_filter_mask(dev);
1725  if (!nibbles) {
1726  port_config |= UNICAST_PROMISCUOUS_MODE;
1727  nibbles = 0xffff;
1728  }
1729 
1730  for (i = 0; i < 16; i += 4) {
1731  int off = UNICAST_TABLE(mp->port_num) + i;
1732  u32 v;
1733 
1734  v = 0;
1735  if (nibbles & 1)
1736  v |= 0x00000001;
1737  if (nibbles & 2)
1738  v |= 0x00000100;
1739  if (nibbles & 4)
1740  v |= 0x00010000;
1741  if (nibbles & 8)
1742  v |= 0x01000000;
1743  nibbles >>= 4;
1744 
1745  wrl(mp, off, v);
1746  }
1747 
1748  wrlp(mp, PORT_CONFIG, port_config);
1749 }
1750 
1751 static int addr_crc(unsigned char *addr)
1752 {
1753  int crc = 0;
1754  int i;
1755 
1756  for (i = 0; i < 6; i++) {
1757  int j;
1758 
1759  crc = (crc ^ addr[i]) << 8;
1760  for (j = 7; j >= 0; j--) {
1761  if (crc & (0x100 << j))
1762  crc ^= 0x107 << j;
1763  }
1764  }
1765 
1766  return crc;
1767 }
1768 
1769 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1770 {
1771  struct mv643xx_eth_private *mp = netdev_priv(dev);
1772  u32 *mc_spec;
1773  u32 *mc_other;
1774  struct netdev_hw_addr *ha;
1775  int i;
1776 
1777  if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1778  int port_num;
1779  u32 accept;
1780 
1781 oom:
1782  port_num = mp->port_num;
1783  accept = 0x01010101;
1784  for (i = 0; i < 0x100; i += 4) {
1785  wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1786  wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1787  }
1788  return;
1789  }
1790 
1791  mc_spec = kmalloc(0x200, GFP_ATOMIC);
1792  if (mc_spec == NULL)
1793  goto oom;
1794  mc_other = mc_spec + (0x100 >> 2);
1795 
1796  memset(mc_spec, 0, 0x100);
1797  memset(mc_other, 0, 0x100);
1798 
1799  netdev_for_each_mc_addr(ha, dev) {
1800  u8 *a = ha->addr;
1801  u32 *table;
1802  int entry;
1803 
1804  if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1805  table = mc_spec;
1806  entry = a[5];
1807  } else {
1808  table = mc_other;
1809  entry = addr_crc(a);
1810  }
1811 
1812  table[entry >> 2] |= 1 << (8 * (entry & 3));
1813  }
1814 
1815  for (i = 0; i < 0x100; i += 4) {
1816  wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1817  wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1818  }
1819 
1820  kfree(mc_spec);
1821 }
1822 
1823 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1824 {
1825  mv643xx_eth_program_unicast_filter(dev);
1826  mv643xx_eth_program_multicast_filter(dev);
1827 }
1828 
1829 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1830 {
1831  struct sockaddr *sa = addr;
1832 
1833  if (!is_valid_ether_addr(sa->sa_data))
1834  return -EADDRNOTAVAIL;
1835 
1836  memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1837 
1838  netif_addr_lock_bh(dev);
1839  mv643xx_eth_program_unicast_filter(dev);
1840  netif_addr_unlock_bh(dev);
1841 
1842  return 0;
1843 }
1844 
1845 
1846 /* rx/tx queue initialisation ***********************************************/
1847 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1848 {
1849  struct rx_queue *rxq = mp->rxq + index;
1850  struct rx_desc *rx_desc;
1851  int size;
1852  int i;
1853 
1854  rxq->index = index;
1855 
1856  rxq->rx_ring_size = mp->rx_ring_size;
1857 
1858  rxq->rx_desc_count = 0;
1859  rxq->rx_curr_desc = 0;
1860  rxq->rx_used_desc = 0;
1861 
1862  size = rxq->rx_ring_size * sizeof(struct rx_desc);
1863 
1864  if (index == 0 && size <= mp->rx_desc_sram_size) {
1865  rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1866  mp->rx_desc_sram_size);
1867  rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1868  } else {
1869  rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1870  size, &rxq->rx_desc_dma,
1871  GFP_KERNEL);
1872  }
1873 
1874  if (rxq->rx_desc_area == NULL) {
1875  netdev_err(mp->dev,
1876  "can't allocate rx ring (%d bytes)\n", size);
1877  goto out;
1878  }
1879  memset(rxq->rx_desc_area, 0, size);
1880 
1881  rxq->rx_desc_area_size = size;
1882  rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1883  GFP_KERNEL);
1884  if (rxq->rx_skb == NULL) {
1885  netdev_err(mp->dev, "can't allocate rx skb ring\n");
1886  goto out_free;
1887  }
1888 
1889  rx_desc = rxq->rx_desc_area;
1890  for (i = 0; i < rxq->rx_ring_size; i++) {
1891  int nexti;
1892 
1893  nexti = i + 1;
1894  if (nexti == rxq->rx_ring_size)
1895  nexti = 0;
1896 
1897  rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1898  nexti * sizeof(struct rx_desc);
1899  }
1900 
1901  rxq->lro_mgr.dev = mp->dev;
1902  memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
1903  rxq->lro_mgr.features = LRO_F_NAPI;
1904  rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1905  rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1906  rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
1907  rxq->lro_mgr.max_aggr = 32;
1908  rxq->lro_mgr.frag_align_pad = 0;
1909  rxq->lro_mgr.lro_arr = rxq->lro_arr;
1910  rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
1911 
1912  memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
1913 
1914  return 0;
1915 
1916 
1917 out_free:
1918  if (index == 0 && size <= mp->rx_desc_sram_size)
1919  iounmap(rxq->rx_desc_area);
1920  else
1921  dma_free_coherent(mp->dev->dev.parent, size,
1922  rxq->rx_desc_area,
1923  rxq->rx_desc_dma);
1924 
1925 out:
1926  return -ENOMEM;
1927 }
1928 
1929 static void rxq_deinit(struct rx_queue *rxq)
1930 {
1931  struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1932  int i;
1933 
1934  rxq_disable(rxq);
1935 
1936  for (i = 0; i < rxq->rx_ring_size; i++) {
1937  if (rxq->rx_skb[i]) {
1938  dev_kfree_skb(rxq->rx_skb[i]);
1939  rxq->rx_desc_count--;
1940  }
1941  }
1942 
1943  if (rxq->rx_desc_count) {
1944  netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
1945  rxq->rx_desc_count);
1946  }
1947 
1948  if (rxq->index == 0 &&
1949  rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1950  iounmap(rxq->rx_desc_area);
1951  else
1952  dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
1953  rxq->rx_desc_area, rxq->rx_desc_dma);
1954 
1955  kfree(rxq->rx_skb);
1956 }
1957 
1958 static int txq_init(struct mv643xx_eth_private *mp, int index)
1959 {
1960  struct tx_queue *txq = mp->txq + index;
1961  struct tx_desc *tx_desc;
1962  int size;
1963  int i;
1964 
1965  txq->index = index;
1966 
1967  txq->tx_ring_size = mp->tx_ring_size;
1968 
1969  txq->tx_desc_count = 0;
1970  txq->tx_curr_desc = 0;
1971  txq->tx_used_desc = 0;
1972 
1973  size = txq->tx_ring_size * sizeof(struct tx_desc);
1974 
1975  if (index == 0 && size <= mp->tx_desc_sram_size) {
1976  txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1977  mp->tx_desc_sram_size);
1978  txq->tx_desc_dma = mp->tx_desc_sram_addr;
1979  } else {
1980  txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1981  size, &txq->tx_desc_dma,
1982  GFP_KERNEL);
1983  }
1984 
1985  if (txq->tx_desc_area == NULL) {
1986  netdev_err(mp->dev,
1987  "can't allocate tx ring (%d bytes)\n", size);
1988  return -ENOMEM;
1989  }
1990  memset(txq->tx_desc_area, 0, size);
1991 
1992  txq->tx_desc_area_size = size;
1993 
1994  tx_desc = txq->tx_desc_area;
1995  for (i = 0; i < txq->tx_ring_size; i++) {
1996  struct tx_desc *txd = tx_desc + i;
1997  int nexti;
1998 
1999  nexti = i + 1;
2000  if (nexti == txq->tx_ring_size)
2001  nexti = 0;
2002 
2003  txd->cmd_sts = 0;
2004  txd->next_desc_ptr = txq->tx_desc_dma +
2005  nexti * sizeof(struct tx_desc);
2006  }
2007 
2008  skb_queue_head_init(&txq->tx_skb);
2009 
2010  return 0;
2011 }
2012 
2013 static void txq_deinit(struct tx_queue *txq)
2014 {
2015  struct mv643xx_eth_private *mp = txq_to_mp(txq);
2016 
2017  txq_disable(txq);
2018  txq_reclaim(txq, txq->tx_ring_size, 1);
2019 
2020  BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2021 
2022  if (txq->index == 0 &&
2023  txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2024  iounmap(txq->tx_desc_area);
2025  else
2026  dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2027  txq->tx_desc_area, txq->tx_desc_dma);
2028 }
2029 
2030 
2031 /* netdev ops and related ***************************************************/
2032 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2033 {
2034  u32 int_cause;
2035  u32 int_cause_ext;
2036 
2037  int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
2038  if (int_cause == 0)
2039  return 0;
2040 
2041  int_cause_ext = 0;
2042  if (int_cause & INT_EXT) {
2043  int_cause &= ~INT_EXT;
2044  int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2045  }
2046 
2047  if (int_cause) {
2048  wrlp(mp, INT_CAUSE, ~int_cause);
2049  mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2050  ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2051  mp->work_rx |= (int_cause & INT_RX) >> 2;
2052  }
2053 
2054  int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2055  if (int_cause_ext) {
2056  wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2057  if (int_cause_ext & INT_EXT_LINK_PHY)
2058  mp->work_link = 1;
2059  mp->work_tx |= int_cause_ext & INT_EXT_TX;
2060  }
2061 
2062  return 1;
2063 }
2064 
2065 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2066 {
2067  struct net_device *dev = (struct net_device *)dev_id;
2068  struct mv643xx_eth_private *mp = netdev_priv(dev);
2069 
2070  if (unlikely(!mv643xx_eth_collect_events(mp)))
2071  return IRQ_NONE;
2072 
2073  wrlp(mp, INT_MASK, 0);
2074  napi_schedule(&mp->napi);
2075 
2076  return IRQ_HANDLED;
2077 }
2078 
2079 static void handle_link_event(struct mv643xx_eth_private *mp)
2080 {
2081  struct net_device *dev = mp->dev;
2082  u32 port_status;
2083  int speed;
2084  int duplex;
2085  int fc;
2086 
2087  port_status = rdlp(mp, PORT_STATUS);
2088  if (!(port_status & LINK_UP)) {
2089  if (netif_carrier_ok(dev)) {
2090  int i;
2091 
2092  netdev_info(dev, "link down\n");
2093 
2094  netif_carrier_off(dev);
2095 
2096  for (i = 0; i < mp->txq_count; i++) {
2097  struct tx_queue *txq = mp->txq + i;
2098 
2099  txq_reclaim(txq, txq->tx_ring_size, 1);
2100  txq_reset_hw_ptr(txq);
2101  }
2102  }
2103  return;
2104  }
2105 
2106  switch (port_status & PORT_SPEED_MASK) {
2107  case PORT_SPEED_10:
2108  speed = 10;
2109  break;
2110  case PORT_SPEED_100:
2111  speed = 100;
2112  break;
2113  case PORT_SPEED_1000:
2114  speed = 1000;
2115  break;
2116  default:
2117  speed = -1;
2118  break;
2119  }
2120  duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2121  fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2122 
2123  netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2124  speed, duplex ? "full" : "half", fc ? "en" : "dis");
2125 
2126  if (!netif_carrier_ok(dev))
2127  netif_carrier_on(dev);
2128 }
2129 
2130 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2131 {
2132  struct mv643xx_eth_private *mp;
2133  int work_done;
2134 
2135  mp = container_of(napi, struct mv643xx_eth_private, napi);
2136 
2137  if (unlikely(mp->oom)) {
2138  mp->oom = 0;
2139  del_timer(&mp->rx_oom);
2140  }
2141 
2142  work_done = 0;
2143  while (work_done < budget) {
2144  u8 queue_mask;
2145  int queue;
2146  int work_tbd;
2147 
2148  if (mp->work_link) {
2149  mp->work_link = 0;
2150  handle_link_event(mp);
2151  work_done++;
2152  continue;
2153  }
2154 
2155  queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2156  if (likely(!mp->oom))
2157  queue_mask |= mp->work_rx_refill;
2158 
2159  if (!queue_mask) {
2160  if (mv643xx_eth_collect_events(mp))
2161  continue;
2162  break;
2163  }
2164 
2165  queue = fls(queue_mask) - 1;
2166  queue_mask = 1 << queue;
2167 
2168  work_tbd = budget - work_done;
2169  if (work_tbd > 16)
2170  work_tbd = 16;
2171 
2172  if (mp->work_tx_end & queue_mask) {
2173  txq_kick(mp->txq + queue);
2174  } else if (mp->work_tx & queue_mask) {
2175  work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2176  txq_maybe_wake(mp->txq + queue);
2177  } else if (mp->work_rx & queue_mask) {
2178  work_done += rxq_process(mp->rxq + queue, work_tbd);
2179  } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2180  work_done += rxq_refill(mp->rxq + queue, work_tbd);
2181  } else {
2182  BUG();
2183  }
2184  }
2185 
2186  if (work_done < budget) {
2187  if (mp->oom)
2188  mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2189  napi_complete(napi);
2190  wrlp(mp, INT_MASK, mp->int_mask);
2191  }
2192 
2193  return work_done;
2194 }
2195 
2196 static inline void oom_timer_wrapper(unsigned long data)
2197 {
2198  struct mv643xx_eth_private *mp = (void *)data;
2199 
2200  napi_schedule(&mp->napi);
2201 }
2202 
2203 static void phy_reset(struct mv643xx_eth_private *mp)
2204 {
2205  int data;
2206 
2207  data = phy_read(mp->phy, MII_BMCR);
2208  if (data < 0)
2209  return;
2210 
2211  data |= BMCR_RESET;
2212  if (phy_write(mp->phy, MII_BMCR, data) < 0)
2213  return;
2214 
2215  do {
2216  data = phy_read(mp->phy, MII_BMCR);
2217  } while (data >= 0 && data & BMCR_RESET);
2218 }
2219 
2220 static void port_start(struct mv643xx_eth_private *mp)
2221 {
2222  u32 pscr;
2223  int i;
2224 
2225  /*
2226  * Perform PHY reset, if there is a PHY.
2227  */
2228  if (mp->phy != NULL) {
2229  struct ethtool_cmd cmd;
2230 
2231  mv643xx_eth_get_settings(mp->dev, &cmd);
2232  phy_reset(mp);
2233  mv643xx_eth_set_settings(mp->dev, &cmd);
2234  }
2235 
2236  /*
2237  * Configure basic link parameters.
2238  */
2239  pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2240 
2241  pscr |= SERIAL_PORT_ENABLE;
2242  wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2243 
2244  pscr |= DO_NOT_FORCE_LINK_FAIL;
2245  if (mp->phy == NULL)
2246  pscr |= FORCE_LINK_PASS;
2247  wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2248 
2249  /*
2250  * Configure TX path and queues.
2251  */
2252  tx_set_rate(mp, 1000000000, 16777216);
2253  for (i = 0; i < mp->txq_count; i++) {
2254  struct tx_queue *txq = mp->txq + i;
2255 
2256  txq_reset_hw_ptr(txq);
2257  txq_set_rate(txq, 1000000000, 16777216);
2258  txq_set_fixed_prio_mode(txq);
2259  }
2260 
2261  /*
2262  * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2263  * frames to RX queue #0, and include the pseudo-header when
2264  * calculating receive checksums.
2265  */
2266  mv643xx_eth_set_features(mp->dev, mp->dev->features);
2267 
2268  /*
2269  * Treat BPDUs as normal multicasts, and disable partition mode.
2270  */
2271  wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2272 
2273  /*
2274  * Add configured unicast addresses to address filter table.
2275  */
2276  mv643xx_eth_program_unicast_filter(mp->dev);
2277 
2278  /*
2279  * Enable the receive queues.
2280  */
2281  for (i = 0; i < mp->rxq_count; i++) {
2282  struct rx_queue *rxq = mp->rxq + i;
2283  u32 addr;
2284 
2285  addr = (u32)rxq->rx_desc_dma;
2286  addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2287  wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2288 
2289  rxq_enable(rxq);
2290  }
2291 }
2292 
2293 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2294 {
2295  int skb_size;
2296 
2297  /*
2298  * Reserve 2+14 bytes for an ethernet header (the hardware
2299  * automatically prepends 2 bytes of dummy data to each
2300  * received packet), 16 bytes for up to four VLAN tags, and
2301  * 4 bytes for the trailing FCS -- 36 bytes total.
2302  */
2303  skb_size = mp->dev->mtu + 36;
2304 
2305  /*
2306  * Make sure that the skb size is a multiple of 8 bytes, as
2307  * the lower three bits of the receive descriptor's buffer
2308  * size field are ignored by the hardware.
2309  */
2310  mp->skb_size = (skb_size + 7) & ~7;
2311 
2312  /*
2313  * If NET_SKB_PAD is smaller than a cache line,
2314  * netdev_alloc_skb() will cause skb->data to be misaligned
2315  * to a cache line boundary. If this is the case, include
2316  * some extra space to allow re-aligning the data area.
2317  */
2318  mp->skb_size += SKB_DMA_REALIGN;
2319 }
2320 
2321 static int mv643xx_eth_open(struct net_device *dev)
2322 {
2323  struct mv643xx_eth_private *mp = netdev_priv(dev);
2324  int err;
2325  int i;
2326 
2327  wrlp(mp, INT_CAUSE, 0);
2328  wrlp(mp, INT_CAUSE_EXT, 0);
2329  rdlp(mp, INT_CAUSE_EXT);
2330 
2331  err = request_irq(dev->irq, mv643xx_eth_irq,
2332  IRQF_SHARED, dev->name, dev);
2333  if (err) {
2334  netdev_err(dev, "can't assign irq\n");
2335  return -EAGAIN;
2336  }
2337 
2338  mv643xx_eth_recalc_skb_size(mp);
2339 
2340  napi_enable(&mp->napi);
2341 
2342  mp->int_mask = INT_EXT;
2343 
2344  for (i = 0; i < mp->rxq_count; i++) {
2345  err = rxq_init(mp, i);
2346  if (err) {
2347  while (--i >= 0)
2348  rxq_deinit(mp->rxq + i);
2349  goto out;
2350  }
2351 
2352  rxq_refill(mp->rxq + i, INT_MAX);
2353  mp->int_mask |= INT_RX_0 << i;
2354  }
2355 
2356  if (mp->oom) {
2357  mp->rx_oom.expires = jiffies + (HZ / 10);
2358  add_timer(&mp->rx_oom);
2359  }
2360 
2361  for (i = 0; i < mp->txq_count; i++) {
2362  err = txq_init(mp, i);
2363  if (err) {
2364  while (--i >= 0)
2365  txq_deinit(mp->txq + i);
2366  goto out_free;
2367  }
2368  mp->int_mask |= INT_TX_END_0 << i;
2369  }
2370 
2371  port_start(mp);
2372 
2373  wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2374  wrlp(mp, INT_MASK, mp->int_mask);
2375 
2376  return 0;
2377 
2378 
2379 out_free:
2380  for (i = 0; i < mp->rxq_count; i++)
2381  rxq_deinit(mp->rxq + i);
2382 out:
2383  free_irq(dev->irq, dev);
2384 
2385  return err;
2386 }
2387 
2388 static void port_reset(struct mv643xx_eth_private *mp)
2389 {
2390  unsigned int data;
2391  int i;
2392 
2393  for (i = 0; i < mp->rxq_count; i++)
2394  rxq_disable(mp->rxq + i);
2395  for (i = 0; i < mp->txq_count; i++)
2396  txq_disable(mp->txq + i);
2397 
2398  while (1) {
2399  u32 ps = rdlp(mp, PORT_STATUS);
2400 
2401  if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2402  break;
2403  udelay(10);
2404  }
2405 
2406  /* Reset the Enable bit in the Configuration Register */
2407  data = rdlp(mp, PORT_SERIAL_CONTROL);
2408  data &= ~(SERIAL_PORT_ENABLE |
2409  DO_NOT_FORCE_LINK_FAIL |
2410  FORCE_LINK_PASS);
2411  wrlp(mp, PORT_SERIAL_CONTROL, data);
2412 }
2413 
2414 static int mv643xx_eth_stop(struct net_device *dev)
2415 {
2416  struct mv643xx_eth_private *mp = netdev_priv(dev);
2417  int i;
2418 
2419  wrlp(mp, INT_MASK_EXT, 0x00000000);
2420  wrlp(mp, INT_MASK, 0x00000000);
2421  rdlp(mp, INT_MASK);
2422 
2423  napi_disable(&mp->napi);
2424 
2425  del_timer_sync(&mp->rx_oom);
2426 
2427  netif_carrier_off(dev);
2428 
2429  free_irq(dev->irq, dev);
2430 
2431  port_reset(mp);
2432  mv643xx_eth_get_stats(dev);
2433  mib_counters_update(mp);
2434  del_timer_sync(&mp->mib_counters_timer);
2435 
2436  for (i = 0; i < mp->rxq_count; i++)
2437  rxq_deinit(mp->rxq + i);
2438  for (i = 0; i < mp->txq_count; i++)
2439  txq_deinit(mp->txq + i);
2440 
2441  return 0;
2442 }
2443 
2444 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2445 {
2446  struct mv643xx_eth_private *mp = netdev_priv(dev);
2447 
2448  if (mp->phy != NULL)
2449  return phy_mii_ioctl(mp->phy, ifr, cmd);
2450 
2451  return -EOPNOTSUPP;
2452 }
2453 
2454 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2455 {
2456  struct mv643xx_eth_private *mp = netdev_priv(dev);
2457 
2458  if (new_mtu < 64 || new_mtu > 9500)
2459  return -EINVAL;
2460 
2461  dev->mtu = new_mtu;
2462  mv643xx_eth_recalc_skb_size(mp);
2463  tx_set_rate(mp, 1000000000, 16777216);
2464 
2465  if (!netif_running(dev))
2466  return 0;
2467 
2468  /*
2469  * Stop and then re-open the interface. This will allocate RX
2470  * skbs of the new MTU.
2471  * There is a possible danger that the open will not succeed,
2472  * due to memory being full.
2473  */
2474  mv643xx_eth_stop(dev);
2475  if (mv643xx_eth_open(dev)) {
2476  netdev_err(dev,
2477  "fatal error on re-opening device after MTU change\n");
2478  }
2479 
2480  return 0;
2481 }
2482 
2483 static void tx_timeout_task(struct work_struct *ugly)
2484 {
2485  struct mv643xx_eth_private *mp;
2486 
2487  mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2488  if (netif_running(mp->dev)) {
2489  netif_tx_stop_all_queues(mp->dev);
2490  port_reset(mp);
2491  port_start(mp);
2492  netif_tx_wake_all_queues(mp->dev);
2493  }
2494 }
2495 
2496 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2497 {
2498  struct mv643xx_eth_private *mp = netdev_priv(dev);
2499 
2500  netdev_info(dev, "tx timeout\n");
2501 
2502  schedule_work(&mp->tx_timeout_task);
2503 }
2504 
2505 #ifdef CONFIG_NET_POLL_CONTROLLER
2506 static void mv643xx_eth_netpoll(struct net_device *dev)
2507 {
2508  struct mv643xx_eth_private *mp = netdev_priv(dev);
2509 
2510  wrlp(mp, INT_MASK, 0x00000000);
2511  rdlp(mp, INT_MASK);
2512 
2513  mv643xx_eth_irq(dev->irq, dev);
2514 
2515  wrlp(mp, INT_MASK, mp->int_mask);
2516 }
2517 #endif
2518 
2519 
2520 /* platform glue ************************************************************/
2521 static void
2522 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2523  const struct mbus_dram_target_info *dram)
2524 {
2525  void __iomem *base = msp->base;
2526  u32 win_enable;
2527  u32 win_protect;
2528  int i;
2529 
2530  for (i = 0; i < 6; i++) {
2531  writel(0, base + WINDOW_BASE(i));
2532  writel(0, base + WINDOW_SIZE(i));
2533  if (i < 4)
2534  writel(0, base + WINDOW_REMAP_HIGH(i));
2535  }
2536 
2537  win_enable = 0x3f;
2538  win_protect = 0;
2539 
2540  for (i = 0; i < dram->num_cs; i++) {
2541  const struct mbus_dram_window *cs = dram->cs + i;
2542 
2543  writel((cs->base & 0xffff0000) |
2544  (cs->mbus_attr << 8) |
2545  dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2546  writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2547 
2548  win_enable &= ~(1 << i);
2549  win_protect |= 3 << (2 * i);
2550  }
2551 
2552  writel(win_enable, base + WINDOW_BAR_ENABLE);
2553  msp->win_protect = win_protect;
2554 }
2555 
2556 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2557 {
2558  /*
2559  * Check whether we have a 14-bit coal limit field in bits
2560  * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2561  * SDMA config register.
2562  */
2563  writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2564  if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2565  msp->extended_rx_coal_limit = 1;
2566  else
2567  msp->extended_rx_coal_limit = 0;
2568 
2569  /*
2570  * Check whether the MAC supports TX rate control, and if
2571  * yes, whether its associated registers are in the old or
2572  * the new place.
2573  */
2574  writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2575  if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2576  msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2577  } else {
2578  writel(7, msp->base + 0x0400 + TX_BW_RATE);
2579  if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2580  msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2581  else
2582  msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2583  }
2584 }
2585 
2586 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2587 {
2588  static int mv643xx_eth_version_printed;
2589  struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2590  struct mv643xx_eth_shared_private *msp;
2591  const struct mbus_dram_target_info *dram;
2592  struct resource *res;
2593  int ret;
2594 
2595  if (!mv643xx_eth_version_printed++)
2596  pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2597  mv643xx_eth_driver_version);
2598 
2599  ret = -EINVAL;
2600  res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2601  if (res == NULL)
2602  goto out;
2603 
2604  ret = -ENOMEM;
2605  msp = kzalloc(sizeof(*msp), GFP_KERNEL);
2606  if (msp == NULL)
2607  goto out;
2608 
2609  msp->base = ioremap(res->start, resource_size(res));
2610  if (msp->base == NULL)
2611  goto out_free;
2612 
2613  /*
2614  * Set up and register SMI bus.
2615  */
2616  if (pd == NULL || pd->shared_smi == NULL) {
2617  msp->smi_bus = mdiobus_alloc();
2618  if (msp->smi_bus == NULL)
2619  goto out_unmap;
2620 
2621  msp->smi_bus->priv = msp;
2622  msp->smi_bus->name = "mv643xx_eth smi";
2623  msp->smi_bus->read = smi_bus_read;
2624  msp->smi_bus->write = smi_bus_write,
2625  snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d",
2626  pdev->name, pdev->id);
2627  msp->smi_bus->parent = &pdev->dev;
2628  msp->smi_bus->phy_mask = 0xffffffff;
2629  if (mdiobus_register(msp->smi_bus) < 0)
2630  goto out_free_mii_bus;
2631  msp->smi = msp;
2632  } else {
2633  msp->smi = platform_get_drvdata(pd->shared_smi);
2634  }
2635 
2636  msp->err_interrupt = NO_IRQ;
2637  init_waitqueue_head(&msp->smi_busy_wait);
2638 
2639  /*
2640  * Check whether the error interrupt is hooked up.
2641  */
2642  res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2643  if (res != NULL) {
2644  int err;
2645 
2646  err = request_irq(res->start, mv643xx_eth_err_irq,
2647  IRQF_SHARED, "mv643xx_eth", msp);
2648  if (!err) {
2649  writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2650  msp->err_interrupt = res->start;
2651  }
2652  }
2653 
2654  /*
2655  * (Re-)program MBUS remapping windows if we are asked to.
2656  */
2657  dram = mv_mbus_dram_info();
2658  if (dram)
2659  mv643xx_eth_conf_mbus_windows(msp, dram);
2660 
2661  msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2662  pd->tx_csum_limit : 9 * 1024;
2663  infer_hw_params(msp);
2664 
2665  platform_set_drvdata(pdev, msp);
2666 
2667  return 0;
2668 
2669 out_free_mii_bus:
2670  mdiobus_free(msp->smi_bus);
2671 out_unmap:
2672  iounmap(msp->base);
2673 out_free:
2674  kfree(msp);
2675 out:
2676  return ret;
2677 }
2678 
2679 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2680 {
2681  struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2682  struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2683 
2684  if (pd == NULL || pd->shared_smi == NULL) {
2685  mdiobus_unregister(msp->smi_bus);
2686  mdiobus_free(msp->smi_bus);
2687  }
2688  if (msp->err_interrupt != NO_IRQ)
2689  free_irq(msp->err_interrupt, msp);
2690  iounmap(msp->base);
2691  kfree(msp);
2692 
2693  return 0;
2694 }
2695 
2696 static struct platform_driver mv643xx_eth_shared_driver = {
2697  .probe = mv643xx_eth_shared_probe,
2698  .remove = mv643xx_eth_shared_remove,
2699  .driver = {
2700  .name = MV643XX_ETH_SHARED_NAME,
2701  .owner = THIS_MODULE,
2702  },
2703 };
2704 
2705 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2706 {
2707  int addr_shift = 5 * mp->port_num;
2708  u32 data;
2709 
2710  data = rdl(mp, PHY_ADDR);
2711  data &= ~(0x1f << addr_shift);
2712  data |= (phy_addr & 0x1f) << addr_shift;
2713  wrl(mp, PHY_ADDR, data);
2714 }
2715 
2716 static int phy_addr_get(struct mv643xx_eth_private *mp)
2717 {
2718  unsigned int data;
2719 
2720  data = rdl(mp, PHY_ADDR);
2721 
2722  return (data >> (5 * mp->port_num)) & 0x1f;
2723 }
2724 
2725 static void set_params(struct mv643xx_eth_private *mp,
2726  struct mv643xx_eth_platform_data *pd)
2727 {
2728  struct net_device *dev = mp->dev;
2729 
2730  if (is_valid_ether_addr(pd->mac_addr))
2731  memcpy(dev->dev_addr, pd->mac_addr, 6);
2732  else
2733  uc_addr_get(mp, dev->dev_addr);
2734 
2735  mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2736  if (pd->rx_queue_size)
2737  mp->rx_ring_size = pd->rx_queue_size;
2738  mp->rx_desc_sram_addr = pd->rx_sram_addr;
2739  mp->rx_desc_sram_size = pd->rx_sram_size;
2740 
2741  mp->rxq_count = pd->rx_queue_count ? : 1;
2742 
2743  mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2744  if (pd->tx_queue_size)
2745  mp->tx_ring_size = pd->tx_queue_size;
2746  mp->tx_desc_sram_addr = pd->tx_sram_addr;
2747  mp->tx_desc_sram_size = pd->tx_sram_size;
2748 
2749  mp->txq_count = pd->tx_queue_count ? : 1;
2750 }
2751 
2752 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2753  int phy_addr)
2754 {
2755  struct mii_bus *bus = mp->shared->smi->smi_bus;
2756  struct phy_device *phydev;
2757  int start;
2758  int num;
2759  int i;
2760 
2761  if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2762  start = phy_addr_get(mp) & 0x1f;
2763  num = 32;
2764  } else {
2765  start = phy_addr & 0x1f;
2766  num = 1;
2767  }
2768 
2769  phydev = NULL;
2770  for (i = 0; i < num; i++) {
2771  int addr = (start + i) & 0x1f;
2772 
2773  if (bus->phy_map[addr] == NULL)
2774  mdiobus_scan(bus, addr);
2775 
2776  if (phydev == NULL) {
2777  phydev = bus->phy_map[addr];
2778  if (phydev != NULL)
2779  phy_addr_set(mp, addr);
2780  }
2781  }
2782 
2783  return phydev;
2784 }
2785 
2786 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2787 {
2788  struct phy_device *phy = mp->phy;
2789 
2790  phy_reset(mp);
2791 
2792  phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
2793 
2794  if (speed == 0) {
2795  phy->autoneg = AUTONEG_ENABLE;
2796  phy->speed = 0;
2797  phy->duplex = 0;
2798  phy->advertising = phy->supported | ADVERTISED_Autoneg;
2799  } else {
2800  phy->autoneg = AUTONEG_DISABLE;
2801  phy->advertising = 0;
2802  phy->speed = speed;
2803  phy->duplex = duplex;
2804  }
2805  phy_start_aneg(phy);
2806 }
2807 
2808 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2809 {
2810  u32 pscr;
2811 
2812  pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2813  if (pscr & SERIAL_PORT_ENABLE) {
2814  pscr &= ~SERIAL_PORT_ENABLE;
2815  wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2816  }
2817 
2818  pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2819  if (mp->phy == NULL) {
2820  pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2821  if (speed == SPEED_1000)
2822  pscr |= SET_GMII_SPEED_TO_1000;
2823  else if (speed == SPEED_100)
2824  pscr |= SET_MII_SPEED_TO_100;
2825 
2826  pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2827 
2828  pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2829  if (duplex == DUPLEX_FULL)
2830  pscr |= SET_FULL_DUPLEX_MODE;
2831  }
2832 
2833  wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2834 }
2835 
2836 static const struct net_device_ops mv643xx_eth_netdev_ops = {
2837  .ndo_open = mv643xx_eth_open,
2838  .ndo_stop = mv643xx_eth_stop,
2839  .ndo_start_xmit = mv643xx_eth_xmit,
2840  .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2841  .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2842  .ndo_validate_addr = eth_validate_addr,
2843  .ndo_do_ioctl = mv643xx_eth_ioctl,
2844  .ndo_change_mtu = mv643xx_eth_change_mtu,
2845  .ndo_set_features = mv643xx_eth_set_features,
2846  .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2847  .ndo_get_stats = mv643xx_eth_get_stats,
2848 #ifdef CONFIG_NET_POLL_CONTROLLER
2849  .ndo_poll_controller = mv643xx_eth_netpoll,
2850 #endif
2851 };
2852 
2853 static int mv643xx_eth_probe(struct platform_device *pdev)
2854 {
2855  struct mv643xx_eth_platform_data *pd;
2856  struct mv643xx_eth_private *mp;
2857  struct net_device *dev;
2858  struct resource *res;
2859  int err;
2860 
2861  pd = pdev->dev.platform_data;
2862  if (pd == NULL) {
2863  dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
2864  return -ENODEV;
2865  }
2866 
2867  if (pd->shared == NULL) {
2868  dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
2869  return -ENODEV;
2870  }
2871 
2872  dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2873  if (!dev)
2874  return -ENOMEM;
2875 
2876  mp = netdev_priv(dev);
2877  platform_set_drvdata(pdev, mp);
2878 
2879  mp->shared = platform_get_drvdata(pd->shared);
2880  mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2881  mp->port_num = pd->port_number;
2882 
2883  mp->dev = dev;
2884 
2885  /*
2886  * Start with a default rate, and if there is a clock, allow
2887  * it to override the default.
2888  */
2889  mp->t_clk = 133000000;
2890 #if defined(CONFIG_HAVE_CLK)
2891  mp->clk = clk_get(&pdev->dev, (pdev->id ? "1" : "0"));
2892  if (!IS_ERR(mp->clk)) {
2893  clk_prepare_enable(mp->clk);
2894  mp->t_clk = clk_get_rate(mp->clk);
2895  }
2896 #endif
2897  set_params(mp, pd);
2898  netif_set_real_num_tx_queues(dev, mp->txq_count);
2899  netif_set_real_num_rx_queues(dev, mp->rxq_count);
2900 
2901  if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2902  mp->phy = phy_scan(mp, pd->phy_addr);
2903 
2904  if (mp->phy != NULL)
2905  phy_init(mp, pd->speed, pd->duplex);
2906 
2907  SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2908 
2909  init_pscr(mp, pd->speed, pd->duplex);
2910 
2911 
2912  mib_counters_clear(mp);
2913 
2914  init_timer(&mp->mib_counters_timer);
2915  mp->mib_counters_timer.data = (unsigned long)mp;
2916  mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2917  mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2918  add_timer(&mp->mib_counters_timer);
2919 
2920  spin_lock_init(&mp->mib_counters_lock);
2921 
2922  INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2923 
2924  netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2925 
2926  init_timer(&mp->rx_oom);
2927  mp->rx_oom.data = (unsigned long)mp;
2928  mp->rx_oom.function = oom_timer_wrapper;
2929 
2930 
2931  res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2932  BUG_ON(!res);
2933  dev->irq = res->start;
2934 
2935  dev->netdev_ops = &mv643xx_eth_netdev_ops;
2936 
2937  dev->watchdog_timeo = 2 * HZ;
2938  dev->base_addr = 0;
2939 
2940  dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
2941  NETIF_F_RXCSUM | NETIF_F_LRO;
2942  dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
2943  dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2944 
2945  dev->priv_flags |= IFF_UNICAST_FLT;
2946 
2947  SET_NETDEV_DEV(dev, &pdev->dev);
2948 
2949  if (mp->shared->win_protect)
2950  wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2951 
2952  netif_carrier_off(dev);
2953 
2954  wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2955 
2956  set_rx_coal(mp, 250);
2957  set_tx_coal(mp, 0);
2958 
2959  err = register_netdev(dev);
2960  if (err)
2961  goto out;
2962 
2963  netdev_notice(dev, "port %d with MAC address %pM\n",
2964  mp->port_num, dev->dev_addr);
2965 
2966  if (mp->tx_desc_sram_size > 0)
2967  netdev_notice(dev, "configured with sram\n");
2968 
2969  return 0;
2970 
2971 out:
2972 #if defined(CONFIG_HAVE_CLK)
2973  if (!IS_ERR(mp->clk)) {
2974  clk_disable_unprepare(mp->clk);
2975  clk_put(mp->clk);
2976  }
2977 #endif
2978  free_netdev(dev);
2979 
2980  return err;
2981 }
2982 
2983 static int mv643xx_eth_remove(struct platform_device *pdev)
2984 {
2985  struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2986 
2987  unregister_netdev(mp->dev);
2988  if (mp->phy != NULL)
2989  phy_detach(mp->phy);
2990  cancel_work_sync(&mp->tx_timeout_task);
2991 
2992 #if defined(CONFIG_HAVE_CLK)
2993  if (!IS_ERR(mp->clk)) {
2994  clk_disable_unprepare(mp->clk);
2995  clk_put(mp->clk);
2996  }
2997 #endif
2998 
2999  free_netdev(mp->dev);
3000 
3001  platform_set_drvdata(pdev, NULL);
3002 
3003  return 0;
3004 }
3005 
3006 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3007 {
3008  struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3009 
3010  /* Mask all interrupts on ethernet port */
3011  wrlp(mp, INT_MASK, 0);
3012  rdlp(mp, INT_MASK);
3013 
3014  if (netif_running(mp->dev))
3015  port_reset(mp);
3016 }
3017 
3018 static struct platform_driver mv643xx_eth_driver = {
3019  .probe = mv643xx_eth_probe,
3020  .remove = mv643xx_eth_remove,
3021  .shutdown = mv643xx_eth_shutdown,
3022  .driver = {
3023  .name = MV643XX_ETH_NAME,
3024  .owner = THIS_MODULE,
3025  },
3026 };
3027 
3028 static int __init mv643xx_eth_init_module(void)
3029 {
3030  int rc;
3031 
3032  rc = platform_driver_register(&mv643xx_eth_shared_driver);
3033  if (!rc) {
3034  rc = platform_driver_register(&mv643xx_eth_driver);
3035  if (rc)
3036  platform_driver_unregister(&mv643xx_eth_shared_driver);
3037  }
3038 
3039  return rc;
3040 }
3041 module_init(mv643xx_eth_init_module);
3042 
3043 static void __exit mv643xx_eth_cleanup_module(void)
3044 {
3045  platform_driver_unregister(&mv643xx_eth_driver);
3046  platform_driver_unregister(&mv643xx_eth_shared_driver);
3047 }
3048 module_exit(mv643xx_eth_cleanup_module);
3049 
3050 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3051  "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3052 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3053 MODULE_LICENSE("GPL");
3054 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3055 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
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