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hw.c
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1 /******************************************************************************
2  *
3  * Copyright(c) 2009-2012 Realtek Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  * The full GNU General Public License is included in this distribution in the
19  * file called LICENSE.
20  *
21  * Contact Information:
22  * wlanfae <[email protected]>
23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24  * Hsinchu 300, Taiwan.
25  *
26  * Larry Finger <[email protected]>
27  *
28  *****************************************************************************/
29 
30 #include "../wifi.h"
31 #include "../efuse.h"
32 #include "../base.h"
33 #include "../regd.h"
34 #include "../cam.h"
35 #include "../ps.h"
36 #include "../pci.h"
37 #include "reg.h"
38 #include "def.h"
39 #include "phy.h"
40 #include "dm.h"
41 #include "fw.h"
42 #include "led.h"
43 #include "sw.h"
44 #include "hw.h"
45 
46 u32 rtl92de_read_dword_dbi(struct ieee80211_hw *hw, u16 offset, u8 direct)
47 {
48  struct rtl_priv *rtlpriv = rtl_priv(hw);
49  u32 value;
50 
51  rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC));
52  rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(1) | direct);
53  udelay(10);
54  value = rtl_read_dword(rtlpriv, REG_DBI_RDATA);
55  return value;
56 }
57 
58 void rtl92de_write_dword_dbi(struct ieee80211_hw *hw,
59  u16 offset, u32 value, u8 direct)
60 {
61  struct rtl_priv *rtlpriv = rtl_priv(hw);
62 
63  rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000));
64  rtl_write_dword(rtlpriv, REG_DBI_WDATA, value);
65  rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct);
66 }
67 
68 static void _rtl92de_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
69  u8 set_bits, u8 clear_bits)
70 {
71  struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
72  struct rtl_priv *rtlpriv = rtl_priv(hw);
73 
74  rtlpci->reg_bcn_ctrl_val |= set_bits;
75  rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
76  rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
77 }
78 
79 static void _rtl92de_stop_tx_beacon(struct ieee80211_hw *hw)
80 {
81  struct rtl_priv *rtlpriv = rtl_priv(hw);
82  u8 tmp1byte;
83 
84  tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
85  rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
86  rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
87  rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
88  tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
89  tmp1byte &= ~(BIT(0));
90  rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
91 }
92 
93 static void _rtl92de_resume_tx_beacon(struct ieee80211_hw *hw)
94 {
95  struct rtl_priv *rtlpriv = rtl_priv(hw);
96  u8 tmp1byte;
97 
98  tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
99  rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
100  rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
101  rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
102  tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
103  tmp1byte |= BIT(0);
104  rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
105 }
106 
107 static void _rtl92de_enable_bcn_sub_func(struct ieee80211_hw *hw)
108 {
109  _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1));
110 }
111 
112 static void _rtl92de_disable_bcn_sub_func(struct ieee80211_hw *hw)
113 {
114  _rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0);
115 }
116 
117 void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
118 {
119  struct rtl_priv *rtlpriv = rtl_priv(hw);
120  struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
121  struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
122 
123  switch (variable) {
124  case HW_VAR_RCR:
125  *((u32 *) (val)) = rtlpci->receive_config;
126  break;
127  case HW_VAR_RF_STATE:
128  *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
129  break;
130  case HW_VAR_FWLPS_RF_ON:{
131  enum rf_pwrstate rfState;
132  u32 val_rcr;
133 
134  rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
135  (u8 *) (&rfState));
136  if (rfState == ERFOFF) {
137  *((bool *) (val)) = true;
138  } else {
139  val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
140  val_rcr &= 0x00070000;
141  if (val_rcr)
142  *((bool *) (val)) = false;
143  else
144  *((bool *) (val)) = true;
145  }
146  break;
147  }
148  case HW_VAR_FW_PSMODE_STATUS:
149  *((bool *) (val)) = ppsc->fw_current_inpsmode;
150  break;
151  case HW_VAR_CORRECT_TSF:{
152  u64 tsf;
153  u32 *ptsf_low = (u32 *)&tsf;
154  u32 *ptsf_high = ((u32 *)&tsf) + 1;
155 
156  *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
157  *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
158  *((u64 *) (val)) = tsf;
159  break;
160  }
161  case HW_VAR_INT_MIGRATION:
162  *((bool *)(val)) = rtlpriv->dm.interrupt_migration;
163  break;
164  case HW_VAR_INT_AC:
165  *((bool *)(val)) = rtlpriv->dm.disable_tx_int;
166  break;
167  default:
168  RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
169  "switch case not processed\n");
170  break;
171  }
172 }
173 
174 void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
175 {
176  struct rtl_priv *rtlpriv = rtl_priv(hw);
177  struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
178  struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
179  struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
180  struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
181  struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
182  u8 idx;
183 
184  switch (variable) {
185  case HW_VAR_ETHER_ADDR:
186  for (idx = 0; idx < ETH_ALEN; idx++) {
187  rtl_write_byte(rtlpriv, (REG_MACID + idx),
188  val[idx]);
189  }
190  break;
191  case HW_VAR_BASIC_RATE: {
192  u16 rate_cfg = ((u16 *) val)[0];
193  u8 rate_index = 0;
194 
195  rate_cfg = rate_cfg & 0x15f;
196  if (mac->vendor == PEER_CISCO &&
197  ((rate_cfg & 0x150) == 0))
198  rate_cfg |= 0x01;
199  rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
200  rtl_write_byte(rtlpriv, REG_RRSR + 1,
201  (rate_cfg >> 8) & 0xff);
202  while (rate_cfg > 0x1) {
203  rate_cfg = (rate_cfg >> 1);
204  rate_index++;
205  }
206  if (rtlhal->fw_version > 0xe)
207  rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
208  rate_index);
209  break;
210  }
211  case HW_VAR_BSSID:
212  for (idx = 0; idx < ETH_ALEN; idx++) {
213  rtl_write_byte(rtlpriv, (REG_BSSID + idx),
214  val[idx]);
215  }
216  break;
217  case HW_VAR_SIFS:
218  rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
219  rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
220  rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
221  rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
222  if (!mac->ht_enable)
223  rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
224  0x0e0e);
225  else
226  rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
227  *((u16 *) val));
228  break;
229  case HW_VAR_SLOT_TIME: {
230  u8 e_aci;
231 
232  RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
233  "HW_VAR_SLOT_TIME %x\n", val[0]);
234  rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
235  for (e_aci = 0; e_aci < AC_MAX; e_aci++)
236  rtlpriv->cfg->ops->set_hw_reg(hw,
237  HW_VAR_AC_PARAM,
238  (&e_aci));
239  break;
240  }
241  case HW_VAR_ACK_PREAMBLE: {
242  u8 reg_tmp;
243  u8 short_preamble = (bool) (*val);
244 
245  reg_tmp = (mac->cur_40_prime_sc) << 5;
246  if (short_preamble)
247  reg_tmp |= 0x80;
248  rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
249  break;
250  }
251  case HW_VAR_AMPDU_MIN_SPACE: {
252  u8 min_spacing_to_set;
253  u8 sec_min_space;
254 
255  min_spacing_to_set = *val;
256  if (min_spacing_to_set <= 7) {
257  sec_min_space = 0;
258  if (min_spacing_to_set < sec_min_space)
259  min_spacing_to_set = sec_min_space;
260  mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
261  min_spacing_to_set);
262  *val = min_spacing_to_set;
263  RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
264  "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
265  mac->min_space_cfg);
266  rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
267  mac->min_space_cfg);
268  }
269  break;
270  }
271  case HW_VAR_SHORTGI_DENSITY: {
272  u8 density_to_set;
273 
274  density_to_set = *val;
275  mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
276  mac->min_space_cfg |= (density_to_set << 3);
277  RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
278  "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
279  mac->min_space_cfg);
280  rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
281  mac->min_space_cfg);
282  break;
283  }
284  case HW_VAR_AMPDU_FACTOR: {
285  u8 factor_toset;
286  u32 regtoSet;
287  u8 *ptmp_byte = NULL;
288  u8 index;
289 
290  if (rtlhal->macphymode == DUALMAC_DUALPHY)
291  regtoSet = 0xb9726641;
292  else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
293  regtoSet = 0x66626641;
294  else
295  regtoSet = 0xb972a841;
296  factor_toset = *val;
297  if (factor_toset <= 3) {
298  factor_toset = (1 << (factor_toset + 2));
299  if (factor_toset > 0xf)
300  factor_toset = 0xf;
301  for (index = 0; index < 4; index++) {
302  ptmp_byte = (u8 *) (&regtoSet) + index;
303  if ((*ptmp_byte & 0xf0) >
304  (factor_toset << 4))
305  *ptmp_byte = (*ptmp_byte & 0x0f)
306  | (factor_toset << 4);
307  if ((*ptmp_byte & 0x0f) > factor_toset)
308  *ptmp_byte = (*ptmp_byte & 0xf0)
309  | (factor_toset);
310  }
311  rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoSet);
312  RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
313  "Set HW_VAR_AMPDU_FACTOR: %#x\n",
314  factor_toset);
315  }
316  break;
317  }
318  case HW_VAR_AC_PARAM: {
319  u8 e_aci = *val;
320  rtl92d_dm_init_edca_turbo(hw);
321  if (rtlpci->acm_method != eAcmWay2_SW)
322  rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
323  &e_aci);
324  break;
325  }
326  case HW_VAR_ACM_CTRL: {
327  u8 e_aci = *val;
328  union aci_aifsn *p_aci_aifsn =
329  (union aci_aifsn *)(&(mac->ac[0].aifs));
330  u8 acm = p_aci_aifsn->f.acm;
331  u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
332 
333  acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
334  if (acm) {
335  switch (e_aci) {
336  case AC0_BE:
337  acm_ctrl |= ACMHW_BEQEN;
338  break;
339  case AC2_VI:
340  acm_ctrl |= ACMHW_VIQEN;
341  break;
342  case AC3_VO:
343  acm_ctrl |= ACMHW_VOQEN;
344  break;
345  default:
346  RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
347  "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
348  acm);
349  break;
350  }
351  } else {
352  switch (e_aci) {
353  case AC0_BE:
354  acm_ctrl &= (~ACMHW_BEQEN);
355  break;
356  case AC2_VI:
357  acm_ctrl &= (~ACMHW_VIQEN);
358  break;
359  case AC3_VO:
360  acm_ctrl &= (~ACMHW_VOQEN);
361  break;
362  default:
363  RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
364  "switch case not processed\n");
365  break;
366  }
367  }
368  RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
369  "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
370  acm_ctrl);
371  rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
372  break;
373  }
374  case HW_VAR_RCR:
375  rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
376  rtlpci->receive_config = ((u32 *) (val))[0];
377  break;
378  case HW_VAR_RETRY_LIMIT: {
379  u8 retry_limit = val[0];
380 
381  rtl_write_word(rtlpriv, REG_RL,
382  retry_limit << RETRY_LIMIT_SHORT_SHIFT |
383  retry_limit << RETRY_LIMIT_LONG_SHIFT);
384  break;
385  }
386  case HW_VAR_DUAL_TSF_RST:
387  rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
388  break;
389  case HW_VAR_EFUSE_BYTES:
390  rtlefuse->efuse_usedbytes = *((u16 *) val);
391  break;
392  case HW_VAR_EFUSE_USAGE:
393  rtlefuse->efuse_usedpercentage = *val;
394  break;
395  case HW_VAR_IO_CMD:
396  rtl92d_phy_set_io_cmd(hw, (*(enum io_type *)val));
397  break;
398  case HW_VAR_WPA_CONFIG:
399  rtl_write_byte(rtlpriv, REG_SECCFG, *val);
400  break;
401  case HW_VAR_SET_RPWM:
402  rtl92d_fill_h2c_cmd(hw, H2C_PWRM, 1, (val));
403  break;
404  case HW_VAR_H2C_FW_PWRMODE:
405  break;
406  case HW_VAR_FW_PSMODE_STATUS:
407  ppsc->fw_current_inpsmode = *((bool *) val);
408  break;
409  case HW_VAR_H2C_FW_JOINBSSRPT: {
410  u8 mstatus = (*val);
411  u8 tmp_regcr, tmp_reg422;
412  bool recover = false;
413 
414  if (mstatus == RT_MEDIA_CONNECT) {
415  rtlpriv->cfg->ops->set_hw_reg(hw,
416  HW_VAR_AID, NULL);
417  tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
418  rtl_write_byte(rtlpriv, REG_CR + 1,
419  (tmp_regcr | BIT(0)));
420  _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
421  _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
422  tmp_reg422 = rtl_read_byte(rtlpriv,
423  REG_FWHW_TXQ_CTRL + 2);
424  if (tmp_reg422 & BIT(6))
425  recover = true;
426  rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
427  tmp_reg422 & (~BIT(6)));
428  rtl92d_set_fw_rsvdpagepkt(hw, 0);
429  _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
430  _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
431  if (recover)
432  rtl_write_byte(rtlpriv,
433  REG_FWHW_TXQ_CTRL + 2,
434  tmp_reg422);
435  rtl_write_byte(rtlpriv, REG_CR + 1,
436  (tmp_regcr & ~(BIT(0))));
437  }
438  rtl92d_set_fw_joinbss_report_cmd(hw, (*val));
439  break;
440  }
441  case HW_VAR_AID: {
442  u16 u2btmp;
443  u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
444  u2btmp &= 0xC000;
445  rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
446  mac->assoc_id));
447  break;
448  }
449  case HW_VAR_CORRECT_TSF: {
450  u8 btype_ibss = val[0];
451 
452  if (btype_ibss)
453  _rtl92de_stop_tx_beacon(hw);
454  _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
455  rtl_write_dword(rtlpriv, REG_TSFTR,
456  (u32) (mac->tsf & 0xffffffff));
457  rtl_write_dword(rtlpriv, REG_TSFTR + 4,
458  (u32) ((mac->tsf >> 32) & 0xffffffff));
459  _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
460  if (btype_ibss)
461  _rtl92de_resume_tx_beacon(hw);
462 
463  break;
464  }
465  case HW_VAR_INT_MIGRATION: {
466  bool int_migration = *(bool *) (val);
467 
468  if (int_migration) {
469  /* Set interrupt migration timer and
470  * corresponding Tx/Rx counter.
471  * timer 25ns*0xfa0=100us for 0xf packets.
472  * 0x306:Rx, 0x307:Tx */
473  rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0);
474  rtlpriv->dm.interrupt_migration = int_migration;
475  } else {
476  /* Reset all interrupt migration settings. */
477  rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
478  rtlpriv->dm.interrupt_migration = int_migration;
479  }
480  break;
481  }
482  case HW_VAR_INT_AC: {
483  bool disable_ac_int = *((bool *) val);
484 
485  /* Disable four ACs interrupts. */
486  if (disable_ac_int) {
487  /* Disable VO, VI, BE and BK four AC interrupts
488  * to gain more efficient CPU utilization.
489  * When extremely highly Rx OK occurs,
490  * we will disable Tx interrupts.
491  */
492  rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
493  RT_AC_INT_MASKS);
494  rtlpriv->dm.disable_tx_int = disable_ac_int;
495  /* Enable four ACs interrupts. */
496  } else {
497  rtlpriv->cfg->ops->update_interrupt_mask(hw,
498  RT_AC_INT_MASKS, 0);
499  rtlpriv->dm.disable_tx_int = disable_ac_int;
500  }
501  break;
502  }
503  default:
504  RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
505  "switch case not processed\n");
506  break;
507  }
508 }
509 
510 static bool _rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
511 {
512  struct rtl_priv *rtlpriv = rtl_priv(hw);
513  bool status = true;
514  long count = 0;
515  u32 value = _LLT_INIT_ADDR(address) |
516  _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
517 
518  rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
519  do {
520  value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
521  if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
522  break;
523  if (count > POLLING_LLT_THRESHOLD) {
524  RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
525  "Failed to polling write LLT done at address %d!\n",
526  address);
527  status = false;
528  break;
529  }
530  } while (++count);
531  return status;
532 }
533 
534 static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw)
535 {
536  struct rtl_priv *rtlpriv = rtl_priv(hw);
537  unsigned short i;
538  u8 txpktbuf_bndy;
539  u8 maxPage;
540  bool status;
541  u32 value32; /* High+low page number */
542  u8 value8; /* normal page number */
543 
544  if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
545  maxPage = 255;
546  txpktbuf_bndy = 246;
547  value8 = 0;
548  value32 = 0x80bf0d29;
549  } else if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
550  maxPage = 127;
551  txpktbuf_bndy = 123;
552  value8 = 0;
553  value32 = 0x80750005;
554  }
555 
556  /* Set reserved page for each queue */
557  /* 11. RQPN 0x200[31:0] = 0x80BD1C1C */
558  /* load RQPN */
559  rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
560  rtl_write_dword(rtlpriv, REG_RQPN, value32);
561 
562  /* 12. TXRKTBUG_PG_BNDY 0x114[31:0] = 0x27FF00F6 */
563  /* TXRKTBUG_PG_BNDY */
564  rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
565  (rtl_read_word(rtlpriv, REG_TRXFF_BNDY + 2) << 16 |
566  txpktbuf_bndy));
567 
568  /* 13. TDECTRL[15:8] 0x209[7:0] = 0xF6 */
569  /* Beacon Head for TXDMA */
570  rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
571 
572  /* 14. BCNQ_PGBNDY 0x424[7:0] = 0xF6 */
573  /* BCNQ_PGBNDY */
574  rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
575  rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
576 
577  /* 15. WMAC_LBK_BF_HD 0x45D[7:0] = 0xF6 */
578  /* WMAC_LBK_BF_HD */
579  rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
580 
581  /* Set Tx/Rx page size (Tx must be 128 Bytes, */
582  /* Rx can be 64,128,256,512,1024 bytes) */
583  /* 16. PBP [7:0] = 0x11 */
584  /* TRX page size */
585  rtl_write_byte(rtlpriv, REG_PBP, 0x11);
586 
587  /* 17. DRV_INFO_SZ = 0x04 */
588  rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
589 
590  /* 18. LLT_table_init(Adapter); */
591  for (i = 0; i < (txpktbuf_bndy - 1); i++) {
592  status = _rtl92de_llt_write(hw, i, i + 1);
593  if (true != status)
594  return status;
595  }
596 
597  /* end of list */
598  status = _rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
599  if (true != status)
600  return status;
601 
602  /* Make the other pages as ring buffer */
603  /* This ring buffer is used as beacon buffer if we */
604  /* config this MAC as two MAC transfer. */
605  /* Otherwise used as local loopback buffer. */
606  for (i = txpktbuf_bndy; i < maxPage; i++) {
607  status = _rtl92de_llt_write(hw, i, (i + 1));
608  if (true != status)
609  return status;
610  }
611 
612  /* Let last entry point to the start entry of ring buffer */
613  status = _rtl92de_llt_write(hw, maxPage, txpktbuf_bndy);
614  if (true != status)
615  return status;
616 
617  return true;
618 }
619 
620 static void _rtl92de_gen_refresh_led_state(struct ieee80211_hw *hw)
621 {
622  struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
623  struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
624  struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
625  struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
626 
627  if (rtlpci->up_first_time)
628  return;
629  if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
630  rtl92de_sw_led_on(hw, pLed0);
631  else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
632  rtl92de_sw_led_on(hw, pLed0);
633  else
634  rtl92de_sw_led_off(hw, pLed0);
635 }
636 
637 static bool _rtl92de_init_mac(struct ieee80211_hw *hw)
638 {
639  struct rtl_priv *rtlpriv = rtl_priv(hw);
640  struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
641  unsigned char bytetmp;
642  unsigned short wordtmp;
643  u16 retry;
644 
645  rtl92d_phy_set_poweron(hw);
646  /* Add for resume sequence of power domain according
647  * to power document V11. Chapter V.11.... */
648  /* 0. RSV_CTRL 0x1C[7:0] = 0x00 */
649  /* unlock ISO/CLK/Power control register */
650  rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
651  rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x05);
652 
653  /* 1. AFE_XTAL_CTRL [7:0] = 0x0F enable XTAL */
654  /* 2. SPS0_CTRL 0x11[7:0] = 0x2b enable SPS into PWM mode */
655  /* 3. delay (1ms) this is not necessary when initially power on */
656 
657  /* C. Resume Sequence */
658  /* a. SPS0_CTRL 0x11[7:0] = 0x2b */
659  rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
660 
661  /* b. AFE_XTAL_CTRL [7:0] = 0x0F */
662  rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
663 
664  /* c. DRV runs power on init flow */
665 
666  /* auto enable WLAN */
667  /* 4. APS_FSMCO 0x04[8] = 1; wait till 0x04[8] = 0 */
668  /* Power On Reset for MAC Block */
669  bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
670  udelay(2);
671  rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
672  udelay(2);
673 
674  /* 5. Wait while 0x04[8] == 0 goto 2, otherwise goto 1 */
675  bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
676  udelay(50);
677  retry = 0;
678  while ((bytetmp & BIT(0)) && retry < 1000) {
679  retry++;
680  bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
681  udelay(50);
682  }
683 
684  /* Enable Radio off, GPIO, and LED function */
685  /* 6. APS_FSMCO 0x04[15:0] = 0x0012 when enable HWPDN */
686  rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
687 
688  /* release RF digital isolation */
689  /* 7. SYS_ISO_CTRL 0x01[1] = 0x0; */
690  /*Set REG_SYS_ISO_CTRL 0x1=0x82 to prevent wake# problem. */
691  rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
692  udelay(2);
693 
694  /* make sure that BB reset OK. */
695  /* rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); */
696 
697  /* Disable REG_CR before enable it to assure reset */
698  rtl_write_word(rtlpriv, REG_CR, 0x0);
699 
700  /* Release MAC IO register reset */
701  rtl_write_word(rtlpriv, REG_CR, 0x2ff);
702 
703  /* clear stopping tx/rx dma */
704  rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x0);
705 
706  /* rtl_write_word(rtlpriv,REG_CR+2, 0x2); */
707 
708  /* System init */
709  /* 18. LLT_table_init(Adapter); */
710  if (!_rtl92de_llt_table_init(hw))
711  return false;
712 
713  /* Clear interrupt and enable interrupt */
714  /* 19. HISR 0x124[31:0] = 0xffffffff; */
715  /* HISRE 0x12C[7:0] = 0xFF */
716  rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
717  rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
718 
719  /* 20. HIMR 0x120[31:0] |= [enable INT mask bit map]; */
720  /* 21. HIMRE 0x128[7:0] = [enable INT mask bit map] */
721  /* The IMR should be enabled later after all init sequence
722  * is finished. */
723 
724  /* 22. PCIE configuration space configuration */
725  /* 23. Ensure PCIe Device 0x80[15:0] = 0x0143 (ASPM+CLKREQ), */
726  /* and PCIe gated clock function is enabled. */
727  /* PCIE configuration space will be written after
728  * all init sequence.(Or by BIOS) */
729 
730  rtl92d_phy_config_maccoexist_rfpage(hw);
731 
732  /* THe below section is not related to power document Vxx . */
733  /* This is only useful for driver and OS setting. */
734  /* -------------------Software Relative Setting---------------------- */
735  wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
736  wordtmp &= 0xf;
737  wordtmp |= 0xF771;
738  rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
739 
740  /* Reported Tx status from HW for rate adaptive. */
741  /* This should be realtive to power on step 14. But in document V11 */
742  /* still not contain the description.!!! */
743  rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
744 
745  /* Set Tx/Rx page size (Tx must be 128 Bytes,
746  * Rx can be 64,128,256,512,1024 bytes) */
747  /* rtl_write_byte(rtlpriv,REG_PBP, 0x11); */
748 
749  /* Set RCR register */
750  rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
751  /* rtl_write_byte(rtlpriv,REG_RX_DRVINFO_SZ, 4); */
752 
753  /* Set TCR register */
754  rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
755 
756  /* disable earlymode */
757  rtl_write_byte(rtlpriv, 0x4d0, 0x0);
758 
759  /* Set TX/RX descriptor physical address(from OS API). */
760  rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
761  rtlpci->tx_ring[BEACON_QUEUE].dma);
762  rtl_write_dword(rtlpriv, REG_MGQ_DESA, rtlpci->tx_ring[MGNT_QUEUE].dma);
763  rtl_write_dword(rtlpriv, REG_VOQ_DESA, rtlpci->tx_ring[VO_QUEUE].dma);
764  rtl_write_dword(rtlpriv, REG_VIQ_DESA, rtlpci->tx_ring[VI_QUEUE].dma);
765  rtl_write_dword(rtlpriv, REG_BEQ_DESA, rtlpci->tx_ring[BE_QUEUE].dma);
766  rtl_write_dword(rtlpriv, REG_BKQ_DESA, rtlpci->tx_ring[BK_QUEUE].dma);
767  rtl_write_dword(rtlpriv, REG_HQ_DESA, rtlpci->tx_ring[HIGH_QUEUE].dma);
768  /* Set RX Desc Address */
769  rtl_write_dword(rtlpriv, REG_RX_DESA,
770  rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
771 
772  /* if we want to support 64 bit DMA, we should set it here,
773  * but now we do not support 64 bit DMA*/
774 
775  rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x33);
776 
777  /* Reset interrupt migration setting when initialization */
778  rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
779 
780  /* Reconsider when to do this operation after asking HWSD. */
781  bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
782  rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
783  do {
784  retry++;
785  bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
786  } while ((retry < 200) && !(bytetmp & BIT(7)));
787 
788  /* After MACIO reset,we must refresh LED state. */
789  _rtl92de_gen_refresh_led_state(hw);
790 
791  /* Reset H2C protection register */
792  rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
793 
794  return true;
795 }
796 
797 static void _rtl92de_hw_configure(struct ieee80211_hw *hw)
798 {
799  struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
800  struct rtl_priv *rtlpriv = rtl_priv(hw);
801  struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
802  u8 reg_bw_opmode = BW_OPMODE_20MHZ;
803  u32 reg_rrsr;
804 
805  reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
806  rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
807  rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
808  rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
809  rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
810  rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
811  rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
812  rtl_write_word(rtlpriv, REG_RL, 0x0707);
813  rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
814  rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
815  rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
816  rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
817  rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
818  rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
819  /* Aggregation threshold */
820  if (rtlhal->macphymode == DUALMAC_DUALPHY)
821  rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641);
822  else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
823  rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641);
824  else
825  rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
826  rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
827  rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
828  rtlpci->reg_bcn_ctrl_val = 0x1f;
829  rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
830  rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
831  rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
832  rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
833  rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
834  /* For throughput */
835  rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x6666);
836  /* ACKTO for IOT issue. */
837  rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
838  /* Set Spec SIFS (used in NAV) */
839  rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
840  rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
841  /* Set SIFS for CCK */
842  rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
843  /* Set SIFS for OFDM */
844  rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
845  /* Set Multicast Address. */
846  rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
847  rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
848  switch (rtlpriv->phy.rf_type) {
849  case RF_1T2R:
850  case RF_1T1R:
851  rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
852  break;
853  case RF_2T2R:
854  case RF_2T2R_GREEN:
855  rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
856  break;
857  }
858 }
859 
860 static void _rtl92de_enable_aspm_back_door(struct ieee80211_hw *hw)
861 {
862  struct rtl_priv *rtlpriv = rtl_priv(hw);
863  struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
864 
865  rtl_write_byte(rtlpriv, 0x34b, 0x93);
866  rtl_write_word(rtlpriv, 0x350, 0x870c);
867  rtl_write_byte(rtlpriv, 0x352, 0x1);
868  if (ppsc->support_backdoor)
869  rtl_write_byte(rtlpriv, 0x349, 0x1b);
870  else
871  rtl_write_byte(rtlpriv, 0x349, 0x03);
872  rtl_write_word(rtlpriv, 0x350, 0x2718);
873  rtl_write_byte(rtlpriv, 0x352, 0x1);
874 }
875 
876 void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw)
877 {
878  struct rtl_priv *rtlpriv = rtl_priv(hw);
879  u8 sec_reg_value;
880 
881  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
882  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
883  rtlpriv->sec.pairwise_enc_algorithm,
884  rtlpriv->sec.group_enc_algorithm);
885  if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
886  RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
887  "not open hw encryption\n");
888  return;
889  }
890  sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
891  if (rtlpriv->sec.use_defaultkey) {
892  sec_reg_value |= SCR_TXUSEDK;
893  sec_reg_value |= SCR_RXUSEDK;
894  }
895  sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
896  rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
897  RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
898  "The SECR-value %x\n", sec_reg_value);
899  rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
900 }
901 
902 int rtl92de_hw_init(struct ieee80211_hw *hw)
903 {
904  struct rtl_priv *rtlpriv = rtl_priv(hw);
905  struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
906  struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
907  struct rtl_phy *rtlphy = &(rtlpriv->phy);
908  struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
909  struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
910  bool rtstatus = true;
911  u8 tmp_u1b;
912  int i;
913  int err;
914  unsigned long flags;
915 
916  rtlpci->being_init_adapter = true;
917  rtlpci->init_ready = false;
918  spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags);
919  /* we should do iqk after disable/enable */
920  rtl92d_phy_reset_iqk_result(hw);
921  /* rtlpriv->intf_ops->disable_aspm(hw); */
922  rtstatus = _rtl92de_init_mac(hw);
923  if (!rtstatus) {
924  RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
925  err = 1;
926  spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
927  return err;
928  }
929  err = rtl92d_download_fw(hw);
930  spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
931  if (err) {
932  RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
933  "Failed to download FW. Init HW without FW..\n");
934  return 1;
935  }
936  rtlhal->last_hmeboxnum = 0;
937  rtlpriv->psc.fw_current_inpsmode = false;
938 
939  tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
940  tmp_u1b = tmp_u1b | 0x30;
941  rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
942 
943  if (rtlhal->earlymode_enable) {
944  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
945  "EarlyMode Enabled!!!\n");
946 
947  tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0);
948  tmp_u1b = tmp_u1b | 0x1f;
949  rtl_write_byte(rtlpriv, 0x4d0, tmp_u1b);
950 
951  rtl_write_byte(rtlpriv, 0x4d3, 0x80);
952 
953  tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
954  tmp_u1b = tmp_u1b | 0x40;
955  rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
956  }
957 
958  if (mac->rdg_en) {
959  rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff);
960  rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);
961  rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);
962  }
963 
964  rtl92d_phy_mac_config(hw);
965  /* because last function modify RCR, so we update
966  * rcr var here, or TP will unstable for receive_config
967  * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
968  * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
969  rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
970  rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
971 
972  rtl92d_phy_bb_config(hw);
973 
974  rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
975  /* set before initialize RF */
976  rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
977 
978  /* config RF */
979  rtl92d_phy_rf_config(hw);
980 
981  /* After read predefined TXT, we must set BB/MAC/RF
982  * register as our requirement */
983  /* After load BB,RF params,we need do more for 92D. */
984  rtl92d_update_bbrf_configuration(hw);
985  /* set default value after initialize RF, */
986  rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
987  rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
988  RF_CHNLBW, BRFREGOFFSETMASK);
989  rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
990  RF_CHNLBW, BRFREGOFFSETMASK);
991 
992  /*---- Set CCK and OFDM Block "ON"----*/
993  if (rtlhal->current_bandtype == BAND_ON_2_4G)
994  rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
995  rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
996  if (rtlhal->interfaceindex == 0) {
997  /* RFPGA0_ANALOGPARAMETER2: cck clock select,
998  * set to 20MHz by default */
999  rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1000  BIT(11), 3);
1001  } else {
1002  /* Mac1 */
1003  rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(11) |
1004  BIT(10), 3);
1005  }
1006 
1007  _rtl92de_hw_configure(hw);
1008 
1009  /* reset hw sec */
1010  rtl_cam_reset_all_entry(hw);
1011  rtl92de_enable_hw_security_config(hw);
1012 
1013  /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1014  /* TX power index for different rate set. */
1015  rtl92d_phy_get_hw_reg_originalvalue(hw);
1016  rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
1017 
1018  ppsc->rfpwr_state = ERFON;
1019 
1020  rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1021 
1022  _rtl92de_enable_aspm_back_door(hw);
1023  /* rtlpriv->intf_ops->enable_aspm(hw); */
1024 
1025  rtl92d_dm_init(hw);
1026  rtlpci->being_init_adapter = false;
1027 
1028  if (ppsc->rfpwr_state == ERFON) {
1029  rtl92d_phy_lc_calibrate(hw);
1030  /* 5G and 2.4G must wait sometime to let RF LO ready */
1031  if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1032  u32 tmp_rega;
1033  for (i = 0; i < 10000; i++) {
1034  udelay(MAX_STALL_TIME);
1035 
1036  tmp_rega = rtl_get_rfreg(hw,
1037  (enum radio_path)RF90_PATH_A,
1038  0x2a, BMASKDWORD);
1039 
1040  if (((tmp_rega & BIT(11)) == BIT(11)))
1041  break;
1042  }
1043  /* check that loop was successful. If not, exit now */
1044  if (i == 10000) {
1045  rtlpci->init_ready = false;
1046  return 1;
1047  }
1048  }
1049  }
1050  rtlpci->init_ready = true;
1051  return err;
1052 }
1053 
1054 static enum version_8192d _rtl92de_read_chip_version(struct ieee80211_hw *hw)
1055 {
1056  struct rtl_priv *rtlpriv = rtl_priv(hw);
1057  enum version_8192d version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1058  u32 value32;
1059 
1060  value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1061  if (!(value32 & 0x000f0000)) {
1062  version = VERSION_TEST_CHIP_92D_SINGLEPHY;
1063  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "TEST CHIP!!!\n");
1064  } else {
1065  version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1066  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Normal CHIP!!!\n");
1067  }
1068  return version;
1069 }
1070 
1071 static int _rtl92de_set_media_status(struct ieee80211_hw *hw,
1072  enum nl80211_iftype type)
1073 {
1074  struct rtl_priv *rtlpriv = rtl_priv(hw);
1075  u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1076  enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1077  u8 bcnfunc_enable;
1078 
1079  bt_msr &= 0xfc;
1080 
1081  if (type == NL80211_IFTYPE_UNSPECIFIED ||
1082  type == NL80211_IFTYPE_STATION) {
1083  _rtl92de_stop_tx_beacon(hw);
1084  _rtl92de_enable_bcn_sub_func(hw);
1085  } else if (type == NL80211_IFTYPE_ADHOC ||
1086  type == NL80211_IFTYPE_AP) {
1087  _rtl92de_resume_tx_beacon(hw);
1088  _rtl92de_disable_bcn_sub_func(hw);
1089  } else {
1090  RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1091  "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1092  type);
1093  }
1094  bcnfunc_enable = rtl_read_byte(rtlpriv, REG_BCN_CTRL);
1095  switch (type) {
1096  case NL80211_IFTYPE_UNSPECIFIED:
1097  bt_msr |= MSR_NOLINK;
1098  ledaction = LED_CTL_LINK;
1099  bcnfunc_enable &= 0xF7;
1100  RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1101  "Set Network type to NO LINK!\n");
1102  break;
1103  case NL80211_IFTYPE_ADHOC:
1104  bt_msr |= MSR_ADHOC;
1105  bcnfunc_enable |= 0x08;
1106  RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1107  "Set Network type to Ad Hoc!\n");
1108  break;
1109  case NL80211_IFTYPE_STATION:
1110  bt_msr |= MSR_INFRA;
1111  ledaction = LED_CTL_LINK;
1112  bcnfunc_enable &= 0xF7;
1113  RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1114  "Set Network type to STA!\n");
1115  break;
1116  case NL80211_IFTYPE_AP:
1117  bt_msr |= MSR_AP;
1118  bcnfunc_enable |= 0x08;
1119  RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1120  "Set Network type to AP!\n");
1121  break;
1122  default:
1123  RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1124  "Network type %d not supported!\n", type);
1125  return 1;
1126  break;
1127 
1128  }
1129  rtl_write_byte(rtlpriv, REG_CR + 2, bt_msr);
1130  rtlpriv->cfg->ops->led_control(hw, ledaction);
1131  if ((bt_msr & 0xfc) == MSR_AP)
1132  rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1133  else
1134  rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1135  return 0;
1136 }
1137 
1138 void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1139 {
1140  struct rtl_priv *rtlpriv = rtl_priv(hw);
1141  struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1142  u32 reg_rcr = rtlpci->receive_config;
1143 
1144  if (rtlpriv->psc.rfpwr_state != ERFON)
1145  return;
1146  if (check_bssid) {
1147  reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1148  rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1149  _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
1150  } else if (!check_bssid) {
1151  reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1152  _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
1153  rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1154  }
1155 }
1156 
1157 int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1158 {
1159  struct rtl_priv *rtlpriv = rtl_priv(hw);
1160 
1161  if (_rtl92de_set_media_status(hw, type))
1162  return -EOPNOTSUPP;
1163 
1164  /* check bssid */
1165  if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1166  if (type != NL80211_IFTYPE_AP)
1167  rtl92de_set_check_bssid(hw, true);
1168  } else {
1169  rtl92de_set_check_bssid(hw, false);
1170  }
1171  return 0;
1172 }
1173 
1174 /* do iqk or reload iqk */
1175 /* windows just rtl92d_phy_reload_iqk_setting in set channel,
1176  * but it's very strict for time sequence so we add
1177  * rtl92d_phy_reload_iqk_setting here */
1178 void rtl92d_linked_set_reg(struct ieee80211_hw *hw)
1179 {
1180  struct rtl_priv *rtlpriv = rtl_priv(hw);
1181  struct rtl_phy *rtlphy = &(rtlpriv->phy);
1182  u8 indexforchannel;
1183  u8 channel = rtlphy->current_channel;
1184 
1185  indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
1186  if (!rtlphy->iqk_matrix_regsetting[indexforchannel].iqk_done) {
1187  RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG,
1188  "Do IQK for channel:%d\n", channel);
1189  rtl92d_phy_iq_calibrate(hw);
1190  }
1191 }
1192 
1193 /* don't set REG_EDCA_BE_PARAM here because
1194  * mac80211 will send pkt when scan */
1195 void rtl92de_set_qos(struct ieee80211_hw *hw, int aci)
1196 {
1197  struct rtl_priv *rtlpriv = rtl_priv(hw);
1198  rtl92d_dm_init_edca_turbo(hw);
1199  return;
1200  switch (aci) {
1201  case AC1_BK:
1202  rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1203  break;
1204  case AC0_BE:
1205  break;
1206  case AC2_VI:
1207  rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1208  break;
1209  case AC3_VO:
1210  rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1211  break;
1212  default:
1213  RT_ASSERT(false, "invalid aci: %d !\n", aci);
1214  break;
1215  }
1216 }
1217 
1218 void rtl92de_enable_interrupt(struct ieee80211_hw *hw)
1219 {
1220  struct rtl_priv *rtlpriv = rtl_priv(hw);
1221  struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1222 
1223  rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1224  rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1225 }
1226 
1227 void rtl92de_disable_interrupt(struct ieee80211_hw *hw)
1228 {
1229  struct rtl_priv *rtlpriv = rtl_priv(hw);
1230  struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1231 
1232  rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1233  rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1234  synchronize_irq(rtlpci->pdev->irq);
1235 }
1236 
1237 static void _rtl92de_poweroff_adapter(struct ieee80211_hw *hw)
1238 {
1239  struct rtl_priv *rtlpriv = rtl_priv(hw);
1240  u8 u1b_tmp;
1241  unsigned long flags;
1242 
1243  rtlpriv->intf_ops->enable_aspm(hw);
1244  rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1245  rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(3), 0);
1246  rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(15), 0);
1247 
1248  /* 0x20:value 05-->04 */
1249  rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1250 
1251  /* ==== Reset digital sequence ====== */
1252  rtl92d_firmware_selfreset(hw);
1253 
1254  /* f. SYS_FUNC_EN 0x03[7:0]=0x51 reset MCU, MAC register, DCORE */
1255  rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1256 
1257  /* g. MCUFWDL 0x80[1:0]=0 reset MCU ready status */
1258  rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1259 
1260  /* ==== Pull GPIO PIN to balance level and LED control ====== */
1261 
1262  /* h. GPIO_PIN_CTRL 0x44[31:0]=0x000 */
1263  rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1264 
1265  /* i. Value = GPIO_PIN_CTRL[7:0] */
1266  u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1267 
1268  /* j. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); */
1269  /* write external PIN level */
1270  rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL,
1271  0x00FF0000 | (u1b_tmp << 8));
1272 
1273  /* k. GPIO_MUXCFG 0x42 [15:0] = 0x0780 */
1274  rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1275 
1276  /* l. LEDCFG 0x4C[15:0] = 0x8080 */
1277  rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1278 
1279  /* ==== Disable analog sequence === */
1280 
1281  /* m. AFE_PLL_CTRL[7:0] = 0x80 disable PLL */
1282  rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1283 
1284  /* n. SPS0_CTRL 0x11[7:0] = 0x22 enter PFM mode */
1285  rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1286 
1287  /* o. AFE_XTAL_CTRL 0x24[7:0] = 0x0E disable XTAL, if No BT COEX */
1288  rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1289 
1290  /* p. RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */
1291  rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1292 
1293  /* ==== interface into suspend === */
1294 
1295  /* q. APS_FSMCO[15:8] = 0x58 PCIe suspend mode */
1296  /* According to power document V11, we need to set this */
1297  /* value as 0x18. Otherwise, we may not L0s sometimes. */
1298  /* This indluences power consumption. Bases on SD1's test, */
1299  /* set as 0x00 do not affect power current. And if it */
1300  /* is set as 0x18, they had ever met auto load fail problem. */
1301  rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1302 
1303  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1304  "In PowerOff,reg0x%x=%X\n",
1305  REG_SPS0_CTRL, rtl_read_byte(rtlpriv, REG_SPS0_CTRL));
1306  /* r. Note: for PCIe interface, PON will not turn */
1307  /* off m-bias and BandGap in PCIe suspend mode. */
1308 
1309  /* 0x17[7] 1b': power off in process 0b' : power off over */
1310  if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
1311  spin_lock_irqsave(&globalmutex_power, flags);
1312  u1b_tmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
1313  u1b_tmp &= (~BIT(7));
1314  rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1b_tmp);
1315  spin_unlock_irqrestore(&globalmutex_power, flags);
1316  }
1317 
1318  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<=======\n");
1319 }
1320 
1321 void rtl92de_card_disable(struct ieee80211_hw *hw)
1322 {
1323  struct rtl_priv *rtlpriv = rtl_priv(hw);
1324  struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1325  struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1326  struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1327  enum nl80211_iftype opmode;
1328 
1329  mac->link_state = MAC80211_NOLINK;
1330  opmode = NL80211_IFTYPE_UNSPECIFIED;
1331  _rtl92de_set_media_status(hw, opmode);
1332 
1333  if (rtlpci->driver_is_goingto_unload ||
1334  ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1335  rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1336  RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1337  /* Power sequence for each MAC. */
1338  /* a. stop tx DMA */
1339  /* b. close RF */
1340  /* c. clear rx buf */
1341  /* d. stop rx DMA */
1342  /* e. reset MAC */
1343 
1344  /* a. stop tx DMA */
1345  rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1346  udelay(50);
1347 
1348  /* b. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
1349 
1350  /* c. ========RF OFF sequence========== */
1351  /* 0x88c[23:20] = 0xf. */
1352  rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1353  rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00);
1354 
1355  /* APSD_CTRL 0x600[7:0] = 0x40 */
1356  rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1357 
1358  /* Close antenna 0,0xc04,0xd04 */
1359  rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0);
1360  rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0);
1361 
1362  /* SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB state machine */
1363  rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1364 
1365  /* Mac0 can not do Global reset. Mac1 can do. */
1366  /* SYS_FUNC_EN 0x02[7:0] = 0xE0 reset BB state machine */
1367  if (rtlpriv->rtlhal.interfaceindex == 1)
1368  rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1369  udelay(50);
1370 
1371  /* d. stop tx/rx dma before disable REG_CR (0x100) to fix */
1372  /* dma hang issue when disable/enable device. */
1373  rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
1374  udelay(50);
1375  rtl_write_byte(rtlpriv, REG_CR, 0x0);
1376  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==> Do power off.......\n");
1377  if (rtl92d_phy_check_poweroff(hw))
1378  _rtl92de_poweroff_adapter(hw);
1379  return;
1380 }
1381 
1382 void rtl92de_interrupt_recognized(struct ieee80211_hw *hw,
1383  u32 *p_inta, u32 *p_intb)
1384 {
1385  struct rtl_priv *rtlpriv = rtl_priv(hw);
1386  struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1387 
1388  *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1389  rtl_write_dword(rtlpriv, ISR, *p_inta);
1390 
1391  /*
1392  * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1393  * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1394  */
1395 }
1396 
1397 void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw)
1398 {
1399  struct rtl_priv *rtlpriv = rtl_priv(hw);
1400  struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1401  u16 bcn_interval, atim_window;
1402 
1403  bcn_interval = mac->beacon_interval;
1404  atim_window = 2;
1405  /*rtl92de_disable_interrupt(hw); */
1406  rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1407  rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1408  rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1409  rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20);
1410  if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
1411  rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30);
1412  else
1413  rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20);
1414  rtl_write_byte(rtlpriv, 0x606, 0x30);
1415 }
1416 
1417 void rtl92de_set_beacon_interval(struct ieee80211_hw *hw)
1418 {
1419  struct rtl_priv *rtlpriv = rtl_priv(hw);
1420  struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1421  u16 bcn_interval = mac->beacon_interval;
1422 
1423  RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1424  "beacon_interval:%d\n", bcn_interval);
1425  /* rtl92de_disable_interrupt(hw); */
1426  rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1427  /* rtl92de_enable_interrupt(hw); */
1428 }
1429 
1430 void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw,
1431  u32 add_msr, u32 rm_msr)
1432 {
1433  struct rtl_priv *rtlpriv = rtl_priv(hw);
1434  struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1435 
1436  RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1437  add_msr, rm_msr);
1438  if (add_msr)
1439  rtlpci->irq_mask[0] |= add_msr;
1440  if (rm_msr)
1441  rtlpci->irq_mask[0] &= (~rm_msr);
1442  rtl92de_disable_interrupt(hw);
1443  rtl92de_enable_interrupt(hw);
1444 }
1445 
1446 static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo,
1447  u8 *rom_content, bool autoLoadfail)
1448 {
1449  u32 rfpath, eeaddr, group, offset1, offset2;
1450  u8 i;
1451 
1452  memset(pwrinfo, 0, sizeof(struct txpower_info));
1453  if (autoLoadfail) {
1454  for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1455  for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1456  if (group < CHANNEL_GROUP_MAX_2G) {
1457  pwrinfo->cck_index[rfpath][group] =
1458  EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1459  pwrinfo->ht40_1sindex[rfpath][group] =
1460  EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1461  } else {
1462  pwrinfo->ht40_1sindex[rfpath][group] =
1463  EEPROM_DEFAULT_TXPOWERLEVEL_5G;
1464  }
1465  pwrinfo->ht40_2sindexdiff[rfpath][group] =
1466  EEPROM_DEFAULT_HT40_2SDIFF;
1467  pwrinfo->ht20indexdiff[rfpath][group] =
1468  EEPROM_DEFAULT_HT20_DIFF;
1469  pwrinfo->ofdmindexdiff[rfpath][group] =
1470  EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1471  pwrinfo->ht40maxoffset[rfpath][group] =
1472  EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1473  pwrinfo->ht20maxoffset[rfpath][group] =
1474  EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1475  }
1476  }
1477  for (i = 0; i < 3; i++) {
1478  pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1479  pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1480  }
1481  return;
1482  }
1483 
1484  /* Maybe autoload OK,buf the tx power index value is not filled.
1485  * If we find it, we set it to default value. */
1486  for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1487  for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) {
1488  eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3)
1489  + group;
1490  pwrinfo->cck_index[rfpath][group] =
1491  (rom_content[eeaddr] == 0xFF) ?
1492  (eeaddr > 0x7B ?
1493  EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1494  EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1495  rom_content[eeaddr];
1496  }
1497  }
1498  for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1499  for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1500  offset1 = group / 3;
1501  offset2 = group % 3;
1502  eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) +
1503  offset2 + offset1 * 21;
1504  pwrinfo->ht40_1sindex[rfpath][group] =
1505  (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ?
1506  EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1507  EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1508  rom_content[eeaddr];
1509  }
1510  }
1511  /* These just for 92D efuse offset. */
1512  for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1513  for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1514  int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G;
1515 
1516  offset1 = group / 3;
1517  offset2 = group % 3;
1518 
1519  if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF)
1520  pwrinfo->ht40_2sindexdiff[rfpath][group] =
1521  (rom_content[base1 +
1522  offset2 + offset1 * 21] >> (rfpath * 4))
1523  & 0xF;
1524  else
1525  pwrinfo->ht40_2sindexdiff[rfpath][group] =
1526  EEPROM_DEFAULT_HT40_2SDIFF;
1527  if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2
1528  + offset1 * 21] != 0xFF)
1529  pwrinfo->ht20indexdiff[rfpath][group] =
1530  (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G
1531  + offset2 + offset1 * 21] >> (rfpath * 4))
1532  & 0xF;
1533  else
1534  pwrinfo->ht20indexdiff[rfpath][group] =
1535  EEPROM_DEFAULT_HT20_DIFF;
1536  if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2
1537  + offset1 * 21] != 0xFF)
1538  pwrinfo->ofdmindexdiff[rfpath][group] =
1539  (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G
1540  + offset2 + offset1 * 21] >> (rfpath * 4))
1541  & 0xF;
1542  else
1543  pwrinfo->ofdmindexdiff[rfpath][group] =
1544  EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1545  if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2
1546  + offset1 * 21] != 0xFF)
1547  pwrinfo->ht40maxoffset[rfpath][group] =
1548  (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G
1549  + offset2 + offset1 * 21] >> (rfpath * 4))
1550  & 0xF;
1551  else
1552  pwrinfo->ht40maxoffset[rfpath][group] =
1553  EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1554  if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2
1555  + offset1 * 21] != 0xFF)
1556  pwrinfo->ht20maxoffset[rfpath][group] =
1557  (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G +
1558  offset2 + offset1 * 21] >> (rfpath * 4)) &
1559  0xF;
1560  else
1561  pwrinfo->ht20maxoffset[rfpath][group] =
1562  EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1563  }
1564  }
1565  if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) {
1566  /* 5GL */
1567  pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F;
1568  pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F;
1569  /* 5GM */
1570  pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F;
1571  pwrinfo->tssi_b[1] =
1572  (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 |
1573  (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2;
1574  /* 5GH */
1575  pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] &
1576  0xF0) >> 4 |
1577  (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4;
1578  pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] &
1579  0xFC) >> 2;
1580  } else {
1581  for (i = 0; i < 3; i++) {
1582  pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1583  pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1584  }
1585  }
1586 }
1587 
1588 static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw,
1589  bool autoload_fail, u8 *hwinfo)
1590 {
1591  struct rtl_priv *rtlpriv = rtl_priv(hw);
1592  struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1593  struct txpower_info pwrinfo;
1594  u8 tempval[2], i, pwr, diff;
1595  u32 ch, rfPath, group;
1596 
1597  _rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail);
1598  if (!autoload_fail) {
1599  /* bit0~2 */
1600  rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7);
1601  rtlefuse->eeprom_thermalmeter =
1602  hwinfo[EEPROM_THERMAL_METER] & 0x1f;
1603  rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_K];
1604  tempval[0] = hwinfo[EEPROM_IQK_DELTA] & 0x03;
1605  tempval[1] = (hwinfo[EEPROM_LCK_DELTA] & 0x0C) >> 2;
1606  rtlefuse->txpwr_fromeprom = true;
1607  if (IS_92D_D_CUT(rtlpriv->rtlhal.version) ||
1608  IS_92D_E_CUT(rtlpriv->rtlhal.version)) {
1609  rtlefuse->internal_pa_5g[0] =
1610  !((hwinfo[EEPROM_TSSI_A_5G] & BIT(6)) >> 6);
1611  rtlefuse->internal_pa_5g[1] =
1612  !((hwinfo[EEPROM_TSSI_B_5G] & BIT(6)) >> 6);
1613  RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1614  "Is D cut,Internal PA0 %d Internal PA1 %d\n",
1615  rtlefuse->internal_pa_5g[0],
1616  rtlefuse->internal_pa_5g[1]);
1617  }
1618  rtlefuse->eeprom_c9 = hwinfo[EEPROM_RF_OPT6];
1619  rtlefuse->eeprom_cc = hwinfo[EEPROM_RF_OPT7];
1620  } else {
1621  rtlefuse->eeprom_regulatory = 0;
1622  rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1623  rtlefuse->crystalcap = EEPROM_DEFAULT_CRYSTALCAP;
1624  tempval[0] = tempval[1] = 3;
1625  }
1626 
1627  /* Use default value to fill parameters if
1628  * efuse is not filled on some place. */
1629 
1630  /* ThermalMeter from EEPROM */
1631  if (rtlefuse->eeprom_thermalmeter < 0x06 ||
1632  rtlefuse->eeprom_thermalmeter > 0x1c)
1633  rtlefuse->eeprom_thermalmeter = 0x12;
1634  rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1635 
1636  /* check XTAL_K */
1637  if (rtlefuse->crystalcap == 0xFF)
1638  rtlefuse->crystalcap = 0;
1639  if (rtlefuse->eeprom_regulatory > 3)
1640  rtlefuse->eeprom_regulatory = 0;
1641 
1642  for (i = 0; i < 2; i++) {
1643  switch (tempval[i]) {
1644  case 0:
1645  tempval[i] = 5;
1646  break;
1647  case 1:
1648  tempval[i] = 4;
1649  break;
1650  case 2:
1651  tempval[i] = 3;
1652  break;
1653  case 3:
1654  default:
1655  tempval[i] = 0;
1656  break;
1657  }
1658  }
1659 
1660  rtlefuse->delta_iqk = tempval[0];
1661  if (tempval[1] > 0)
1662  rtlefuse->delta_lck = tempval[1] - 1;
1663  if (rtlefuse->eeprom_c9 == 0xFF)
1664  rtlefuse->eeprom_c9 = 0x00;
1665  RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1666  "EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1667  RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1668  "ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1669  RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1670  "CrystalCap = 0x%x\n", rtlefuse->crystalcap);
1671  RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1672  "Delta_IQK = 0x%x Delta_LCK = 0x%x\n",
1673  rtlefuse->delta_iqk, rtlefuse->delta_lck);
1674 
1675  for (rfPath = 0; rfPath < RF6052_MAX_PATH; rfPath++) {
1676  for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1677  group = rtl92d_get_chnlgroup_fromarray((u8) ch);
1678  if (ch < CHANNEL_MAX_NUMBER_2G)
1679  rtlefuse->txpwrlevel_cck[rfPath][ch] =
1680  pwrinfo.cck_index[rfPath][group];
1681  rtlefuse->txpwrlevel_ht40_1s[rfPath][ch] =
1682  pwrinfo.ht40_1sindex[rfPath][group];
1683  rtlefuse->txpwr_ht20diff[rfPath][ch] =
1684  pwrinfo.ht20indexdiff[rfPath][group];
1685  rtlefuse->txpwr_legacyhtdiff[rfPath][ch] =
1686  pwrinfo.ofdmindexdiff[rfPath][group];
1687  rtlefuse->pwrgroup_ht20[rfPath][ch] =
1688  pwrinfo.ht20maxoffset[rfPath][group];
1689  rtlefuse->pwrgroup_ht40[rfPath][ch] =
1690  pwrinfo.ht40maxoffset[rfPath][group];
1691  pwr = pwrinfo.ht40_1sindex[rfPath][group];
1692  diff = pwrinfo.ht40_2sindexdiff[rfPath][group];
1693  rtlefuse->txpwrlevel_ht40_2s[rfPath][ch] =
1694  (pwr > diff) ? (pwr - diff) : 0;
1695  }
1696  }
1697 }
1698 
1699 static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw,
1700  u8 *content)
1701 {
1702  struct rtl_priv *rtlpriv = rtl_priv(hw);
1703  struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1704  u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION];
1705 
1706  if (macphy_crvalue & BIT(3)) {
1707  rtlhal->macphymode = SINGLEMAC_SINGLEPHY;
1708  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1709  "MacPhyMode SINGLEMAC_SINGLEPHY\n");
1710  } else {
1711  rtlhal->macphymode = DUALMAC_DUALPHY;
1712  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1713  "MacPhyMode DUALMAC_DUALPHY\n");
1714  }
1715 }
1716 
1717 static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw,
1718  u8 *content)
1719 {
1720  _rtl92de_read_macphymode_from_prom(hw, content);
1721  rtl92d_phy_config_macphymode(hw);
1722  rtl92d_phy_config_macphymode_info(hw);
1723 }
1724 
1725 static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw)
1726 {
1727  struct rtl_priv *rtlpriv = rtl_priv(hw);
1728  enum version_8192d chipver = rtlpriv->rtlhal.version;
1729  u8 cutvalue[2];
1730  u16 chipvalue;
1731 
1732  rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_H,
1733  &cutvalue[1]);
1734  rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_L,
1735  &cutvalue[0]);
1736  chipvalue = (cutvalue[1] << 8) | cutvalue[0];
1737  switch (chipvalue) {
1738  case 0xAA55:
1739  chipver |= CHIP_92D_C_CUT;
1740  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "C-CUT!!!\n");
1741  break;
1742  case 0x9966:
1743  chipver |= CHIP_92D_D_CUT;
1744  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n");
1745  break;
1746  case 0xCC33:
1747  chipver |= CHIP_92D_E_CUT;
1748  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n");
1749  break;
1750  default:
1751  chipver |= CHIP_92D_D_CUT;
1752  RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Unknown CUT!\n");
1753  break;
1754  }
1755  rtlpriv->rtlhal.version = chipver;
1756 }
1757 
1758 static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw)
1759 {
1760  struct rtl_priv *rtlpriv = rtl_priv(hw);
1761  struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1762  struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1763  u16 i, usvalue;
1764  u8 hwinfo[HWSET_MAX_SIZE];
1765  u16 eeprom_id;
1766  unsigned long flags;
1767 
1768  if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1769  spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags);
1770  rtl_efuse_shadow_map_update(hw);
1771  _rtl92de_efuse_update_chip_version(hw);
1772  spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
1773  memcpy((void *)hwinfo, (void *)&rtlefuse->efuse_map
1774  [EFUSE_INIT_MAP][0],
1775  HWSET_MAX_SIZE);
1776  } else if (rtlefuse->epromtype == EEPROM_93C46) {
1777  RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1778  "RTL819X Not boot from eeprom, check it !!\n");
1779  }
1780  RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1781  hwinfo, HWSET_MAX_SIZE);
1782 
1783  eeprom_id = *((u16 *)&hwinfo[0]);
1784  if (eeprom_id != RTL8190_EEPROM_ID) {
1785  RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1786  "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1787  rtlefuse->autoload_failflag = true;
1788  } else {
1789  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1790  rtlefuse->autoload_failflag = false;
1791  }
1792  if (rtlefuse->autoload_failflag) {
1793  RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1794  "RTL819X Not boot from eeprom, check it !!\n");
1795  return;
1796  }
1797  rtlefuse->eeprom_oemid = hwinfo[EEPROM_CUSTOMER_ID];
1798  _rtl92de_read_macphymode_and_bandtype(hw, hwinfo);
1799 
1800  /* VID, DID SE 0xA-D */
1801  rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1802  rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1803  rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1804  rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1805  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROMId = 0x%4x\n", eeprom_id);
1806  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1807  "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1808  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1809  "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1810  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1811  "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1812  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1813  "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1814 
1815  /* Read Permanent MAC address */
1816  if (rtlhal->interfaceindex == 0) {
1817  for (i = 0; i < 6; i += 2) {
1818  usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC0_92D + i];
1819  *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1820  }
1821  } else {
1822  for (i = 0; i < 6; i += 2) {
1823  usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i];
1824  *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1825  }
1826  }
1827  rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR,
1828  rtlefuse->dev_addr);
1829  RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1830  _rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo);
1831 
1832  /* Read Channel Plan */
1833  switch (rtlhal->bandset) {
1834  case BAND_ON_2_4G:
1835  rtlefuse->channel_plan = COUNTRY_CODE_TELEC;
1836  break;
1837  case BAND_ON_5G:
1838  rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1839  break;
1840  case BAND_ON_BOTH:
1841  rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1842  break;
1843  default:
1844  rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1845  break;
1846  }
1847  rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1848  rtlefuse->txpwr_fromeprom = true;
1849  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1850  "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1851 }
1852 
1853 void rtl92de_read_eeprom_info(struct ieee80211_hw *hw)
1854 {
1855  struct rtl_priv *rtlpriv = rtl_priv(hw);
1856  struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1857  struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1858  u8 tmp_u1b;
1859 
1860  rtlhal->version = _rtl92de_read_chip_version(hw);
1861  tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1862  rtlefuse->autoload_status = tmp_u1b;
1863  if (tmp_u1b & BIT(4)) {
1864  RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1865  rtlefuse->epromtype = EEPROM_93C46;
1866  } else {
1867  RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1868  rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1869  }
1870  if (tmp_u1b & BIT(5)) {
1871  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1872 
1873  rtlefuse->autoload_failflag = false;
1874  _rtl92de_read_adapter_info(hw);
1875  } else {
1876  RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1877  }
1878  return;
1879 }
1880 
1881 static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw,
1882  struct ieee80211_sta *sta)
1883 {
1884  struct rtl_priv *rtlpriv = rtl_priv(hw);
1885  struct rtl_phy *rtlphy = &(rtlpriv->phy);
1886  struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1887  struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1888  u32 ratr_value;
1889  u8 ratr_index = 0;
1890  u8 nmode = mac->ht_enable;
1891  u8 mimo_ps = IEEE80211_SMPS_OFF;
1892  u16 shortgi_rate;
1893  u32 tmp_ratr_value;
1894  u8 curtxbw_40mhz = mac->bw_40;
1895  u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1896  1 : 0;
1897  u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1898  1 : 0;
1899  enum wireless_mode wirelessmode = mac->mode;
1900 
1901  if (rtlhal->current_bandtype == BAND_ON_5G)
1902  ratr_value = sta->supp_rates[1] << 4;
1903  else
1904  ratr_value = sta->supp_rates[0];
1905  ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1906  sta->ht_cap.mcs.rx_mask[0] << 12);
1907  switch (wirelessmode) {
1908  case WIRELESS_MODE_A:
1909  ratr_value &= 0x00000FF0;
1910  break;
1911  case WIRELESS_MODE_B:
1912  if (ratr_value & 0x0000000c)
1913  ratr_value &= 0x0000000d;
1914  else
1915  ratr_value &= 0x0000000f;
1916  break;
1917  case WIRELESS_MODE_G:
1918  ratr_value &= 0x00000FF5;
1919  break;
1920  case WIRELESS_MODE_N_24G:
1921  case WIRELESS_MODE_N_5G:
1922  nmode = 1;
1923  if (mimo_ps == IEEE80211_SMPS_STATIC) {
1924  ratr_value &= 0x0007F005;
1925  } else {
1926  u32 ratr_mask;
1927 
1928  if (get_rf_type(rtlphy) == RF_1T2R ||
1929  get_rf_type(rtlphy) == RF_1T1R) {
1930  ratr_mask = 0x000ff005;
1931  } else {
1932  ratr_mask = 0x0f0ff005;
1933  }
1934 
1935  ratr_value &= ratr_mask;
1936  }
1937  break;
1938  default:
1939  if (rtlphy->rf_type == RF_1T2R)
1940  ratr_value &= 0x000ff0ff;
1941  else
1942  ratr_value &= 0x0f0ff0ff;
1943 
1944  break;
1945  }
1946  ratr_value &= 0x0FFFFFFF;
1947  if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
1948  (!curtxbw_40mhz && curshortgi_20mhz))) {
1949  ratr_value |= 0x10000000;
1950  tmp_ratr_value = (ratr_value >> 12);
1951  for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1952  if ((1 << shortgi_rate) & tmp_ratr_value)
1953  break;
1954  }
1955  shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1956  (shortgi_rate << 4) | (shortgi_rate);
1957  }
1958  rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1959  RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1960  rtl_read_dword(rtlpriv, REG_ARFR0));
1961 }
1962 
1963 static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw,
1964  struct ieee80211_sta *sta, u8 rssi_level)
1965 {
1966  struct rtl_priv *rtlpriv = rtl_priv(hw);
1967  struct rtl_phy *rtlphy = &(rtlpriv->phy);
1968  struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1969  struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1970  struct rtl_sta_info *sta_entry = NULL;
1971  u32 ratr_bitmap;
1972  u8 ratr_index;
1973  u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
1974  ? 1 : 0;
1975  u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1976  1 : 0;
1977  u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1978  1 : 0;
1979  enum wireless_mode wirelessmode = 0;
1980  bool shortgi = false;
1981  u32 value[2];
1982  u8 macid = 0;
1983  u8 mimo_ps = IEEE80211_SMPS_OFF;
1984 
1985  sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1986  mimo_ps = sta_entry->mimo_ps;
1987  wirelessmode = sta_entry->wireless_mode;
1988  if (mac->opmode == NL80211_IFTYPE_STATION)
1989  curtxbw_40mhz = mac->bw_40;
1990  else if (mac->opmode == NL80211_IFTYPE_AP ||
1991  mac->opmode == NL80211_IFTYPE_ADHOC)
1992  macid = sta->aid + 1;
1993 
1994  if (rtlhal->current_bandtype == BAND_ON_5G)
1995  ratr_bitmap = sta->supp_rates[1] << 4;
1996  else
1997  ratr_bitmap = sta->supp_rates[0];
1998  ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1999  sta->ht_cap.mcs.rx_mask[0] << 12);
2000  switch (wirelessmode) {
2001  case WIRELESS_MODE_B:
2002  ratr_index = RATR_INX_WIRELESS_B;
2003  if (ratr_bitmap & 0x0000000c)
2004  ratr_bitmap &= 0x0000000d;
2005  else
2006  ratr_bitmap &= 0x0000000f;
2007  break;
2008  case WIRELESS_MODE_G:
2009  ratr_index = RATR_INX_WIRELESS_GB;
2010 
2011  if (rssi_level == 1)
2012  ratr_bitmap &= 0x00000f00;
2013  else if (rssi_level == 2)
2014  ratr_bitmap &= 0x00000ff0;
2015  else
2016  ratr_bitmap &= 0x00000ff5;
2017  break;
2018  case WIRELESS_MODE_A:
2019  ratr_index = RATR_INX_WIRELESS_G;
2020  ratr_bitmap &= 0x00000ff0;
2021  break;
2022  case WIRELESS_MODE_N_24G:
2023  case WIRELESS_MODE_N_5G:
2024  if (wirelessmode == WIRELESS_MODE_N_24G)
2025  ratr_index = RATR_INX_WIRELESS_NGB;
2026  else
2027  ratr_index = RATR_INX_WIRELESS_NG;
2028  if (mimo_ps == IEEE80211_SMPS_STATIC) {
2029  if (rssi_level == 1)
2030  ratr_bitmap &= 0x00070000;
2031  else if (rssi_level == 2)
2032  ratr_bitmap &= 0x0007f000;
2033  else
2034  ratr_bitmap &= 0x0007f005;
2035  } else {
2036  if (rtlphy->rf_type == RF_1T2R ||
2037  rtlphy->rf_type == RF_1T1R) {
2038  if (curtxbw_40mhz) {
2039  if (rssi_level == 1)
2040  ratr_bitmap &= 0x000f0000;
2041  else if (rssi_level == 2)
2042  ratr_bitmap &= 0x000ff000;
2043  else
2044  ratr_bitmap &= 0x000ff015;
2045  } else {
2046  if (rssi_level == 1)
2047  ratr_bitmap &= 0x000f0000;
2048  else if (rssi_level == 2)
2049  ratr_bitmap &= 0x000ff000;
2050  else
2051  ratr_bitmap &= 0x000ff005;
2052  }
2053  } else {
2054  if (curtxbw_40mhz) {
2055  if (rssi_level == 1)
2056  ratr_bitmap &= 0x0f0f0000;
2057  else if (rssi_level == 2)
2058  ratr_bitmap &= 0x0f0ff000;
2059  else
2060  ratr_bitmap &= 0x0f0ff015;
2061  } else {
2062  if (rssi_level == 1)
2063  ratr_bitmap &= 0x0f0f0000;
2064  else if (rssi_level == 2)
2065  ratr_bitmap &= 0x0f0ff000;
2066  else
2067  ratr_bitmap &= 0x0f0ff005;
2068  }
2069  }
2070  }
2071  if ((curtxbw_40mhz && curshortgi_40mhz) ||
2072  (!curtxbw_40mhz && curshortgi_20mhz)) {
2073 
2074  if (macid == 0)
2075  shortgi = true;
2076  else if (macid == 1)
2077  shortgi = false;
2078  }
2079  break;
2080  default:
2081  ratr_index = RATR_INX_WIRELESS_NGB;
2082 
2083  if (rtlphy->rf_type == RF_1T2R)
2084  ratr_bitmap &= 0x000ff0ff;
2085  else
2086  ratr_bitmap &= 0x0f0ff0ff;
2087  break;
2088  }
2089 
2090  value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28);
2091  value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2092  RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2093  "ratr_bitmap :%x value0:%x value1:%x\n",
2094  ratr_bitmap, value[0], value[1]);
2095  rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *) value);
2096  if (macid != 0)
2097  sta_entry->ratr_index = ratr_index;
2098 }
2099 
2100 void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw,
2101  struct ieee80211_sta *sta, u8 rssi_level)
2102 {
2103  struct rtl_priv *rtlpriv = rtl_priv(hw);
2104 
2105  if (rtlpriv->dm.useramask)
2106  rtl92de_update_hal_rate_mask(hw, sta, rssi_level);
2107  else
2108  rtl92de_update_hal_rate_table(hw, sta);
2109 }
2110 
2111 void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw)
2112 {
2113  struct rtl_priv *rtlpriv = rtl_priv(hw);
2114  struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2115  u16 sifs_timer;
2116 
2117  rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2118  &mac->slot_time);
2119  if (!mac->ht_enable)
2120  sifs_timer = 0x0a0a;
2121  else
2122  sifs_timer = 0x1010;
2123  rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2124 }
2125 
2126 bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2127 {
2128  struct rtl_priv *rtlpriv = rtl_priv(hw);
2129  struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2130  struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2131  enum rf_pwrstate e_rfpowerstate_toset;
2132  u8 u1tmp;
2133  bool actuallyset = false;
2134  unsigned long flag;
2135 
2136  if (rtlpci->being_init_adapter)
2137  return false;
2138  if (ppsc->swrf_processing)
2139  return false;
2140  spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2141  if (ppsc->rfchange_inprogress) {
2142  spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2143  return false;
2144  } else {
2145  ppsc->rfchange_inprogress = true;
2146  spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2147  }
2148  rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2149  REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2150  u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2151  e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2152  if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2153  RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2154  "GPIOChangeRF - HW Radio ON, RF ON\n");
2155  e_rfpowerstate_toset = ERFON;
2156  ppsc->hwradiooff = false;
2157  actuallyset = true;
2158  } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2159  RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2160  "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2161  e_rfpowerstate_toset = ERFOFF;
2162  ppsc->hwradiooff = true;
2163  actuallyset = true;
2164  }
2165  if (actuallyset) {
2166  spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2167  ppsc->rfchange_inprogress = false;
2168  spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2169  } else {
2170  if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2171  RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2172  spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2173  ppsc->rfchange_inprogress = false;
2174  spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2175  }
2176  *valid = 1;
2177  return !ppsc->hwradiooff;
2178 }
2179 
2180 void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index,
2181  u8 *p_macaddr, bool is_group, u8 enc_algo,
2182  bool is_wepkey, bool clear_all)
2183 {
2184  struct rtl_priv *rtlpriv = rtl_priv(hw);
2185  struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2186  struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2187  u8 *macaddr = p_macaddr;
2188  u32 entry_id;
2189  bool is_pairwise = false;
2190  static u8 cam_const_addr[4][6] = {
2191  {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2192  {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2193  {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2194  {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2195  };
2196  static u8 cam_const_broad[] = {
2197  0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2198  };
2199 
2200  if (clear_all) {
2201  u8 idx;
2202  u8 cam_offset = 0;
2203  u8 clear_number = 5;
2204  RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2205  for (idx = 0; idx < clear_number; idx++) {
2206  rtl_cam_mark_invalid(hw, cam_offset + idx);
2207  rtl_cam_empty_entry(hw, cam_offset + idx);
2208 
2209  if (idx < 5) {
2210  memset(rtlpriv->sec.key_buf[idx], 0,
2211  MAX_KEY_LEN);
2212  rtlpriv->sec.key_len[idx] = 0;
2213  }
2214  }
2215  } else {
2216  switch (enc_algo) {
2217  case WEP40_ENCRYPTION:
2218  enc_algo = CAM_WEP40;
2219  break;
2220  case WEP104_ENCRYPTION:
2221  enc_algo = CAM_WEP104;
2222  break;
2223  case TKIP_ENCRYPTION:
2224  enc_algo = CAM_TKIP;
2225  break;
2226  case AESCCMP_ENCRYPTION:
2227  enc_algo = CAM_AES;
2228  break;
2229  default:
2230  RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2231  "switch case not processed\n");
2232  enc_algo = CAM_TKIP;
2233  break;
2234  }
2235  if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2236  macaddr = cam_const_addr[key_index];
2237  entry_id = key_index;
2238  } else {
2239  if (is_group) {
2240  macaddr = cam_const_broad;
2241  entry_id = key_index;
2242  } else {
2243  if (mac->opmode == NL80211_IFTYPE_AP) {
2244  entry_id = rtl_cam_get_free_entry(hw,
2245  p_macaddr);
2246  if (entry_id >= TOTAL_CAM_ENTRY) {
2247  RT_TRACE(rtlpriv, COMP_SEC,
2248  DBG_EMERG,
2249  "Can not find free hw security cam entry\n");
2250  return;
2251  }
2252  } else {
2253  entry_id = CAM_PAIRWISE_KEY_POSITION;
2254  }
2255  key_index = PAIRWISE_KEYIDX;
2256  is_pairwise = true;
2257  }
2258  }
2259  if (rtlpriv->sec.key_len[key_index] == 0) {
2260  RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2261  "delete one entry, entry_id is %d\n",
2262  entry_id);
2263  if (mac->opmode == NL80211_IFTYPE_AP)
2264  rtl_cam_del_entry(hw, p_macaddr);
2265  rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2266  } else {
2267  RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2268  "The insert KEY length is %d\n",
2269  rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2270  RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2271  "The insert KEY is %x %x\n",
2272  rtlpriv->sec.key_buf[0][0],
2273  rtlpriv->sec.key_buf[0][1]);
2274  RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2275  "add one entry\n");
2276  if (is_pairwise) {
2277  RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2278  "Pairwise Key content",
2279  rtlpriv->sec.pairwise_key,
2280  rtlpriv->
2281  sec.key_len[PAIRWISE_KEYIDX]);
2282  RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2283  "set Pairwise key\n");
2284  rtl_cam_add_one_entry(hw, macaddr, key_index,
2285  entry_id, enc_algo,
2286  CAM_CONFIG_NO_USEDK,
2287  rtlpriv->
2288  sec.key_buf[key_index]);
2289  } else {
2290  RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2291  "set group key\n");
2292  if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2293  rtl_cam_add_one_entry(hw,
2294  rtlefuse->dev_addr,
2295  PAIRWISE_KEYIDX,
2296  CAM_PAIRWISE_KEY_POSITION,
2297  enc_algo, CAM_CONFIG_NO_USEDK,
2298  rtlpriv->sec.key_buf[entry_id]);
2299  }
2300  rtl_cam_add_one_entry(hw, macaddr, key_index,
2301  entry_id, enc_algo,
2302  CAM_CONFIG_NO_USEDK,
2303  rtlpriv->sec.key_buf
2304  [entry_id]);
2305  }
2306  }
2307  }
2308 }
2309 
2310 void rtl92de_suspend(struct ieee80211_hw *hw)
2311 {
2312  struct rtl_priv *rtlpriv = rtl_priv(hw);
2313 
2314  rtlpriv->rtlhal.macphyctl_reg = rtl_read_byte(rtlpriv,
2315  REG_MAC_PHY_CTRL_NORMAL);
2316 }
2317 
2318 void rtl92de_resume(struct ieee80211_hw *hw)
2319 {
2320  struct rtl_priv *rtlpriv = rtl_priv(hw);
2321 
2322  rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL,
2323  rtlpriv->rtlhal.macphyctl_reg);
2324 }
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