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phy.c
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1 /******************************************************************************
2  *
3  * Copyright(c) 2009-2012 Realtek Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  * The full GNU General Public License is included in this distribution in the
19  * file called LICENSE.
20  *
21  * Contact Information:
22  * wlanfae <[email protected]>
23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24  * Hsinchu 300, Taiwan.
25  *
26  * Larry Finger <[email protected]>
27  *
28  *****************************************************************************/
29 
30 #include "../wifi.h"
31 #include "../pci.h"
32 #include "../ps.h"
33 #include "reg.h"
34 #include "def.h"
35 #include "phy.h"
36 #include "rf.h"
37 #include "dm.h"
38 #include "fw.h"
39 #include "hw.h"
40 #include "table.h"
41 
42 static u32 _rtl92s_phy_calculate_bit_shift(u32 bitmask)
43 {
44  u32 i;
45 
46  for (i = 0; i <= 31; i++) {
47  if (((bitmask >> i) & 0x1) == 1)
48  break;
49  }
50 
51  return i;
52 }
53 
54 u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
55 {
56  struct rtl_priv *rtlpriv = rtl_priv(hw);
57  u32 returnvalue = 0, originalvalue, bitshift;
58 
59  RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
60  regaddr, bitmask);
61 
62  originalvalue = rtl_read_dword(rtlpriv, regaddr);
63  bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
64  returnvalue = (originalvalue & bitmask) >> bitshift;
65 
66  RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
67  bitmask, regaddr, originalvalue);
68 
69  return returnvalue;
70 
71 }
72 
73 void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
74  u32 data)
75 {
76  struct rtl_priv *rtlpriv = rtl_priv(hw);
77  u32 originalvalue, bitshift;
78 
79  RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
80  "regaddr(%#x), bitmask(%#x), data(%#x)\n",
81  regaddr, bitmask, data);
82 
83  if (bitmask != MASKDWORD) {
84  originalvalue = rtl_read_dword(rtlpriv, regaddr);
85  bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
86  data = ((originalvalue & (~bitmask)) | (data << bitshift));
87  }
88 
89  rtl_write_dword(rtlpriv, regaddr, data);
90 
91  RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
92  "regaddr(%#x), bitmask(%#x), data(%#x)\n",
93  regaddr, bitmask, data);
94 
95 }
96 
97 static u32 _rtl92s_phy_rf_serial_read(struct ieee80211_hw *hw,
98  enum radio_path rfpath, u32 offset)
99 {
100 
101  struct rtl_priv *rtlpriv = rtl_priv(hw);
102  struct rtl_phy *rtlphy = &(rtlpriv->phy);
103  struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
104  u32 newoffset;
105  u32 tmplong, tmplong2;
106  u8 rfpi_enable = 0;
107  u32 retvalue = 0;
108 
109  offset &= 0x3f;
110  newoffset = offset;
111 
112  tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
113 
114  if (rfpath == RF90_PATH_A)
115  tmplong2 = tmplong;
116  else
117  tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
118 
119  tmplong2 = (tmplong2 & (~BLSSI_READADDRESS)) | (newoffset << 23) |
120  BLSSI_READEDGE;
121 
122  rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
123  tmplong & (~BLSSI_READEDGE));
124 
125  mdelay(1);
126 
127  rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
128  mdelay(1);
129 
130  rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong |
131  BLSSI_READEDGE);
132  mdelay(1);
133 
134  if (rfpath == RF90_PATH_A)
135  rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
136  BIT(8));
137  else if (rfpath == RF90_PATH_B)
138  rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
139  BIT(8));
140 
141  if (rfpi_enable)
142  retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readbackpi,
143  BLSSI_READBACK_DATA);
144  else
145  retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
146  BLSSI_READBACK_DATA);
147 
148  retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
149  BLSSI_READBACK_DATA);
150 
151  RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
152  rfpath, pphyreg->rflssi_readback, retvalue);
153 
154  return retvalue;
155 
156 }
157 
158 static void _rtl92s_phy_rf_serial_write(struct ieee80211_hw *hw,
159  enum radio_path rfpath, u32 offset,
160  u32 data)
161 {
162  struct rtl_priv *rtlpriv = rtl_priv(hw);
163  struct rtl_phy *rtlphy = &(rtlpriv->phy);
164  struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
165  u32 data_and_addr = 0;
166  u32 newoffset;
167 
168  offset &= 0x3f;
169  newoffset = offset;
170 
171  data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
172  rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
173 
174  RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
175  rfpath, pphyreg->rf3wire_offset, data_and_addr);
176 }
177 
178 
179 u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
180  u32 regaddr, u32 bitmask)
181 {
182  struct rtl_priv *rtlpriv = rtl_priv(hw);
183  u32 original_value, readback_value, bitshift;
184 
185  RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
186  "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
187  regaddr, rfpath, bitmask);
188 
189  spin_lock(&rtlpriv->locks.rf_lock);
190 
191  original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr);
192 
193  bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
194  readback_value = (original_value & bitmask) >> bitshift;
195 
196  spin_unlock(&rtlpriv->locks.rf_lock);
197 
198  RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
199  "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
200  regaddr, rfpath, bitmask, original_value);
201 
202  return readback_value;
203 }
204 
205 void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
206  u32 regaddr, u32 bitmask, u32 data)
207 {
208  struct rtl_priv *rtlpriv = rtl_priv(hw);
209  struct rtl_phy *rtlphy = &(rtlpriv->phy);
210  u32 original_value, bitshift;
211 
212  if (!((rtlphy->rf_pathmap >> rfpath) & 0x1))
213  return;
214 
215  RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
216  "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
217  regaddr, bitmask, data, rfpath);
218 
219  spin_lock(&rtlpriv->locks.rf_lock);
220 
221  if (bitmask != RFREG_OFFSET_MASK) {
222  original_value = _rtl92s_phy_rf_serial_read(hw, rfpath,
223  regaddr);
224  bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
225  data = ((original_value & (~bitmask)) | (data << bitshift));
226  }
227 
228  _rtl92s_phy_rf_serial_write(hw, rfpath, regaddr, data);
229 
230  spin_unlock(&rtlpriv->locks.rf_lock);
231 
232  RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
233  "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
234  regaddr, bitmask, data, rfpath);
235 
236 }
237 
238 void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw,
239  u8 operation)
240 {
241  struct rtl_priv *rtlpriv = rtl_priv(hw);
242  struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
243 
244  if (!is_hal_stop(rtlhal)) {
245  switch (operation) {
246  case SCAN_OPT_BACKUP:
247  rtl92s_phy_set_fw_cmd(hw, FW_CMD_PAUSE_DM_BY_SCAN);
248  break;
249  case SCAN_OPT_RESTORE:
250  rtl92s_phy_set_fw_cmd(hw, FW_CMD_RESUME_DM_BY_SCAN);
251  break;
252  default:
253  RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
254  "Unknown operation\n");
255  break;
256  }
257  }
258 }
259 
260 void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw,
261  enum nl80211_channel_type ch_type)
262 {
263  struct rtl_priv *rtlpriv = rtl_priv(hw);
264  struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
265  struct rtl_phy *rtlphy = &(rtlpriv->phy);
266  struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
267  u8 reg_bw_opmode;
268 
269  RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
270  rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
271  "20MHz" : "40MHz");
272 
273  if (rtlphy->set_bwmode_inprogress)
274  return;
275  if (is_hal_stop(rtlhal))
276  return;
277 
278  rtlphy->set_bwmode_inprogress = true;
279 
280  reg_bw_opmode = rtl_read_byte(rtlpriv, BW_OPMODE);
281  /* dummy read */
282  rtl_read_byte(rtlpriv, RRSR + 2);
283 
284  switch (rtlphy->current_chan_bw) {
285  case HT_CHANNEL_WIDTH_20:
286  reg_bw_opmode |= BW_OPMODE_20MHZ;
287  rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
288  break;
289  case HT_CHANNEL_WIDTH_20_40:
290  reg_bw_opmode &= ~BW_OPMODE_20MHZ;
291  rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
292  break;
293  default:
294  RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
295  "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
296  break;
297  }
298 
299  switch (rtlphy->current_chan_bw) {
300  case HT_CHANNEL_WIDTH_20:
301  rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
302  rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
303 
304  if (rtlhal->version >= VERSION_8192S_BCUT)
305  rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x58);
306  break;
307  case HT_CHANNEL_WIDTH_20_40:
308  rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
309  rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
310 
311  rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
312  (mac->cur_40_prime_sc >> 1));
313  rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
314 
315  if (rtlhal->version >= VERSION_8192S_BCUT)
316  rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x18);
317  break;
318  default:
319  RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
320  "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
321  break;
322  }
323 
324  rtl92s_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
325  rtlphy->set_bwmode_inprogress = false;
326  RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
327 }
328 
329 static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
330  u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
331  u32 para1, u32 para2, u32 msdelay)
332 {
333  struct swchnlcmd *pcmd;
334 
335  if (cmdtable == NULL) {
336  RT_ASSERT(false, "cmdtable cannot be NULL\n");
337  return false;
338  }
339 
340  if (cmdtableidx >= cmdtablesz)
341  return false;
342 
343  pcmd = cmdtable + cmdtableidx;
344  pcmd->cmdid = cmdid;
345  pcmd->para1 = para1;
346  pcmd->para2 = para2;
347  pcmd->msdelay = msdelay;
348 
349  return true;
350 }
351 
352 static bool _rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
353  u8 channel, u8 *stage, u8 *step, u32 *delay)
354 {
355  struct rtl_priv *rtlpriv = rtl_priv(hw);
356  struct rtl_phy *rtlphy = &(rtlpriv->phy);
357  struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
358  u32 precommoncmdcnt;
359  struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
360  u32 postcommoncmdcnt;
361  struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
362  u32 rfdependcmdcnt;
363  struct swchnlcmd *currentcmd = NULL;
364  u8 rfpath;
365  u8 num_total_rfpath = rtlphy->num_total_rfpath;
366 
367  precommoncmdcnt = 0;
368  _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
369  MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
370  _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
371  MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
372 
373  postcommoncmdcnt = 0;
374 
375  _rtl92s_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
376  MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
377 
378  rfdependcmdcnt = 0;
379 
380  RT_ASSERT((channel >= 1 && channel <= 14),
381  "invalid channel for Zebra: %d\n", channel);
382 
383  _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
384  MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
385  RF_CHNLBW, channel, 10);
386 
387  _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
388  MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0);
389 
390  do {
391  switch (*stage) {
392  case 0:
393  currentcmd = &precommoncmd[*step];
394  break;
395  case 1:
396  currentcmd = &rfdependcmd[*step];
397  break;
398  case 2:
399  currentcmd = &postcommoncmd[*step];
400  break;
401  }
402 
403  if (currentcmd->cmdid == CMDID_END) {
404  if ((*stage) == 2) {
405  return true;
406  } else {
407  (*stage)++;
408  (*step) = 0;
409  continue;
410  }
411  }
412 
413  switch (currentcmd->cmdid) {
414  case CMDID_SET_TXPOWEROWER_LEVEL:
415  rtl92s_phy_set_txpower(hw, channel);
416  break;
417  case CMDID_WRITEPORT_ULONG:
418  rtl_write_dword(rtlpriv, currentcmd->para1,
419  currentcmd->para2);
420  break;
421  case CMDID_WRITEPORT_USHORT:
422  rtl_write_word(rtlpriv, currentcmd->para1,
423  (u16)currentcmd->para2);
424  break;
425  case CMDID_WRITEPORT_UCHAR:
426  rtl_write_byte(rtlpriv, currentcmd->para1,
427  (u8)currentcmd->para2);
428  break;
429  case CMDID_RF_WRITEREG:
430  for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
431  rtlphy->rfreg_chnlval[rfpath] =
432  ((rtlphy->rfreg_chnlval[rfpath] &
433  0xfffffc00) | currentcmd->para2);
434  rtl_set_rfreg(hw, (enum radio_path)rfpath,
435  currentcmd->para1,
436  RFREG_OFFSET_MASK,
437  rtlphy->rfreg_chnlval[rfpath]);
438  }
439  break;
440  default:
441  RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
442  "switch case not processed\n");
443  break;
444  }
445 
446  break;
447  } while (true);
448 
449  (*delay) = currentcmd->msdelay;
450  (*step)++;
451  return false;
452 }
453 
454 u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw)
455 {
456  struct rtl_priv *rtlpriv = rtl_priv(hw);
457  struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
458  struct rtl_phy *rtlphy = &(rtlpriv->phy);
459  u32 delay;
460  bool ret;
461 
462  RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "switch to channel%d\n",
463  rtlphy->current_channel);
464 
465  if (rtlphy->sw_chnl_inprogress)
466  return 0;
467 
468  if (rtlphy->set_bwmode_inprogress)
469  return 0;
470 
471  if (is_hal_stop(rtlhal))
472  return 0;
473 
474  rtlphy->sw_chnl_inprogress = true;
475  rtlphy->sw_chnl_stage = 0;
476  rtlphy->sw_chnl_step = 0;
477 
478  do {
479  if (!rtlphy->sw_chnl_inprogress)
480  break;
481 
482  ret = _rtl92s_phy_sw_chnl_step_by_step(hw,
483  rtlphy->current_channel,
484  &rtlphy->sw_chnl_stage,
485  &rtlphy->sw_chnl_step, &delay);
486  if (!ret) {
487  if (delay > 0)
488  mdelay(delay);
489  else
490  continue;
491  } else {
492  rtlphy->sw_chnl_inprogress = false;
493  }
494  break;
495  } while (true);
496 
497  rtlphy->sw_chnl_inprogress = false;
498 
499  RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
500 
501  return 1;
502 }
503 
504 static void _rtl92se_phy_set_rf_sleep(struct ieee80211_hw *hw)
505 {
506  struct rtl_priv *rtlpriv = rtl_priv(hw);
507  u8 u1btmp;
508 
509  u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
510  u1btmp |= BIT(0);
511 
512  rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
513  rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
514  rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
515  rtl_write_word(rtlpriv, CMDR, 0x57FC);
516  udelay(100);
517 
518  rtl_write_word(rtlpriv, CMDR, 0x77FC);
519  rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
520  udelay(10);
521 
522  rtl_write_word(rtlpriv, CMDR, 0x37FC);
523  udelay(10);
524 
525  rtl_write_word(rtlpriv, CMDR, 0x77FC);
526  udelay(10);
527 
528  rtl_write_word(rtlpriv, CMDR, 0x57FC);
529 
530  /* we should chnge GPIO to input mode
531  * this will drop away current about 25mA*/
532  rtl8192se_gpiobit3_cfg_inputmode(hw);
533 }
534 
535 bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw,
536  enum rf_pwrstate rfpwr_state)
537 {
538  struct rtl_priv *rtlpriv = rtl_priv(hw);
539  struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
540  struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
541  struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
542  bool bresult = true;
543  u8 i, queue_id;
544  struct rtl8192_tx_ring *ring = NULL;
545 
546  if (rfpwr_state == ppsc->rfpwr_state)
547  return false;
548 
549  switch (rfpwr_state) {
550  case ERFON:{
551  if ((ppsc->rfpwr_state == ERFOFF) &&
552  RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
553 
554  bool rtstatus;
555  u32 InitializeCount = 0;
556  do {
557  InitializeCount++;
558  RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
559  "IPS Set eRf nic enable\n");
560  rtstatus = rtl_ps_enable_nic(hw);
561  } while (!rtstatus && (InitializeCount < 10));
562 
563  RT_CLEAR_PS_LEVEL(ppsc,
564  RT_RF_OFF_LEVL_HALT_NIC);
565  } else {
566  RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
567  "awake, sleeped:%d ms state_inap:%x\n",
568  jiffies_to_msecs(jiffies -
569  ppsc->
570  last_sleep_jiffies),
571  rtlpriv->psc.state_inap);
572  ppsc->last_awake_jiffies = jiffies;
573  rtl_write_word(rtlpriv, CMDR, 0x37FC);
574  rtl_write_byte(rtlpriv, TXPAUSE, 0x00);
575  rtl_write_byte(rtlpriv, PHY_CCA, 0x3);
576  }
577 
578  if (mac->link_state == MAC80211_LINKED)
579  rtlpriv->cfg->ops->led_control(hw,
580  LED_CTL_LINK);
581  else
582  rtlpriv->cfg->ops->led_control(hw,
583  LED_CTL_NO_LINK);
584  break;
585  }
586  case ERFOFF:{
587  if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
588  RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
589  "IPS Set eRf nic disable\n");
590  rtl_ps_disable_nic(hw);
591  RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
592  } else {
593  if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
594  rtlpriv->cfg->ops->led_control(hw,
595  LED_CTL_NO_LINK);
596  else
597  rtlpriv->cfg->ops->led_control(hw,
598  LED_CTL_POWER_OFF);
599  }
600  break;
601  }
602  case ERFSLEEP:
603  if (ppsc->rfpwr_state == ERFOFF)
604  return false;
605 
606  for (queue_id = 0, i = 0;
607  queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
608  ring = &pcipriv->dev.tx_ring[queue_id];
609  if (skb_queue_len(&ring->queue) == 0 ||
610  queue_id == BEACON_QUEUE) {
611  queue_id++;
612  continue;
613  } else {
614  RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
615  "eRf Off/Sleep: %d times TcbBusyQueue[%d] = %d before doze!\n",
616  i + 1, queue_id,
617  skb_queue_len(&ring->queue));
618 
619  udelay(10);
620  i++;
621  }
622 
623  if (i >= MAX_DOZE_WAITING_TIMES_9x) {
624  RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
625  "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
626  MAX_DOZE_WAITING_TIMES_9x,
627  queue_id,
628  skb_queue_len(&ring->queue));
629  break;
630  }
631  }
632 
633  RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
634  "Set ERFSLEEP awaked:%d ms\n",
635  jiffies_to_msecs(jiffies -
636  ppsc->last_awake_jiffies));
637 
638  RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
639  "sleep awaked:%d ms state_inap:%x\n",
640  jiffies_to_msecs(jiffies -
641  ppsc->last_awake_jiffies),
642  rtlpriv->psc.state_inap);
643  ppsc->last_sleep_jiffies = jiffies;
644  _rtl92se_phy_set_rf_sleep(hw);
645  break;
646  default:
647  RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
648  "switch case not processed\n");
649  bresult = false;
650  break;
651  }
652 
653  if (bresult)
654  ppsc->rfpwr_state = rfpwr_state;
655 
656  return bresult;
657 }
658 
659 static bool _rtl92s_phy_config_rfpa_bias_current(struct ieee80211_hw *hw,
660  enum radio_path rfpath)
661 {
662  struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
663  bool rtstatus = true;
664  u32 tmpval = 0;
665 
666  /* If inferiority IC, we have to increase the PA bias current */
667  if (rtlhal->ic_class != IC_INFERIORITY_A) {
668  tmpval = rtl92s_phy_query_rf_reg(hw, rfpath, RF_IPA, 0xf);
669  rtl92s_phy_set_rf_reg(hw, rfpath, RF_IPA, 0xf, tmpval + 1);
670  }
671 
672  return rtstatus;
673 }
674 
675 static void _rtl92s_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
676  u32 reg_addr, u32 bitmask, u32 data)
677 {
678  struct rtl_priv *rtlpriv = rtl_priv(hw);
679  struct rtl_phy *rtlphy = &(rtlpriv->phy);
680  int index;
681 
682  if (reg_addr == RTXAGC_RATE18_06)
683  index = 0;
684  else if (reg_addr == RTXAGC_RATE54_24)
685  index = 1;
686  else if (reg_addr == RTXAGC_CCK_MCS32)
687  index = 6;
688  else if (reg_addr == RTXAGC_MCS03_MCS00)
689  index = 2;
690  else if (reg_addr == RTXAGC_MCS07_MCS04)
691  index = 3;
692  else if (reg_addr == RTXAGC_MCS11_MCS08)
693  index = 4;
694  else if (reg_addr == RTXAGC_MCS15_MCS12)
695  index = 5;
696  else
697  return;
698 
699  rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][index] = data;
700  if (index == 5)
701  rtlphy->pwrgroup_cnt++;
702 }
703 
704 static void _rtl92s_phy_init_register_definition(struct ieee80211_hw *hw)
705 {
706  struct rtl_priv *rtlpriv = rtl_priv(hw);
707  struct rtl_phy *rtlphy = &(rtlpriv->phy);
708 
709  /*RF Interface Sowrtware Control */
710  rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
711  rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
712  rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
713  rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
714 
715  /* RF Interface Readback Value */
716  rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
717  rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
718  rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
719  rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
720 
721  /* RF Interface Output (and Enable) */
722  rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
723  rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
724  rtlphy->phyreg_def[RF90_PATH_C].rfintfo = RFPGA0_XC_RFINTERFACEOE;
725  rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE;
726 
727  /* RF Interface (Output and) Enable */
728  rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
729  rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
730  rtlphy->phyreg_def[RF90_PATH_C].rfintfe = RFPGA0_XC_RFINTERFACEOE;
731  rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE;
732 
733  /* Addr of LSSI. Wirte RF register by driver */
734  rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
735  RFPGA0_XA_LSSIPARAMETER;
736  rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
737  RFPGA0_XB_LSSIPARAMETER;
738  rtlphy->phyreg_def[RF90_PATH_C].rf3wire_offset =
739  RFPGA0_XC_LSSIPARAMETER;
740  rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset =
741  RFPGA0_XD_LSSIPARAMETER;
742 
743  /* RF parameter */
744  rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
745  rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
746  rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
747  rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
748 
749  /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
750  rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
751  rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
752  rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
753  rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
754 
755  /* Tranceiver A~D HSSI Parameter-1 */
756  rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
757  rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
758  rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para1 = RFPGA0_XC_HSSIPARAMETER1;
759  rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1;
760 
761  /* Tranceiver A~D HSSI Parameter-2 */
762  rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
763  rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
764  rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para2 = RFPGA0_XC_HSSIPARAMETER2;
765  rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2;
766 
767  /* RF switch Control */
768  rtlphy->phyreg_def[RF90_PATH_A].rfswitch_control =
769  RFPGA0_XAB_SWITCHCONTROL;
770  rtlphy->phyreg_def[RF90_PATH_B].rfswitch_control =
771  RFPGA0_XAB_SWITCHCONTROL;
772  rtlphy->phyreg_def[RF90_PATH_C].rfswitch_control =
773  RFPGA0_XCD_SWITCHCONTROL;
774  rtlphy->phyreg_def[RF90_PATH_D].rfswitch_control =
775  RFPGA0_XCD_SWITCHCONTROL;
776 
777  /* AGC control 1 */
778  rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
779  rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
780  rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
781  rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
782 
783  /* AGC control 2 */
784  rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
785  rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
786  rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
787  rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
788 
789  /* RX AFE control 1 */
790  rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbalance =
791  ROFDM0_XARXIQIMBALANCE;
792  rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbalance =
793  ROFDM0_XBRXIQIMBALANCE;
794  rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbalance =
795  ROFDM0_XCRXIQIMBALANCE;
796  rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbalance =
797  ROFDM0_XDRXIQIMBALANCE;
798 
799  /* RX AFE control 1 */
800  rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
801  rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
802  rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
803  rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
804 
805  /* Tx AFE control 1 */
806  rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbalance =
807  ROFDM0_XATXIQIMBALANCE;
808  rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbalance =
809  ROFDM0_XBTXIQIMBALANCE;
810  rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbalance =
811  ROFDM0_XCTXIQIMBALANCE;
812  rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbalance =
813  ROFDM0_XDTXIQIMBALANCE;
814 
815  /* Tx AFE control 2 */
816  rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
817  rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
818  rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
819  rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
820 
821  /* Tranceiver LSSI Readback */
822  rtlphy->phyreg_def[RF90_PATH_A].rflssi_readback =
823  RFPGA0_XA_LSSIREADBACK;
824  rtlphy->phyreg_def[RF90_PATH_B].rflssi_readback =
825  RFPGA0_XB_LSSIREADBACK;
826  rtlphy->phyreg_def[RF90_PATH_C].rflssi_readback =
827  RFPGA0_XC_LSSIREADBACK;
828  rtlphy->phyreg_def[RF90_PATH_D].rflssi_readback =
829  RFPGA0_XD_LSSIREADBACK;
830 
831  /* Tranceiver LSSI Readback PI mode */
832  rtlphy->phyreg_def[RF90_PATH_A].rflssi_readbackpi =
833  TRANSCEIVERA_HSPI_READBACK;
834  rtlphy->phyreg_def[RF90_PATH_B].rflssi_readbackpi =
835  TRANSCEIVERB_HSPI_READBACK;
836 }
837 
838 
839 static bool _rtl92s_phy_config_bb(struct ieee80211_hw *hw, u8 configtype)
840 {
841  int i;
842  u32 *phy_reg_table;
843  u32 *agc_table;
844  u16 phy_reg_len, agc_len;
845 
846  agc_len = AGCTAB_ARRAYLENGTH;
847  agc_table = rtl8192seagctab_array;
848  /* Default RF_type: 2T2R */
849  phy_reg_len = PHY_REG_2T2RARRAYLENGTH;
850  phy_reg_table = rtl8192sephy_reg_2t2rarray;
851 
852  if (configtype == BASEBAND_CONFIG_PHY_REG) {
853  for (i = 0; i < phy_reg_len; i = i + 2) {
854  if (phy_reg_table[i] == 0xfe)
855  mdelay(50);
856  else if (phy_reg_table[i] == 0xfd)
857  mdelay(5);
858  else if (phy_reg_table[i] == 0xfc)
859  mdelay(1);
860  else if (phy_reg_table[i] == 0xfb)
861  udelay(50);
862  else if (phy_reg_table[i] == 0xfa)
863  udelay(5);
864  else if (phy_reg_table[i] == 0xf9)
865  udelay(1);
866 
867  /* Add delay for ECS T20 & LG malow platform, */
868  udelay(1);
869 
870  rtl92s_phy_set_bb_reg(hw, phy_reg_table[i], MASKDWORD,
871  phy_reg_table[i + 1]);
872  }
873  } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
874  for (i = 0; i < agc_len; i = i + 2) {
875  rtl92s_phy_set_bb_reg(hw, agc_table[i], MASKDWORD,
876  agc_table[i + 1]);
877 
878  /* Add delay for ECS T20 & LG malow platform */
879  udelay(1);
880  }
881  }
882 
883  return true;
884 }
885 
886 static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw *hw,
887  u8 configtype)
888 {
889  struct rtl_priv *rtlpriv = rtl_priv(hw);
890  struct rtl_phy *rtlphy = &(rtlpriv->phy);
891  u32 *phy_regarray2xtxr_table;
892  u16 phy_regarray2xtxr_len;
893  int i;
894 
895  if (rtlphy->rf_type == RF_1T1R) {
896  phy_regarray2xtxr_table = rtl8192sephy_changeto_1t1rarray;
897  phy_regarray2xtxr_len = PHY_CHANGETO_1T1RARRAYLENGTH;
898  } else if (rtlphy->rf_type == RF_1T2R) {
899  phy_regarray2xtxr_table = rtl8192sephy_changeto_1t2rarray;
900  phy_regarray2xtxr_len = PHY_CHANGETO_1T2RARRAYLENGTH;
901  } else {
902  return false;
903  }
904 
905  if (configtype == BASEBAND_CONFIG_PHY_REG) {
906  for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) {
907  if (phy_regarray2xtxr_table[i] == 0xfe)
908  mdelay(50);
909  else if (phy_regarray2xtxr_table[i] == 0xfd)
910  mdelay(5);
911  else if (phy_regarray2xtxr_table[i] == 0xfc)
912  mdelay(1);
913  else if (phy_regarray2xtxr_table[i] == 0xfb)
914  udelay(50);
915  else if (phy_regarray2xtxr_table[i] == 0xfa)
916  udelay(5);
917  else if (phy_regarray2xtxr_table[i] == 0xf9)
918  udelay(1);
919 
920  rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i],
921  phy_regarray2xtxr_table[i + 1],
922  phy_regarray2xtxr_table[i + 2]);
923  }
924  }
925 
926  return true;
927 }
928 
929 static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw *hw,
930  u8 configtype)
931 {
932  int i;
933  u32 *phy_table_pg;
934  u16 phy_pg_len;
935 
936  phy_pg_len = PHY_REG_ARRAY_PGLENGTH;
937  phy_table_pg = rtl8192sephy_reg_array_pg;
938 
939  if (configtype == BASEBAND_CONFIG_PHY_REG) {
940  for (i = 0; i < phy_pg_len; i = i + 3) {
941  if (phy_table_pg[i] == 0xfe)
942  mdelay(50);
943  else if (phy_table_pg[i] == 0xfd)
944  mdelay(5);
945  else if (phy_table_pg[i] == 0xfc)
946  mdelay(1);
947  else if (phy_table_pg[i] == 0xfb)
948  udelay(50);
949  else if (phy_table_pg[i] == 0xfa)
950  udelay(5);
951  else if (phy_table_pg[i] == 0xf9)
952  udelay(1);
953 
954  _rtl92s_store_pwrindex_diffrate_offset(hw,
955  phy_table_pg[i],
956  phy_table_pg[i + 1],
957  phy_table_pg[i + 2]);
958  rtl92s_phy_set_bb_reg(hw, phy_table_pg[i],
959  phy_table_pg[i + 1],
960  phy_table_pg[i + 2]);
961  }
962  }
963 
964  return true;
965 }
966 
967 static bool _rtl92s_phy_bb_config_parafile(struct ieee80211_hw *hw)
968 {
969  struct rtl_priv *rtlpriv = rtl_priv(hw);
970  struct rtl_phy *rtlphy = &(rtlpriv->phy);
971  struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
972  bool rtstatus = true;
973 
974  /* 1. Read PHY_REG.TXT BB INIT!! */
975  /* We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R */
976  if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_2T2R ||
977  rtlphy->rf_type == RF_1T1R || rtlphy->rf_type == RF_2T2R_GREEN) {
978  rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_PHY_REG);
979 
980  if (rtlphy->rf_type != RF_2T2R &&
981  rtlphy->rf_type != RF_2T2R_GREEN)
982  /* so we should reconfig BB reg with the right
983  * PHY parameters. */
984  rtstatus = _rtl92s_phy_set_bb_to_diff_rf(hw,
985  BASEBAND_CONFIG_PHY_REG);
986  } else {
987  rtstatus = false;
988  }
989 
990  if (!rtstatus) {
991  RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
992  "Write BB Reg Fail!!\n");
993  goto phy_BB8190_Config_ParaFile_Fail;
994  }
995 
996  /* 2. If EEPROM or EFUSE autoload OK, We must config by
997  * PHY_REG_PG.txt */
998  if (rtlefuse->autoload_failflag == false) {
999  rtlphy->pwrgroup_cnt = 0;
1000 
1001  rtstatus = _rtl92s_phy_config_bb_with_pg(hw,
1002  BASEBAND_CONFIG_PHY_REG);
1003  }
1004  if (!rtstatus) {
1005  RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1006  "_rtl92s_phy_bb_config_parafile(): BB_PG Reg Fail!!\n");
1007  goto phy_BB8190_Config_ParaFile_Fail;
1008  }
1009 
1010  /* 3. BB AGC table Initialization */
1011  rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB);
1012 
1013  if (!rtstatus) {
1014  pr_err("%s(): AGC Table Fail\n", __func__);
1015  goto phy_BB8190_Config_ParaFile_Fail;
1016  }
1017 
1018  /* Check if the CCK HighPower is turned ON. */
1019  /* This is used to calculate PWDB. */
1020  rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw,
1021  RFPGA0_XA_HSSIPARAMETER2, 0x200));
1022 
1023 phy_BB8190_Config_ParaFile_Fail:
1024  return rtstatus;
1025 }
1026 
1027 u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath)
1028 {
1029  struct rtl_priv *rtlpriv = rtl_priv(hw);
1030  struct rtl_phy *rtlphy = &(rtlpriv->phy);
1031  int i;
1032  bool rtstatus = true;
1033  u32 *radio_a_table;
1034  u32 *radio_b_table;
1035  u16 radio_a_tblen, radio_b_tblen;
1036 
1037  radio_a_tblen = RADIOA_1T_ARRAYLENGTH;
1038  radio_a_table = rtl8192seradioa_1t_array;
1039 
1040  /* Using Green mode array table for RF_2T2R_GREEN */
1041  if (rtlphy->rf_type == RF_2T2R_GREEN) {
1042  radio_b_table = rtl8192seradiob_gm_array;
1043  radio_b_tblen = RADIOB_GM_ARRAYLENGTH;
1044  } else {
1045  radio_b_table = rtl8192seradiob_array;
1046  radio_b_tblen = RADIOB_ARRAYLENGTH;
1047  }
1048 
1049  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
1050  rtstatus = true;
1051 
1052  switch (rfpath) {
1053  case RF90_PATH_A:
1054  for (i = 0; i < radio_a_tblen; i = i + 2) {
1055  if (radio_a_table[i] == 0xfe)
1056  /* Delay specific ms. Only RF configuration
1057  * requires delay. */
1058  mdelay(50);
1059  else if (radio_a_table[i] == 0xfd)
1060  mdelay(5);
1061  else if (radio_a_table[i] == 0xfc)
1062  mdelay(1);
1063  else if (radio_a_table[i] == 0xfb)
1064  udelay(50);
1065  else if (radio_a_table[i] == 0xfa)
1066  udelay(5);
1067  else if (radio_a_table[i] == 0xf9)
1068  udelay(1);
1069  else
1070  rtl92s_phy_set_rf_reg(hw, rfpath,
1071  radio_a_table[i],
1072  MASK20BITS,
1073  radio_a_table[i + 1]);
1074 
1075  /* Add delay for ECS T20 & LG malow platform */
1076  udelay(1);
1077  }
1078 
1079  /* PA Bias current for inferiority IC */
1080  _rtl92s_phy_config_rfpa_bias_current(hw, rfpath);
1081  break;
1082  case RF90_PATH_B:
1083  for (i = 0; i < radio_b_tblen; i = i + 2) {
1084  if (radio_b_table[i] == 0xfe)
1085  /* Delay specific ms. Only RF configuration
1086  * requires delay.*/
1087  mdelay(50);
1088  else if (radio_b_table[i] == 0xfd)
1089  mdelay(5);
1090  else if (radio_b_table[i] == 0xfc)
1091  mdelay(1);
1092  else if (radio_b_table[i] == 0xfb)
1093  udelay(50);
1094  else if (radio_b_table[i] == 0xfa)
1095  udelay(5);
1096  else if (radio_b_table[i] == 0xf9)
1097  udelay(1);
1098  else
1099  rtl92s_phy_set_rf_reg(hw, rfpath,
1100  radio_b_table[i],
1101  MASK20BITS,
1102  radio_b_table[i + 1]);
1103 
1104  /* Add delay for ECS T20 & LG malow platform */
1105  udelay(1);
1106  }
1107  break;
1108  case RF90_PATH_C:
1109  ;
1110  break;
1111  case RF90_PATH_D:
1112  ;
1113  break;
1114  default:
1115  break;
1116  }
1117 
1118  return rtstatus;
1119 }
1120 
1121 
1122 bool rtl92s_phy_mac_config(struct ieee80211_hw *hw)
1123 {
1124  struct rtl_priv *rtlpriv = rtl_priv(hw);
1125  u32 i;
1126  u32 arraylength;
1127  u32 *ptraArray;
1128 
1129  arraylength = MAC_2T_ARRAYLENGTH;
1130  ptraArray = rtl8192semac_2t_array;
1131 
1132  for (i = 0; i < arraylength; i = i + 2)
1133  rtl_write_byte(rtlpriv, ptraArray[i], (u8)ptraArray[i + 1]);
1134 
1135  return true;
1136 }
1137 
1138 
1139 bool rtl92s_phy_bb_config(struct ieee80211_hw *hw)
1140 {
1141  struct rtl_priv *rtlpriv = rtl_priv(hw);
1142  struct rtl_phy *rtlphy = &(rtlpriv->phy);
1143  bool rtstatus = true;
1144  u8 pathmap, index, rf_num = 0;
1145  u8 path1, path2;
1146 
1147  _rtl92s_phy_init_register_definition(hw);
1148 
1149  /* Config BB and AGC */
1150  rtstatus = _rtl92s_phy_bb_config_parafile(hw);
1151 
1152 
1153  /* Check BB/RF confiuration setting. */
1154  /* We only need to configure RF which is turned on. */
1155  path1 = (u8)(rtl92s_phy_query_bb_reg(hw, RFPGA0_TXINFO, 0xf));
1156  mdelay(10);
1157  path2 = (u8)(rtl92s_phy_query_bb_reg(hw, ROFDM0_TRXPATHENABLE, 0xf));
1158  pathmap = path1 | path2;
1159 
1160  rtlphy->rf_pathmap = pathmap;
1161  for (index = 0; index < 4; index++) {
1162  if ((pathmap >> index) & 0x1)
1163  rf_num++;
1164  }
1165 
1166  if ((rtlphy->rf_type == RF_1T1R && rf_num != 1) ||
1167  (rtlphy->rf_type == RF_1T2R && rf_num != 2) ||
1168  (rtlphy->rf_type == RF_2T2R && rf_num != 2) ||
1169  (rtlphy->rf_type == RF_2T2R_GREEN && rf_num != 2)) {
1170  RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1171  "RF_Type(%x) does not match RF_Num(%x)!!\n",
1172  rtlphy->rf_type, rf_num);
1173  RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1174  "path1 0x%x, path2 0x%x, pathmap 0x%x\n",
1175  path1, path2, pathmap);
1176  }
1177 
1178  return rtstatus;
1179 }
1180 
1181 bool rtl92s_phy_rf_config(struct ieee80211_hw *hw)
1182 {
1183  struct rtl_priv *rtlpriv = rtl_priv(hw);
1184  struct rtl_phy *rtlphy = &(rtlpriv->phy);
1185 
1186  /* Initialize general global value */
1187  if (rtlphy->rf_type == RF_1T1R)
1188  rtlphy->num_total_rfpath = 1;
1189  else
1190  rtlphy->num_total_rfpath = 2;
1191 
1192  /* Config BB and RF */
1193  return rtl92s_phy_rf6052_config(hw);
1194 }
1195 
1196 void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1197 {
1198  struct rtl_priv *rtlpriv = rtl_priv(hw);
1199  struct rtl_phy *rtlphy = &(rtlpriv->phy);
1200 
1201  /* read rx initial gain */
1202  rtlphy->default_initialgain[0] = rtl_get_bbreg(hw,
1203  ROFDM0_XAAGCCORE1, MASKBYTE0);
1204  rtlphy->default_initialgain[1] = rtl_get_bbreg(hw,
1205  ROFDM0_XBAGCCORE1, MASKBYTE0);
1206  rtlphy->default_initialgain[2] = rtl_get_bbreg(hw,
1207  ROFDM0_XCAGCCORE1, MASKBYTE0);
1208  rtlphy->default_initialgain[3] = rtl_get_bbreg(hw,
1209  ROFDM0_XDAGCCORE1, MASKBYTE0);
1210  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1211  "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
1212  rtlphy->default_initialgain[0],
1213  rtlphy->default_initialgain[1],
1214  rtlphy->default_initialgain[2],
1215  rtlphy->default_initialgain[3]);
1216 
1217  /* read framesync */
1218  rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0);
1219  rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
1220  MASKDWORD);
1221  RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1222  "Default framesync (0x%x) = 0x%x\n",
1223  ROFDM0_RXDETECTOR3, rtlphy->framesync);
1224 
1225 }
1226 
1227 static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1228  u8 *cckpowerlevel, u8 *ofdmpowerLevel)
1229 {
1230  struct rtl_priv *rtlpriv = rtl_priv(hw);
1231  struct rtl_phy *rtlphy = &(rtlpriv->phy);
1232  struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1233  u8 index = (channel - 1);
1234 
1235  /* 1. CCK */
1236  /* RF-A */
1237  cckpowerlevel[0] = rtlefuse->txpwrlevel_cck[0][index];
1238  /* RF-B */
1239  cckpowerlevel[1] = rtlefuse->txpwrlevel_cck[1][index];
1240 
1241  /* 2. OFDM for 1T or 2T */
1242  if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
1243  /* Read HT 40 OFDM TX power */
1244  ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index];
1245  ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index];
1246  } else if (rtlphy->rf_type == RF_2T2R) {
1247  /* Read HT 40 OFDM TX power */
1248  ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index];
1249  ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index];
1250  } else {
1251  ofdmpowerLevel[0] = 0;
1252  ofdmpowerLevel[1] = 0;
1253  }
1254 }
1255 
1256 static void _rtl92s_phy_ccxpower_indexcheck(struct ieee80211_hw *hw,
1257  u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1258 {
1259  struct rtl_priv *rtlpriv = rtl_priv(hw);
1260  struct rtl_phy *rtlphy = &(rtlpriv->phy);
1261 
1262  rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
1263  rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
1264 }
1265 
1266 void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel)
1267 {
1268  struct rtl_priv *rtlpriv = rtl_priv(hw);
1269  struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1270  /* [0]:RF-A, [1]:RF-B */
1271  u8 cckpowerlevel[2], ofdmpowerLevel[2];
1272 
1273  if (!rtlefuse->txpwr_fromeprom)
1274  return;
1275 
1276  /* Mainly we use RF-A Tx Power to write the Tx Power registers,
1277  * but the RF-B Tx Power must be calculated by the antenna diff.
1278  * So we have to rewrite Antenna gain offset register here.
1279  * Please refer to BB register 0x80c
1280  * 1. For CCK.
1281  * 2. For OFDM 1T or 2T */
1282  _rtl92s_phy_get_txpower_index(hw, channel, &cckpowerlevel[0],
1283  &ofdmpowerLevel[0]);
1284 
1285  RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1286  "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
1287  channel, cckpowerlevel[0], cckpowerlevel[1],
1288  ofdmpowerLevel[0], ofdmpowerLevel[1]);
1289 
1290  _rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0],
1291  &ofdmpowerLevel[0]);
1292 
1293  rtl92s_phy_rf6052_set_ccktxpower(hw, cckpowerlevel[0]);
1294  rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerLevel[0], channel);
1295 
1296 }
1297 
1298 void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw)
1299 {
1300  struct rtl_priv *rtlpriv = rtl_priv(hw);
1301  u16 pollingcnt = 10000;
1302  u32 tmpvalue;
1303 
1304  /* Make sure that CMD IO has be accepted by FW. */
1305  do {
1306  udelay(10);
1307 
1308  tmpvalue = rtl_read_dword(rtlpriv, WFM5);
1309  if (tmpvalue == 0)
1310  break;
1311  } while (--pollingcnt);
1312 
1313  if (pollingcnt == 0)
1314  RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Set FW Cmd fail!!\n");
1315 }
1316 
1317 
1318 static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw)
1319 {
1320  struct rtl_priv *rtlpriv = rtl_priv(hw);
1321  struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1322  struct rtl_phy *rtlphy = &(rtlpriv->phy);
1323  u32 input, current_aid = 0;
1324 
1325  if (is_hal_stop(rtlhal))
1326  return;
1327 
1328  /* We re-map RA related CMD IO to combinational ones */
1329  /* if FW version is v.52 or later. */
1330  switch (rtlhal->current_fwcmd_io) {
1331  case FW_CMD_RA_REFRESH_N:
1332  rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_N_COMB;
1333  break;
1334  case FW_CMD_RA_REFRESH_BG:
1335  rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_BG_COMB;
1336  break;
1337  default:
1338  break;
1339  }
1340 
1341  switch (rtlhal->current_fwcmd_io) {
1342  case FW_CMD_RA_RESET:
1343  RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_RESET\n");
1344  rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1345  rtl92s_phy_chk_fwcmd_iodone(hw);
1346  break;
1347  case FW_CMD_RA_ACTIVE:
1348  RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_ACTIVE\n");
1349  rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1350  rtl92s_phy_chk_fwcmd_iodone(hw);
1351  break;
1352  case FW_CMD_RA_REFRESH_N:
1353  RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_REFRESH_N\n");
1354  input = FW_RA_REFRESH;
1355  rtl_write_dword(rtlpriv, WFM5, input);
1356  rtl92s_phy_chk_fwcmd_iodone(hw);
1357  rtl_write_dword(rtlpriv, WFM5, FW_RA_ENABLE_RSSI_MASK);
1358  rtl92s_phy_chk_fwcmd_iodone(hw);
1359  break;
1360  case FW_CMD_RA_REFRESH_BG:
1361  RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1362  "FW_CMD_RA_REFRESH_BG\n");
1363  rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1364  rtl92s_phy_chk_fwcmd_iodone(hw);
1365  rtl_write_dword(rtlpriv, WFM5, FW_RA_DISABLE_RSSI_MASK);
1366  rtl92s_phy_chk_fwcmd_iodone(hw);
1367  break;
1368  case FW_CMD_RA_REFRESH_N_COMB:
1369  RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1370  "FW_CMD_RA_REFRESH_N_COMB\n");
1371  input = FW_RA_IOT_N_COMB;
1372  rtl_write_dword(rtlpriv, WFM5, input);
1373  rtl92s_phy_chk_fwcmd_iodone(hw);
1374  break;
1375  case FW_CMD_RA_REFRESH_BG_COMB:
1376  RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1377  "FW_CMD_RA_REFRESH_BG_COMB\n");
1378  input = FW_RA_IOT_BG_COMB;
1379  rtl_write_dword(rtlpriv, WFM5, input);
1380  rtl92s_phy_chk_fwcmd_iodone(hw);
1381  break;
1382  case FW_CMD_IQK_ENABLE:
1383  RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_IQK_ENABLE\n");
1384  rtl_write_dword(rtlpriv, WFM5, FW_IQK_ENABLE);
1385  rtl92s_phy_chk_fwcmd_iodone(hw);
1386  break;
1387  case FW_CMD_PAUSE_DM_BY_SCAN:
1388  /* Lower initial gain */
1389  rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1390  rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1391  /* CCA threshold */
1392  rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1393  break;
1394  case FW_CMD_RESUME_DM_BY_SCAN:
1395  /* CCA threshold */
1396  rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1397  rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1398  break;
1399  case FW_CMD_HIGH_PWR_DISABLE:
1400  if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE)
1401  break;
1402 
1403  /* Lower initial gain */
1404  rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1405  rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1406  /* CCA threshold */
1407  rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1408  break;
1409  case FW_CMD_HIGH_PWR_ENABLE:
1410  if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1411  rtlpriv->dm.dynamic_txpower_enable)
1412  break;
1413 
1414  /* CCA threshold */
1415  rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1416  break;
1417  case FW_CMD_LPS_ENTER:
1418  RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_ENTER\n");
1419  current_aid = rtlpriv->mac80211.assoc_id;
1420  rtl_write_dword(rtlpriv, WFM5, (FW_LPS_ENTER |
1421  ((current_aid | 0xc000) << 8)));
1422  rtl92s_phy_chk_fwcmd_iodone(hw);
1423  /* FW set TXOP disable here, so disable EDCA
1424  * turbo mode until driver leave LPS */
1425  break;
1426  case FW_CMD_LPS_LEAVE:
1427  RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_LEAVE\n");
1428  rtl_write_dword(rtlpriv, WFM5, FW_LPS_LEAVE);
1429  rtl92s_phy_chk_fwcmd_iodone(hw);
1430  break;
1431  case FW_CMD_ADD_A2_ENTRY:
1432  RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_ADD_A2_ENTRY\n");
1433  rtl_write_dword(rtlpriv, WFM5, FW_ADD_A2_ENTRY);
1434  rtl92s_phy_chk_fwcmd_iodone(hw);
1435  break;
1436  case FW_CMD_CTRL_DM_BY_DRIVER:
1437  RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1438  "FW_CMD_CTRL_DM_BY_DRIVER\n");
1439  rtl_write_dword(rtlpriv, WFM5, FW_CTRL_DM_BY_DRIVER);
1440  rtl92s_phy_chk_fwcmd_iodone(hw);
1441  break;
1442 
1443  default:
1444  break;
1445  }
1446 
1447  rtl92s_phy_chk_fwcmd_iodone(hw);
1448 
1449  /* Clear FW CMD operation flag. */
1450  rtlhal->set_fwcmd_inprogress = false;
1451 }
1452 
1453 bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
1454 {
1455  struct rtl_priv *rtlpriv = rtl_priv(hw);
1456  struct dig_t *digtable = &rtlpriv->dm_digtable;
1457  struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1458  struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1459  u32 fw_param = FW_CMD_IO_PARA_QUERY(rtlpriv);
1460  u16 fw_cmdmap = FW_CMD_IO_QUERY(rtlpriv);
1461  bool bPostProcessing = false;
1462 
1463  RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1464  "Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n",
1465  fw_cmdio, rtlhal->set_fwcmd_inprogress);
1466 
1467  do {
1468  /* We re-map to combined FW CMD ones if firmware version */
1469  /* is v.53 or later. */
1470  switch (fw_cmdio) {
1471  case FW_CMD_RA_REFRESH_N:
1472  fw_cmdio = FW_CMD_RA_REFRESH_N_COMB;
1473  break;
1474  case FW_CMD_RA_REFRESH_BG:
1475  fw_cmdio = FW_CMD_RA_REFRESH_BG_COMB;
1476  break;
1477  default:
1478  break;
1479  }
1480 
1481  /* If firmware version is v.62 or later,
1482  * use FW_CMD_IO_SET for FW_CMD_CTRL_DM_BY_DRIVER */
1483  if (hal_get_firmwareversion(rtlpriv) >= 0x3E) {
1484  if (fw_cmdio == FW_CMD_CTRL_DM_BY_DRIVER)
1485  fw_cmdio = FW_CMD_CTRL_DM_BY_DRIVER_NEW;
1486  }
1487 
1488 
1489  /* We shall revise all FW Cmd IO into Reg0x364
1490  * DM map table in the future. */
1491  switch (fw_cmdio) {
1492  case FW_CMD_RA_INIT:
1493  RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "RA init!!\n");
1494  fw_cmdmap |= FW_RA_INIT_CTL;
1495  FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1496  /* Clear control flag to sync with FW. */
1497  FW_CMD_IO_CLR(rtlpriv, FW_RA_INIT_CTL);
1498  break;
1499  case FW_CMD_DIG_DISABLE:
1500  RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1501  "Set DIG disable!!\n");
1502  fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1503  FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1504  break;
1505  case FW_CMD_DIG_ENABLE:
1506  case FW_CMD_DIG_RESUME:
1507  if (!(rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE)) {
1508  RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1509  "Set DIG enable or resume!!\n");
1510  fw_cmdmap |= (FW_DIG_ENABLE_CTL | FW_SS_CTL);
1511  FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1512  }
1513  break;
1514  case FW_CMD_DIG_HALT:
1515  RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1516  "Set DIG halt!!\n");
1517  fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | FW_SS_CTL);
1518  FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1519  break;
1520  case FW_CMD_TXPWR_TRACK_THERMAL: {
1521  u8 thermalval = 0;
1522  fw_cmdmap |= FW_PWR_TRK_CTL;
1523 
1524  /* Clear FW parameter in terms of thermal parts. */
1525  fw_param &= FW_PWR_TRK_PARAM_CLR;
1526 
1527  thermalval = rtlpriv->dm.thermalvalue;
1528  fw_param |= ((thermalval << 24) |
1529  (rtlefuse->thermalmeter[0] << 16));
1530 
1531  RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1532  "Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n",
1533  fw_cmdmap, fw_param);
1534 
1535  FW_CMD_PARA_SET(rtlpriv, fw_param);
1536  FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1537 
1538  /* Clear control flag to sync with FW. */
1539  FW_CMD_IO_CLR(rtlpriv, FW_PWR_TRK_CTL);
1540  }
1541  break;
1542  /* The following FW CMDs are only compatible to
1543  * v.53 or later. */
1544  case FW_CMD_RA_REFRESH_N_COMB:
1545  fw_cmdmap |= FW_RA_N_CTL;
1546 
1547  /* Clear RA BG mode control. */
1548  fw_cmdmap &= ~(FW_RA_BG_CTL | FW_RA_INIT_CTL);
1549 
1550  /* Clear FW parameter in terms of RA parts. */
1551  fw_param &= FW_RA_PARAM_CLR;
1552 
1553  RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1554  "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n",
1555  fw_cmdmap, fw_param);
1556 
1557  FW_CMD_PARA_SET(rtlpriv, fw_param);
1558  FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1559 
1560  /* Clear control flag to sync with FW. */
1561  FW_CMD_IO_CLR(rtlpriv, FW_RA_N_CTL);
1562  break;
1563  case FW_CMD_RA_REFRESH_BG_COMB:
1564  fw_cmdmap |= FW_RA_BG_CTL;
1565 
1566  /* Clear RA n-mode control. */
1567  fw_cmdmap &= ~(FW_RA_N_CTL | FW_RA_INIT_CTL);
1568  /* Clear FW parameter in terms of RA parts. */
1569  fw_param &= FW_RA_PARAM_CLR;
1570 
1571  FW_CMD_PARA_SET(rtlpriv, fw_param);
1572  FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1573 
1574  /* Clear control flag to sync with FW. */
1575  FW_CMD_IO_CLR(rtlpriv, FW_RA_BG_CTL);
1576  break;
1577  case FW_CMD_IQK_ENABLE:
1578  fw_cmdmap |= FW_IQK_CTL;
1579  FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1580  /* Clear control flag to sync with FW. */
1581  FW_CMD_IO_CLR(rtlpriv, FW_IQK_CTL);
1582  break;
1583  /* The following FW CMD is compatible to v.62 or later. */
1584  case FW_CMD_CTRL_DM_BY_DRIVER_NEW:
1585  fw_cmdmap |= FW_DRIVER_CTRL_DM_CTL;
1586  FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1587  break;
1588  /* The followed FW Cmds needs post-processing later. */
1589  case FW_CMD_RESUME_DM_BY_SCAN:
1590  fw_cmdmap |= (FW_DIG_ENABLE_CTL |
1591  FW_HIGH_PWR_ENABLE_CTL |
1592  FW_SS_CTL);
1593 
1594  if (rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE ||
1595  !digtable->dig_enable_flag)
1596  fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1597 
1598  if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1599  rtlpriv->dm.dynamic_txpower_enable)
1600  fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1601 
1602  if ((digtable->dig_ext_port_stage ==
1603  DIG_EXT_PORT_STAGE_0) ||
1604  (digtable->dig_ext_port_stage ==
1605  DIG_EXT_PORT_STAGE_1))
1606  fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1607 
1608  FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1609  bPostProcessing = true;
1610  break;
1611  case FW_CMD_PAUSE_DM_BY_SCAN:
1612  fw_cmdmap &= ~(FW_DIG_ENABLE_CTL |
1613  FW_HIGH_PWR_ENABLE_CTL |
1614  FW_SS_CTL);
1615  FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1616  bPostProcessing = true;
1617  break;
1618  case FW_CMD_HIGH_PWR_DISABLE:
1619  fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1620  FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1621  bPostProcessing = true;
1622  break;
1623  case FW_CMD_HIGH_PWR_ENABLE:
1624  if (!(rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) &&
1625  !rtlpriv->dm.dynamic_txpower_enable) {
1626  fw_cmdmap |= (FW_HIGH_PWR_ENABLE_CTL |
1627  FW_SS_CTL);
1628  FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1629  bPostProcessing = true;
1630  }
1631  break;
1632  case FW_CMD_DIG_MODE_FA:
1633  fw_cmdmap |= FW_FA_CTL;
1634  FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1635  break;
1636  case FW_CMD_DIG_MODE_SS:
1637  fw_cmdmap &= ~FW_FA_CTL;
1638  FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1639  break;
1640  case FW_CMD_PAPE_CONTROL:
1641  RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1642  "[FW CMD] Set PAPE Control\n");
1643  fw_cmdmap &= ~FW_PAPE_CTL_BY_SW_HW;
1644 
1645  FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1646  break;
1647  default:
1648  /* Pass to original FW CMD processing callback
1649  * routine. */
1650  bPostProcessing = true;
1651  break;
1652  }
1653  } while (false);
1654 
1655  /* We shall post processing these FW CMD if
1656  * variable bPostProcessing is set. */
1657  if (bPostProcessing && !rtlhal->set_fwcmd_inprogress) {
1658  rtlhal->set_fwcmd_inprogress = true;
1659  /* Update current FW Cmd for callback use. */
1660  rtlhal->current_fwcmd_io = fw_cmdio;
1661  } else {
1662  return false;
1663  }
1664 
1665  _rtl92s_phy_set_fwcmd_io(hw);
1666  return true;
1667 }
1668 
1669 static void _rtl92s_phy_check_ephy_switchready(struct ieee80211_hw *hw)
1670 {
1671  struct rtl_priv *rtlpriv = rtl_priv(hw);
1672  u32 delay = 100;
1673  u8 regu1;
1674 
1675  regu1 = rtl_read_byte(rtlpriv, 0x554);
1676  while ((regu1 & BIT(5)) && (delay > 0)) {
1677  regu1 = rtl_read_byte(rtlpriv, 0x554);
1678  delay--;
1679  /* We delay only 50us to prevent
1680  * being scheduled out. */
1681  udelay(50);
1682  }
1683 }
1684 
1685 void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw)
1686 {
1687  struct rtl_priv *rtlpriv = rtl_priv(hw);
1688  struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1689 
1690  /* The way to be capable to switch clock request
1691  * when the PG setting does not support clock request.
1692  * This is the backdoor solution to switch clock
1693  * request before ASPM or D3. */
1694  rtl_write_dword(rtlpriv, 0x540, 0x73c11);
1695  rtl_write_dword(rtlpriv, 0x548, 0x2407c);
1696 
1697  /* Switch EPHY parameter!!!! */
1698  rtl_write_word(rtlpriv, 0x550, 0x1000);
1699  rtl_write_byte(rtlpriv, 0x554, 0x20);
1700  _rtl92s_phy_check_ephy_switchready(hw);
1701 
1702  rtl_write_word(rtlpriv, 0x550, 0xa0eb);
1703  rtl_write_byte(rtlpriv, 0x554, 0x3e);
1704  _rtl92s_phy_check_ephy_switchready(hw);
1705 
1706  rtl_write_word(rtlpriv, 0x550, 0xff80);
1707  rtl_write_byte(rtlpriv, 0x554, 0x39);
1708  _rtl92s_phy_check_ephy_switchready(hw);
1709 
1710  /* Delay L1 enter time */
1711  if (ppsc->support_aspm && !ppsc->support_backdoor)
1712  rtl_write_byte(rtlpriv, 0x560, 0x40);
1713  else
1714  rtl_write_byte(rtlpriv, 0x560, 0x00);
1715 
1716 }
1717 
1718 void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 BeaconInterval)
1719 {
1720  struct rtl_priv *rtlpriv = rtl_priv(hw);
1721  rtl_write_dword(rtlpriv, WFM5, 0xF1000000 | (BeaconInterval << 8));
1722 }
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