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io_apic.c
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1 /*
2  * Intel IO-APIC support for multi-Pentium hosts.
3  *
4  * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5  *
6  * Many thanks to Stig Venaas for trying out countless experimental
7  * patches and reporting/debugging problems patiently!
8  *
9  * (c) 1999, Multiple IO-APIC support, developed by
10  * Ken-ichi Yaku <[email protected]> and
11  * Hidemi Kishimoto <[email protected]>,
12  * further tested and cleaned up by Zach Brown <[email protected]>
13  * and Ingo Molnar <[email protected]>
14  *
15  * Fixes
16  * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17  * thanks to Eric Gilmore
18  * and Rolf G. Tews
19  * for testing these extensively
20  * Paul Diefenbaugh : Added full ACPI support
21  */
22 
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
40 #ifdef CONFIG_ACPI
41 #include <acpi/acpi_bus.h>
42 #endif
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
46 
47 #include <asm/idle.h>
48 #include <asm/io.h>
49 #include <asm/smp.h>
50 #include <asm/cpu.h>
51 #include <asm/desc.h>
52 #include <asm/proto.h>
53 #include <asm/acpi.h>
54 #include <asm/dma.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
61 #include <asm/hpet.h>
62 #include <asm/hw_irq.h>
63 
64 #include <asm/apic.h>
65 
66 #define __apicdebuginit(type) static type __init
67 
68 #define for_each_irq_pin(entry, head) \
69  for (entry = head; entry; entry = entry->next)
70 
71 #ifdef CONFIG_IRQ_REMAP
72 static void irq_remap_modify_chip_defaults(struct irq_chip *chip);
73 static inline bool irq_remapped(struct irq_cfg *cfg)
74 {
75  return cfg->irq_2_iommu.iommu != NULL;
76 }
77 #else
78 static inline bool irq_remapped(struct irq_cfg *cfg)
79 {
80  return false;
81 }
82 static inline void irq_remap_modify_chip_defaults(struct irq_chip *chip)
83 {
84 }
85 #endif
86 
87 /*
88  * Is the SiS APIC rmw bug present ?
89  * -1 = don't know, 0 = no, 1 = yes
90  */
91 int sis_apic_bug = -1;
92 
93 static DEFINE_RAW_SPINLOCK(ioapic_lock);
94 static DEFINE_RAW_SPINLOCK(vector_lock);
95 
96 static struct ioapic {
97  /*
98  * # of IRQ routing registers
99  */
100  int nr_registers;
101  /*
102  * Saved state during suspend/resume, or while enabling intr-remap.
103  */
104  struct IO_APIC_route_entry *saved_registers;
105  /* I/O APIC config */
106  struct mpc_ioapic mp_config;
107  /* IO APIC gsi routing info */
108  struct mp_ioapic_gsi gsi_config;
109  DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
110 } ioapics[MAX_IO_APICS];
111 
112 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
113 
114 int mpc_ioapic_id(int ioapic_idx)
115 {
116  return ioapics[ioapic_idx].mp_config.apicid;
117 }
118 
119 unsigned int mpc_ioapic_addr(int ioapic_idx)
120 {
121  return ioapics[ioapic_idx].mp_config.apicaddr;
122 }
123 
124 struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
125 {
126  return &ioapics[ioapic_idx].gsi_config;
127 }
128 
130 
131 /* The one past the highest gsi number used */
133 
134 /* MP IRQ source entries */
136 
137 /* # of MP IRQ source entries */
139 
140 /* GSI interrupts */
141 static int nr_irqs_gsi = NR_IRQS_LEGACY;
142 
143 #ifdef CONFIG_EISA
144 int mp_bus_id_to_type[MAX_MP_BUSSES];
145 #endif
146 
147 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
148 
150 
155 {
156 #ifdef CONFIG_PCI
157  noioapicquirk = 1;
158  noioapicreroute = -1;
159 #endif
160  skip_ioapic_setup = 1;
161 }
162 
163 static int __init parse_noapic(char *str)
164 {
165  /* disable IO-APIC */
167  return 0;
168 }
169 early_param("noapic", parse_noapic);
170 
171 static int io_apic_setup_irq_pin(unsigned int irq, int node,
172  struct io_apic_irq_attr *attr);
173 
174 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
175 void mp_save_irq(struct mpc_intsrc *m)
176 {
177  int i;
178 
179  apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
180  " IRQ %02x, APIC ID %x, APIC INT %02x\n",
181  m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
182  m->srcbusirq, m->dstapic, m->dstirq);
183 
184  for (i = 0; i < mp_irq_entries; i++) {
185  if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
186  return;
187  }
188 
189  memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
190  if (++mp_irq_entries == MAX_IRQ_SOURCES)
191  panic("Max # of irq sources exceeded!!\n");
192 }
193 
194 struct irq_pin_list {
195  int apic, pin;
197 };
198 
199 static struct irq_pin_list *alloc_irq_pin_list(int node)
200 {
201  return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
202 }
203 
204 
205 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
206 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
207 
209 {
210  struct irq_cfg *cfg;
211  int count, node, i;
212 
214  io_apic_irqs = ~0UL;
215 
216  for (i = 0; i < nr_ioapics; i++) {
217  ioapics[i].saved_registers =
218  kzalloc(sizeof(struct IO_APIC_route_entry) *
219  ioapics[i].nr_registers, GFP_KERNEL);
220  if (!ioapics[i].saved_registers)
221  pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
222  }
223 
224  cfg = irq_cfgx;
225  count = ARRAY_SIZE(irq_cfgx);
226  node = cpu_to_node(0);
227 
228  /* Make sure the legacy interrupts are marked in the bitmap */
230 
231  for (i = 0; i < count; i++) {
232  irq_set_chip_data(i, &cfg[i]);
233  zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
234  zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
235  /*
236  * For legacy IRQ's, start with assigning irq0 to irq15 to
237  * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
238  */
239  if (i < legacy_pic->nr_legacy_irqs) {
240  cfg[i].vector = IRQ0_VECTOR + i;
241  cpumask_set_cpu(0, cfg[i].domain);
242  }
243  }
244 
245  return 0;
246 }
247 
248 static struct irq_cfg *irq_cfg(unsigned int irq)
249 {
250  return irq_get_chip_data(irq);
251 }
252 
253 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
254 {
255  struct irq_cfg *cfg;
256 
257  cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
258  if (!cfg)
259  return NULL;
260  if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
261  goto out_cfg;
262  if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
263  goto out_domain;
264  return cfg;
265 out_domain:
266  free_cpumask_var(cfg->domain);
267 out_cfg:
268  kfree(cfg);
269  return NULL;
270 }
271 
272 static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
273 {
274  if (!cfg)
275  return;
276  irq_set_chip_data(at, NULL);
277  free_cpumask_var(cfg->domain);
278  free_cpumask_var(cfg->old_domain);
279  kfree(cfg);
280 }
281 
282 static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
283 {
284  int res = irq_alloc_desc_at(at, node);
285  struct irq_cfg *cfg;
286 
287  if (res < 0) {
288  if (res != -EEXIST)
289  return NULL;
290  cfg = irq_get_chip_data(at);
291  if (cfg)
292  return cfg;
293  }
294 
295  cfg = alloc_irq_cfg(at, node);
296  if (cfg)
297  irq_set_chip_data(at, cfg);
298  else
299  irq_free_desc(at);
300  return cfg;
301 }
302 
303 static int alloc_irq_from(unsigned int from, int node)
304 {
305  return irq_alloc_desc_from(from, node);
306 }
307 
308 static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
309 {
310  free_irq_cfg(at, cfg);
311  irq_free_desc(at);
312 }
313 
314 
315 struct io_apic {
316  unsigned int index;
317  unsigned int unused[3];
318  unsigned int data;
319  unsigned int unused2[11];
320  unsigned int eoi;
321 };
322 
323 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
324 {
325  return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
326  + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
327 }
328 
329 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
330 {
331  struct io_apic __iomem *io_apic = io_apic_base(apic);
332  writel(vector, &io_apic->eoi);
333 }
334 
335 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
336 {
337  struct io_apic __iomem *io_apic = io_apic_base(apic);
338  writel(reg, &io_apic->index);
339  return readl(&io_apic->data);
340 }
341 
342 void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
343 {
344  struct io_apic __iomem *io_apic = io_apic_base(apic);
345 
346  writel(reg, &io_apic->index);
347  writel(value, &io_apic->data);
348 }
349 
350 /*
351  * Re-write a value: to be used for read-modify-write
352  * cycles where the read already set up the index register.
353  *
354  * Older SiS APIC requires we rewrite the index register
355  */
356 void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
357 {
358  struct io_apic __iomem *io_apic = io_apic_base(apic);
359 
360  if (sis_apic_bug)
361  writel(reg, &io_apic->index);
362  writel(value, &io_apic->data);
363 }
364 
365 union entry_union {
366  struct { u32 w1, w2; };
368 };
369 
370 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
371 {
372  union entry_union eu;
373 
374  eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
375  eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
376 
377  return eu.entry;
378 }
379 
380 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
381 {
382  union entry_union eu;
383  unsigned long flags;
384 
385  raw_spin_lock_irqsave(&ioapic_lock, flags);
386  eu.entry = __ioapic_read_entry(apic, pin);
387  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
388 
389  return eu.entry;
390 }
391 
392 /*
393  * When we write a new IO APIC routing entry, we need to write the high
394  * word first! If the mask bit in the low word is clear, we will enable
395  * the interrupt, and we need to make sure the entry is fully populated
396  * before that happens.
397  */
398 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
399 {
400  union entry_union eu = {{0, 0}};
401 
402  eu.entry = e;
403  io_apic_write(apic, 0x11 + 2*pin, eu.w2);
404  io_apic_write(apic, 0x10 + 2*pin, eu.w1);
405 }
406 
407 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
408 {
409  unsigned long flags;
410 
411  raw_spin_lock_irqsave(&ioapic_lock, flags);
412  __ioapic_write_entry(apic, pin, e);
413  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
414 }
415 
416 /*
417  * When we mask an IO APIC routing entry, we need to write the low
418  * word first, in order to set the mask bit before we change the
419  * high bits!
420  */
421 static void ioapic_mask_entry(int apic, int pin)
422 {
423  unsigned long flags;
424  union entry_union eu = { .entry.mask = 1 };
425 
426  raw_spin_lock_irqsave(&ioapic_lock, flags);
427  io_apic_write(apic, 0x10 + 2*pin, eu.w1);
428  io_apic_write(apic, 0x11 + 2*pin, eu.w2);
429  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
430 }
431 
432 /*
433  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
434  * shared ISA-space IRQs, so we have to support them. We are super
435  * fast in the common case, and fast for shared ISA-space IRQs.
436  */
437 static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
438 {
439  struct irq_pin_list **last, *entry;
440 
441  /* don't allow duplicates */
442  last = &cfg->irq_2_pin;
443  for_each_irq_pin(entry, cfg->irq_2_pin) {
444  if (entry->apic == apic && entry->pin == pin)
445  return 0;
446  last = &entry->next;
447  }
448 
449  entry = alloc_irq_pin_list(node);
450  if (!entry) {
451  pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
452  node, apic, pin);
453  return -ENOMEM;
454  }
455  entry->apic = apic;
456  entry->pin = pin;
457 
458  *last = entry;
459  return 0;
460 }
461 
462 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
463 {
464  if (__add_pin_to_irq_node(cfg, node, apic, pin))
465  panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
466 }
467 
468 /*
469  * Reroute an IRQ to a different pin.
470  */
471 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
472  int oldapic, int oldpin,
473  int newapic, int newpin)
474 {
475  struct irq_pin_list *entry;
476 
477  for_each_irq_pin(entry, cfg->irq_2_pin) {
478  if (entry->apic == oldapic && entry->pin == oldpin) {
479  entry->apic = newapic;
480  entry->pin = newpin;
481  /* every one is different, right? */
482  return;
483  }
484  }
485 
486  /* old apic/pin didn't exist, so just add new ones */
487  add_pin_to_irq_node(cfg, node, newapic, newpin);
488 }
489 
490 static void __io_apic_modify_irq(struct irq_pin_list *entry,
491  int mask_and, int mask_or,
492  void (*final)(struct irq_pin_list *entry))
493 {
494  unsigned int reg, pin;
495 
496  pin = entry->pin;
497  reg = io_apic_read(entry->apic, 0x10 + pin * 2);
498  reg &= mask_and;
499  reg |= mask_or;
500  io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
501  if (final)
502  final(entry);
503 }
504 
505 static void io_apic_modify_irq(struct irq_cfg *cfg,
506  int mask_and, int mask_or,
507  void (*final)(struct irq_pin_list *entry))
508 {
509  struct irq_pin_list *entry;
510 
511  for_each_irq_pin(entry, cfg->irq_2_pin)
512  __io_apic_modify_irq(entry, mask_and, mask_or, final);
513 }
514 
515 static void io_apic_sync(struct irq_pin_list *entry)
516 {
517  /*
518  * Synchronize the IO-APIC and the CPU by doing
519  * a dummy read from the IO-APIC
520  */
521  struct io_apic __iomem *io_apic;
522 
523  io_apic = io_apic_base(entry->apic);
524  readl(&io_apic->data);
525 }
526 
527 static void mask_ioapic(struct irq_cfg *cfg)
528 {
529  unsigned long flags;
530 
531  raw_spin_lock_irqsave(&ioapic_lock, flags);
532  io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
533  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
534 }
535 
536 static void mask_ioapic_irq(struct irq_data *data)
537 {
538  mask_ioapic(data->chip_data);
539 }
540 
541 static void __unmask_ioapic(struct irq_cfg *cfg)
542 {
543  io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
544 }
545 
546 static void unmask_ioapic(struct irq_cfg *cfg)
547 {
548  unsigned long flags;
549 
550  raw_spin_lock_irqsave(&ioapic_lock, flags);
551  __unmask_ioapic(cfg);
552  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
553 }
554 
555 static void unmask_ioapic_irq(struct irq_data *data)
556 {
557  unmask_ioapic(data->chip_data);
558 }
559 
560 /*
561  * IO-APIC versions below 0x20 don't support EOI register.
562  * For the record, here is the information about various versions:
563  * 0Xh 82489DX
564  * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
565  * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
566  * 30h-FFh Reserved
567  *
568  * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
569  * version as 0x2. This is an error with documentation and these ICH chips
570  * use io-apic's of version 0x20.
571  *
572  * For IO-APIC's with EOI register, we use that to do an explicit EOI.
573  * Otherwise, we simulate the EOI message manually by changing the trigger
574  * mode to edge and then back to level, with RTE being masked during this.
575  */
576 static void __eoi_ioapic_pin(int apic, int pin, int vector, struct irq_cfg *cfg)
577 {
578  if (mpc_ioapic_ver(apic) >= 0x20) {
579  /*
580  * Intr-remapping uses pin number as the virtual vector
581  * in the RTE. Actual vector is programmed in
582  * intr-remapping table entry. Hence for the io-apic
583  * EOI we use the pin number.
584  */
585  if (cfg && irq_remapped(cfg))
586  io_apic_eoi(apic, pin);
587  else
588  io_apic_eoi(apic, vector);
589  } else {
590  struct IO_APIC_route_entry entry, entry1;
591 
592  entry = entry1 = __ioapic_read_entry(apic, pin);
593 
594  /*
595  * Mask the entry and change the trigger mode to edge.
596  */
597  entry1.mask = 1;
598  entry1.trigger = IOAPIC_EDGE;
599 
600  __ioapic_write_entry(apic, pin, entry1);
601 
602  /*
603  * Restore the previous level triggered entry.
604  */
605  __ioapic_write_entry(apic, pin, entry);
606  }
607 }
608 
609 static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
610 {
611  struct irq_pin_list *entry;
612  unsigned long flags;
613 
614  raw_spin_lock_irqsave(&ioapic_lock, flags);
615  for_each_irq_pin(entry, cfg->irq_2_pin)
616  __eoi_ioapic_pin(entry->apic, entry->pin, cfg->vector, cfg);
617  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
618 }
619 
620 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
621 {
622  struct IO_APIC_route_entry entry;
623 
624  /* Check delivery_mode to be sure we're not clearing an SMI pin */
625  entry = ioapic_read_entry(apic, pin);
626  if (entry.delivery_mode == dest_SMI)
627  return;
628 
629  /*
630  * Make sure the entry is masked and re-read the contents to check
631  * if it is a level triggered pin and if the remote-IRR is set.
632  */
633  if (!entry.mask) {
634  entry.mask = 1;
635  ioapic_write_entry(apic, pin, entry);
636  entry = ioapic_read_entry(apic, pin);
637  }
638 
639  if (entry.irr) {
640  unsigned long flags;
641 
642  /*
643  * Make sure the trigger mode is set to level. Explicit EOI
644  * doesn't clear the remote-IRR if the trigger mode is not
645  * set to level.
646  */
647  if (!entry.trigger) {
648  entry.trigger = IOAPIC_LEVEL;
649  ioapic_write_entry(apic, pin, entry);
650  }
651 
652  raw_spin_lock_irqsave(&ioapic_lock, flags);
653  __eoi_ioapic_pin(apic, pin, entry.vector, NULL);
654  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
655  }
656 
657  /*
658  * Clear the rest of the bits in the IO-APIC RTE except for the mask
659  * bit.
660  */
661  ioapic_mask_entry(apic, pin);
662  entry = ioapic_read_entry(apic, pin);
663  if (entry.irr)
664  pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
665  mpc_ioapic_id(apic), pin);
666 }
667 
668 static void clear_IO_APIC (void)
669 {
670  int apic, pin;
671 
672  for (apic = 0; apic < nr_ioapics; apic++)
673  for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
674  clear_IO_APIC_pin(apic, pin);
675 }
676 
677 #ifdef CONFIG_X86_32
678 /*
679  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
680  * specific CPU-side IRQs.
681  */
682 
683 #define MAX_PIRQS 8
684 static int pirq_entries[MAX_PIRQS] = {
685  [0 ... MAX_PIRQS - 1] = -1
686 };
687 
688 static int __init ioapic_pirq_setup(char *str)
689 {
690  int i, max;
691  int ints[MAX_PIRQS+1];
692 
693  get_options(str, ARRAY_SIZE(ints), ints);
694 
696  "PIRQ redirection, working around broken MP-BIOS.\n");
697  max = MAX_PIRQS;
698  if (ints[0] < MAX_PIRQS)
699  max = ints[0];
700 
701  for (i = 0; i < max; i++) {
703  "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
704  /*
705  * PIRQs are mapped upside down, usually.
706  */
707  pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
708  }
709  return 1;
710 }
711 
712 __setup("pirq=", ioapic_pirq_setup);
713 #endif /* CONFIG_X86_32 */
714 
715 /*
716  * Saves all the IO-APIC RTE's
717  */
719 {
720  int apic, pin;
721  int err = 0;
722 
723  for (apic = 0; apic < nr_ioapics; apic++) {
724  if (!ioapics[apic].saved_registers) {
725  err = -ENOMEM;
726  continue;
727  }
728 
729  for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
730  ioapics[apic].saved_registers[pin] =
731  ioapic_read_entry(apic, pin);
732  }
733 
734  return err;
735 }
736 
737 /*
738  * Mask all IO APIC entries.
739  */
741 {
742  int apic, pin;
743 
744  for (apic = 0; apic < nr_ioapics; apic++) {
745  if (!ioapics[apic].saved_registers)
746  continue;
747 
748  for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
749  struct IO_APIC_route_entry entry;
750 
751  entry = ioapics[apic].saved_registers[pin];
752  if (!entry.mask) {
753  entry.mask = 1;
754  ioapic_write_entry(apic, pin, entry);
755  }
756  }
757  }
758 }
759 
760 /*
761  * Restore IO APIC entries which was saved in the ioapic structure.
762  */
764 {
765  int apic, pin;
766 
767  for (apic = 0; apic < nr_ioapics; apic++) {
768  if (!ioapics[apic].saved_registers)
769  continue;
770 
771  for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
772  ioapic_write_entry(apic, pin,
773  ioapics[apic].saved_registers[pin]);
774  }
775  return 0;
776 }
777 
778 /*
779  * Find the IRQ entry number of a certain pin.
780  */
781 static int find_irq_entry(int ioapic_idx, int pin, int type)
782 {
783  int i;
784 
785  for (i = 0; i < mp_irq_entries; i++)
786  if (mp_irqs[i].irqtype == type &&
787  (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
788  mp_irqs[i].dstapic == MP_APIC_ALL) &&
789  mp_irqs[i].dstirq == pin)
790  return i;
791 
792  return -1;
793 }
794 
795 /*
796  * Find the pin to which IRQ[irq] (ISA) is connected
797  */
798 static int __init find_isa_irq_pin(int irq, int type)
799 {
800  int i;
801 
802  for (i = 0; i < mp_irq_entries; i++) {
803  int lbus = mp_irqs[i].srcbus;
804 
805  if (test_bit(lbus, mp_bus_not_pci) &&
806  (mp_irqs[i].irqtype == type) &&
807  (mp_irqs[i].srcbusirq == irq))
808 
809  return mp_irqs[i].dstirq;
810  }
811  return -1;
812 }
813 
814 static int __init find_isa_irq_apic(int irq, int type)
815 {
816  int i;
817 
818  for (i = 0; i < mp_irq_entries; i++) {
819  int lbus = mp_irqs[i].srcbus;
820 
821  if (test_bit(lbus, mp_bus_not_pci) &&
822  (mp_irqs[i].irqtype == type) &&
823  (mp_irqs[i].srcbusirq == irq))
824  break;
825  }
826 
827  if (i < mp_irq_entries) {
828  int ioapic_idx;
829 
830  for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
831  if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
832  return ioapic_idx;
833  }
834 
835  return -1;
836 }
837 
838 #ifdef CONFIG_EISA
839 /*
840  * EISA Edge/Level control register, ELCR
841  */
842 static int EISA_ELCR(unsigned int irq)
843 {
844  if (irq < legacy_pic->nr_legacy_irqs) {
845  unsigned int port = 0x4d0 + (irq >> 3);
846  return (inb(port) >> (irq & 7)) & 1;
847  }
849  "Broken MPtable reports ISA irq %d\n", irq);
850  return 0;
851 }
852 
853 #endif
854 
855 /* ISA interrupts are always polarity zero edge triggered,
856  * when listed as conforming in the MP table. */
857 
858 #define default_ISA_trigger(idx) (0)
859 #define default_ISA_polarity(idx) (0)
860 
861 /* EISA interrupts are always polarity zero and can be edge or level
862  * trigger depending on the ELCR value. If an interrupt is listed as
863  * EISA conforming in the MP table, that means its trigger type must
864  * be read in from the ELCR */
865 
866 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
867 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
868 
869 /* PCI interrupts are always polarity one level triggered,
870  * when listed as conforming in the MP table. */
871 
872 #define default_PCI_trigger(idx) (1)
873 #define default_PCI_polarity(idx) (1)
874 
875 static int irq_polarity(int idx)
876 {
877  int bus = mp_irqs[idx].srcbus;
878  int polarity;
879 
880  /*
881  * Determine IRQ line polarity (high active or low active):
882  */
883  switch (mp_irqs[idx].irqflag & 3)
884  {
885  case 0: /* conforms, ie. bus-type dependent polarity */
886  if (test_bit(bus, mp_bus_not_pci))
887  polarity = default_ISA_polarity(idx);
888  else
889  polarity = default_PCI_polarity(idx);
890  break;
891  case 1: /* high active */
892  {
893  polarity = 0;
894  break;
895  }
896  case 2: /* reserved */
897  {
898  pr_warn("broken BIOS!!\n");
899  polarity = 1;
900  break;
901  }
902  case 3: /* low active */
903  {
904  polarity = 1;
905  break;
906  }
907  default: /* invalid */
908  {
909  pr_warn("broken BIOS!!\n");
910  polarity = 1;
911  break;
912  }
913  }
914  return polarity;
915 }
916 
917 static int irq_trigger(int idx)
918 {
919  int bus = mp_irqs[idx].srcbus;
920  int trigger;
921 
922  /*
923  * Determine IRQ trigger mode (edge or level sensitive):
924  */
925  switch ((mp_irqs[idx].irqflag>>2) & 3)
926  {
927  case 0: /* conforms, ie. bus-type dependent */
928  if (test_bit(bus, mp_bus_not_pci))
929  trigger = default_ISA_trigger(idx);
930  else
931  trigger = default_PCI_trigger(idx);
932 #ifdef CONFIG_EISA
933  switch (mp_bus_id_to_type[bus]) {
934  case MP_BUS_ISA: /* ISA pin */
935  {
936  /* set before the switch */
937  break;
938  }
939  case MP_BUS_EISA: /* EISA pin */
940  {
941  trigger = default_EISA_trigger(idx);
942  break;
943  }
944  case MP_BUS_PCI: /* PCI pin */
945  {
946  /* set before the switch */
947  break;
948  }
949  default:
950  {
951  pr_warn("broken BIOS!!\n");
952  trigger = 1;
953  break;
954  }
955  }
956 #endif
957  break;
958  case 1: /* edge */
959  {
960  trigger = 0;
961  break;
962  }
963  case 2: /* reserved */
964  {
965  pr_warn("broken BIOS!!\n");
966  trigger = 1;
967  break;
968  }
969  case 3: /* level */
970  {
971  trigger = 1;
972  break;
973  }
974  default: /* invalid */
975  {
976  pr_warn("broken BIOS!!\n");
977  trigger = 0;
978  break;
979  }
980  }
981  return trigger;
982 }
983 
984 static int pin_2_irq(int idx, int apic, int pin)
985 {
986  int irq;
987  int bus = mp_irqs[idx].srcbus;
988  struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic);
989 
990  /*
991  * Debugging check, we are in big trouble if this message pops up!
992  */
993  if (mp_irqs[idx].dstirq != pin)
994  pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
995 
996  if (test_bit(bus, mp_bus_not_pci)) {
997  irq = mp_irqs[idx].srcbusirq;
998  } else {
999  u32 gsi = gsi_cfg->gsi_base + pin;
1000 
1001  if (gsi >= NR_IRQS_LEGACY)
1002  irq = gsi;
1003  else
1004  irq = gsi_top + gsi;
1005  }
1006 
1007 #ifdef CONFIG_X86_32
1008  /*
1009  * PCI IRQ command line redirection. Yes, limits are hardcoded.
1010  */
1011  if ((pin >= 16) && (pin <= 23)) {
1012  if (pirq_entries[pin-16] != -1) {
1013  if (!pirq_entries[pin-16]) {
1015  "disabling PIRQ%d\n", pin-16);
1016  } else {
1017  irq = pirq_entries[pin-16];
1019  "using PIRQ%d -> IRQ %d\n",
1020  pin-16, irq);
1021  }
1022  }
1023  }
1024 #endif
1025 
1026  return irq;
1027 }
1028 
1029 /*
1030  * Find a specific PCI IRQ entry.
1031  * Not an __init, possibly needed by modules
1032  */
1033 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1034  struct io_apic_irq_attr *irq_attr)
1035 {
1036  int ioapic_idx, i, best_guess = -1;
1037 
1039  "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1040  bus, slot, pin);
1041  if (test_bit(bus, mp_bus_not_pci)) {
1043  "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1044  return -1;
1045  }
1046  for (i = 0; i < mp_irq_entries; i++) {
1047  int lbus = mp_irqs[i].srcbus;
1048 
1049  for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1050  if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1051  mp_irqs[i].dstapic == MP_APIC_ALL)
1052  break;
1053 
1054  if (!test_bit(lbus, mp_bus_not_pci) &&
1055  !mp_irqs[i].irqtype &&
1056  (bus == lbus) &&
1057  (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1058  int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq);
1059 
1060  if (!(ioapic_idx || IO_APIC_IRQ(irq)))
1061  continue;
1062 
1063  if (pin == (mp_irqs[i].srcbusirq & 3)) {
1064  set_io_apic_irq_attr(irq_attr, ioapic_idx,
1065  mp_irqs[i].dstirq,
1066  irq_trigger(i),
1067  irq_polarity(i));
1068  return irq;
1069  }
1070  /*
1071  * Use the first all-but-pin matching entry as a
1072  * best-guess fuzzy result for broken mptables.
1073  */
1074  if (best_guess < 0) {
1075  set_io_apic_irq_attr(irq_attr, ioapic_idx,
1076  mp_irqs[i].dstirq,
1077  irq_trigger(i),
1078  irq_polarity(i));
1079  best_guess = irq;
1080  }
1081  }
1082  }
1083  return best_guess;
1084 }
1086 
1088 {
1089  /* Used to the online set of cpus does not change
1090  * during assign_irq_vector.
1091  */
1093 }
1094 
1096 {
1098 }
1099 
1100 static int
1101 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1102 {
1103  /*
1104  * NOTE! The local APIC isn't very good at handling
1105  * multiple interrupts at the same interrupt level.
1106  * As the interrupt level is determined by taking the
1107  * vector number and shifting that right by 4, we
1108  * want to spread these out a bit so that they don't
1109  * all fall in the same interrupt level.
1110  *
1111  * Also, we've got to be careful not to trash gate
1112  * 0x80, because int 0x80 is hm, kind of importantish. ;)
1113  */
1114  static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1115  static int current_offset = VECTOR_OFFSET_START % 16;
1116  int cpu, err;
1117  cpumask_var_t tmp_mask;
1118 
1119  if (cfg->move_in_progress)
1120  return -EBUSY;
1121 
1122  if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1123  return -ENOMEM;
1124 
1125  /* Only try and allocate irqs on cpus that are present */
1126  err = -ENOSPC;
1127  cpumask_clear(cfg->old_domain);
1128  cpu = cpumask_first_and(mask, cpu_online_mask);
1129  while (cpu < nr_cpu_ids) {
1130  int new_cpu, vector, offset;
1131 
1132  apic->vector_allocation_domain(cpu, tmp_mask, mask);
1133 
1134  if (cpumask_subset(tmp_mask, cfg->domain)) {
1135  err = 0;
1136  if (cpumask_equal(tmp_mask, cfg->domain))
1137  break;
1138  /*
1139  * New cpumask using the vector is a proper subset of
1140  * the current in use mask. So cleanup the vector
1141  * allocation for the members that are not used anymore.
1142  */
1143  cpumask_andnot(cfg->old_domain, cfg->domain, tmp_mask);
1144  cfg->move_in_progress = 1;
1145  cpumask_and(cfg->domain, cfg->domain, tmp_mask);
1146  break;
1147  }
1148 
1149  vector = current_vector;
1150  offset = current_offset;
1151 next:
1152  vector += 16;
1153  if (vector >= first_system_vector) {
1154  offset = (offset + 1) % 16;
1155  vector = FIRST_EXTERNAL_VECTOR + offset;
1156  }
1157 
1158  if (unlikely(current_vector == vector)) {
1159  cpumask_or(cfg->old_domain, cfg->old_domain, tmp_mask);
1160  cpumask_andnot(tmp_mask, mask, cfg->old_domain);
1161  cpu = cpumask_first_and(tmp_mask, cpu_online_mask);
1162  continue;
1163  }
1164 
1165  if (test_bit(vector, used_vectors))
1166  goto next;
1167 
1168  for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1169  if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1170  goto next;
1171  /* Found one! */
1172  current_vector = vector;
1173  current_offset = offset;
1174  if (cfg->vector) {
1175  cfg->move_in_progress = 1;
1176  cpumask_copy(cfg->old_domain, cfg->domain);
1177  }
1178  for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1179  per_cpu(vector_irq, new_cpu)[vector] = irq;
1180  cfg->vector = vector;
1181  cpumask_copy(cfg->domain, tmp_mask);
1182  err = 0;
1183  break;
1184  }
1185  free_cpumask_var(tmp_mask);
1186  return err;
1187 }
1188 
1190 {
1191  int err;
1192  unsigned long flags;
1193 
1195  err = __assign_irq_vector(irq, cfg, mask);
1197  return err;
1198 }
1199 
1200 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1201 {
1202  int cpu, vector;
1203 
1204  BUG_ON(!cfg->vector);
1205 
1206  vector = cfg->vector;
1207  for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1208  per_cpu(vector_irq, cpu)[vector] = -1;
1209 
1210  cfg->vector = 0;
1211  cpumask_clear(cfg->domain);
1212 
1213  if (likely(!cfg->move_in_progress))
1214  return;
1215  for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1216  for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1217  vector++) {
1218  if (per_cpu(vector_irq, cpu)[vector] != irq)
1219  continue;
1220  per_cpu(vector_irq, cpu)[vector] = -1;
1221  break;
1222  }
1223  }
1224  cfg->move_in_progress = 0;
1225 }
1226 
1227 void __setup_vector_irq(int cpu)
1228 {
1229  /* Initialize vector_irq on a new cpu */
1230  int irq, vector;
1231  struct irq_cfg *cfg;
1232 
1233  /*
1234  * vector_lock will make sure that we don't run into irq vector
1235  * assignments that might be happening on another cpu in parallel,
1236  * while we setup our initial vector to irq mappings.
1237  */
1239  /* Mark the inuse vectors */
1240  for_each_active_irq(irq) {
1241  cfg = irq_get_chip_data(irq);
1242  if (!cfg)
1243  continue;
1244  /*
1245  * If it is a legacy IRQ handled by the legacy PIC, this cpu
1246  * will be part of the irq_cfg's domain.
1247  */
1248  if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1249  cpumask_set_cpu(cpu, cfg->domain);
1250 
1251  if (!cpumask_test_cpu(cpu, cfg->domain))
1252  continue;
1253  vector = cfg->vector;
1254  per_cpu(vector_irq, cpu)[vector] = irq;
1255  }
1256  /* Mark the free vectors */
1257  for (vector = 0; vector < NR_VECTORS; ++vector) {
1258  irq = per_cpu(vector_irq, cpu)[vector];
1259  if (irq < 0)
1260  continue;
1261 
1262  cfg = irq_cfg(irq);
1263  if (!cpumask_test_cpu(cpu, cfg->domain))
1264  per_cpu(vector_irq, cpu)[vector] = -1;
1265  }
1267 }
1268 
1269 static struct irq_chip ioapic_chip;
1270 
1271 #ifdef CONFIG_X86_32
1272 static inline int IO_APIC_irq_trigger(int irq)
1273 {
1274  int apic, idx, pin;
1275 
1276  for (apic = 0; apic < nr_ioapics; apic++) {
1277  for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1278  idx = find_irq_entry(apic, pin, mp_INT);
1279  if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1280  return irq_trigger(idx);
1281  }
1282  }
1283  /*
1284  * nonexistent IRQs are edge default
1285  */
1286  return 0;
1287 }
1288 #else
1289 static inline int IO_APIC_irq_trigger(int irq)
1290 {
1291  return 1;
1292 }
1293 #endif
1294 
1295 static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1296  unsigned long trigger)
1297 {
1298  struct irq_chip *chip = &ioapic_chip;
1299  irq_flow_handler_t hdl;
1300  bool fasteoi;
1301 
1302  if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1303  trigger == IOAPIC_LEVEL) {
1304  irq_set_status_flags(irq, IRQ_LEVEL);
1305  fasteoi = true;
1306  } else {
1307  irq_clear_status_flags(irq, IRQ_LEVEL);
1308  fasteoi = false;
1309  }
1310 
1311  if (irq_remapped(cfg)) {
1312  irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1313  irq_remap_modify_chip_defaults(chip);
1314  fasteoi = trigger != 0;
1315  }
1316 
1317  hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1318  irq_set_chip_and_handler_name(irq, chip, hdl,
1319  fasteoi ? "fasteoi" : "edge");
1320 }
1321 
1322 static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
1323  unsigned int destination, int vector,
1324  struct io_apic_irq_attr *attr)
1325 {
1327  return setup_ioapic_remapped_entry(irq, entry, destination,
1328  vector, attr);
1329 
1330  memset(entry, 0, sizeof(*entry));
1331 
1332  entry->delivery_mode = apic->irq_delivery_mode;
1333  entry->dest_mode = apic->irq_dest_mode;
1334  entry->dest = destination;
1335  entry->vector = vector;
1336  entry->mask = 0; /* enable IRQ */
1337  entry->trigger = attr->trigger;
1338  entry->polarity = attr->polarity;
1339 
1340  /*
1341  * Mask level triggered irqs.
1342  * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1343  */
1344  if (attr->trigger)
1345  entry->mask = 1;
1346 
1347  return 0;
1348 }
1349 
1350 static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
1351  struct io_apic_irq_attr *attr)
1352 {
1353  struct IO_APIC_route_entry entry;
1354  unsigned int dest;
1355 
1356  if (!IO_APIC_IRQ(irq))
1357  return;
1358 
1359  /*
1360  * For legacy irqs, cfg->domain starts with cpu 0. Now that IO-APIC
1361  * can handle this irq and the apic driver is finialized at this point,
1362  * update the cfg->domain.
1363  */
1364  if (irq < legacy_pic->nr_legacy_irqs &&
1365  cpumask_equal(cfg->domain, cpumask_of(0)))
1366  apic->vector_allocation_domain(0, cfg->domain,
1367  apic->target_cpus());
1368 
1369  if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1370  return;
1371 
1372  if (apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus(),
1373  &dest)) {
1374  pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n",
1375  mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1376  __clear_irq_vector(irq, cfg);
1377 
1378  return;
1379  }
1380 
1382  "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1383  "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1384  attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
1385  cfg->vector, irq, attr->trigger, attr->polarity, dest);
1386 
1387  if (setup_ioapic_entry(irq, &entry, dest, cfg->vector, attr)) {
1388  pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1389  mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1390  __clear_irq_vector(irq, cfg);
1391 
1392  return;
1393  }
1394 
1395  ioapic_register_intr(irq, cfg, attr->trigger);
1396  if (irq < legacy_pic->nr_legacy_irqs)
1397  legacy_pic->mask(irq);
1398 
1399  ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
1400 }
1401 
1402 static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin)
1403 {
1404  if (idx != -1)
1405  return false;
1406 
1407  apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1408  mpc_ioapic_id(ioapic_idx), pin);
1409  return true;
1410 }
1411 
1412 static void __init __io_apic_setup_irqs(unsigned int ioapic_idx)
1413 {
1414  int idx, node = cpu_to_node(0);
1415  struct io_apic_irq_attr attr;
1416  unsigned int pin, irq;
1417 
1418  for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) {
1419  idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1420  if (io_apic_pin_not_connected(idx, ioapic_idx, pin))
1421  continue;
1422 
1423  irq = pin_2_irq(idx, ioapic_idx, pin);
1424 
1425  if ((ioapic_idx > 0) && (irq > 16))
1426  continue;
1427 
1428  /*
1429  * Skip the timer IRQ if there's a quirk handler
1430  * installed and if it returns 1:
1431  */
1432  if (apic->multi_timer_check &&
1433  apic->multi_timer_check(ioapic_idx, irq))
1434  continue;
1435 
1436  set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1437  irq_polarity(idx));
1438 
1439  io_apic_setup_irq_pin(irq, node, &attr);
1440  }
1441 }
1442 
1443 static void __init setup_IO_APIC_irqs(void)
1444 {
1445  unsigned int ioapic_idx;
1446 
1447  apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1448 
1449  for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1450  __io_apic_setup_irqs(ioapic_idx);
1451 }
1452 
1453 /*
1454  * for the gsit that is not in first ioapic
1455  * but could not use acpi_register_gsi()
1456  * like some special sci in IBM x3330
1457  */
1459 {
1460  int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0);
1461  struct io_apic_irq_attr attr;
1462 
1463  /*
1464  * Convert 'gsi' to 'ioapic.pin'.
1465  */
1466  ioapic_idx = mp_find_ioapic(gsi);
1467  if (ioapic_idx < 0)
1468  return;
1469 
1470  pin = mp_find_ioapic_pin(ioapic_idx, gsi);
1471  idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1472  if (idx == -1)
1473  return;
1474 
1475  irq = pin_2_irq(idx, ioapic_idx, pin);
1476 
1477  /* Only handle the non legacy irqs on secondary ioapics */
1478  if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY)
1479  return;
1480 
1481  set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1482  irq_polarity(idx));
1483 
1484  io_apic_setup_irq_pin_once(irq, node, &attr);
1485 }
1486 
1487 /*
1488  * Set up the timer pin, possibly with the 8259A-master behind.
1489  */
1490 static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
1491  unsigned int pin, int vector)
1492 {
1493  struct IO_APIC_route_entry entry;
1494  unsigned int dest;
1495 
1497  return;
1498 
1499  memset(&entry, 0, sizeof(entry));
1500 
1501  /*
1502  * We use logical delivery to get the timer IRQ
1503  * to the first CPU.
1504  */
1505  if (unlikely(apic->cpu_mask_to_apicid_and(apic->target_cpus(),
1506  apic->target_cpus(), &dest)))
1507  dest = BAD_APICID;
1508 
1509  entry.dest_mode = apic->irq_dest_mode;
1510  entry.mask = 0; /* don't mask IRQ for edge */
1511  entry.dest = dest;
1512  entry.delivery_mode = apic->irq_delivery_mode;
1513  entry.polarity = 0;
1514  entry.trigger = 0;
1515  entry.vector = vector;
1516 
1517  /*
1518  * The timer IRQ doesn't have to know that behind the
1519  * scene we may have a 8259A-master in AEOI mode ...
1520  */
1522  "edge");
1523 
1524  /*
1525  * Add it to the IO-APIC irq-routing table:
1526  */
1527  ioapic_write_entry(ioapic_idx, pin, entry);
1528 }
1529 
1530 __apicdebuginit(void) print_IO_APIC(int ioapic_idx)
1531 {
1532  int i;
1533  union IO_APIC_reg_00 reg_00;
1534  union IO_APIC_reg_01 reg_01;
1535  union IO_APIC_reg_02 reg_02;
1536  union IO_APIC_reg_03 reg_03;
1537  unsigned long flags;
1538 
1539  raw_spin_lock_irqsave(&ioapic_lock, flags);
1540  reg_00.raw = io_apic_read(ioapic_idx, 0);
1541  reg_01.raw = io_apic_read(ioapic_idx, 1);
1542  if (reg_01.bits.version >= 0x10)
1543  reg_02.raw = io_apic_read(ioapic_idx, 2);
1544  if (reg_01.bits.version >= 0x20)
1545  reg_03.raw = io_apic_read(ioapic_idx, 3);
1546  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1547 
1548  printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1549  printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1550  printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1551  printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1552  printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1553 
1554  printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1555  printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1556  reg_01.bits.entries);
1557 
1558  printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1559  printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1560  reg_01.bits.version);
1561 
1562  /*
1563  * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1564  * but the value of reg_02 is read as the previous read register
1565  * value, so ignore it if reg_02 == reg_01.
1566  */
1567  if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1568  printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1569  printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1570  }
1571 
1572  /*
1573  * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1574  * or reg_03, but the value of reg_0[23] is read as the previous read
1575  * register value, so ignore it if reg_03 == reg_0[12].
1576  */
1577  if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1578  reg_03.raw != reg_01.raw) {
1579  printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1580  printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1581  }
1582 
1583  printk(KERN_DEBUG ".... IRQ redirection table:\n");
1584 
1585  if (irq_remapping_enabled) {
1586  printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR"
1587  " Pol Stat Indx2 Zero Vect:\n");
1588  } else {
1589  printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1590  " Stat Dmod Deli Vect:\n");
1591  }
1592 
1593  for (i = 0; i <= reg_01.bits.entries; i++) {
1594  if (irq_remapping_enabled) {
1595  struct IO_APIC_route_entry entry;
1596  struct IR_IO_APIC_route_entry *ir_entry;
1597 
1598  entry = ioapic_read_entry(ioapic_idx, i);
1599  ir_entry = (struct IR_IO_APIC_route_entry *) &entry;
1600  printk(KERN_DEBUG " %02x %04X ",
1601  i,
1602  ir_entry->index
1603  );
1604  pr_cont("%1d %1d %1d %1d %1d "
1605  "%1d %1d %X %02X\n",
1606  ir_entry->format,
1607  ir_entry->mask,
1608  ir_entry->trigger,
1609  ir_entry->irr,
1610  ir_entry->polarity,
1611  ir_entry->delivery_status,
1612  ir_entry->index2,
1613  ir_entry->zero,
1614  ir_entry->vector
1615  );
1616  } else {
1617  struct IO_APIC_route_entry entry;
1618 
1619  entry = ioapic_read_entry(ioapic_idx, i);
1620  printk(KERN_DEBUG " %02x %02X ",
1621  i,
1622  entry.dest
1623  );
1624  pr_cont("%1d %1d %1d %1d %1d "
1625  "%1d %1d %02X\n",
1626  entry.mask,
1627  entry.trigger,
1628  entry.irr,
1629  entry.polarity,
1630  entry.delivery_status,
1631  entry.dest_mode,
1632  entry.delivery_mode,
1633  entry.vector
1634  );
1635  }
1636  }
1637 }
1638 
1639 __apicdebuginit(void) print_IO_APICs(void)
1640 {
1641  int ioapic_idx;
1642  struct irq_cfg *cfg;
1643  unsigned int irq;
1644  struct irq_chip *chip;
1645 
1646  printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1647  for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1648  printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1649  mpc_ioapic_id(ioapic_idx),
1650  ioapics[ioapic_idx].nr_registers);
1651 
1652  /*
1653  * We are a bit conservative about what we expect. We have to
1654  * know about every hardware change ASAP.
1655  */
1656  printk(KERN_INFO "testing the IO APIC.......................\n");
1657 
1658  for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1659  print_IO_APIC(ioapic_idx);
1660 
1661  printk(KERN_DEBUG "IRQ to pin mappings:\n");
1662  for_each_active_irq(irq) {
1663  struct irq_pin_list *entry;
1664 
1665  chip = irq_get_chip(irq);
1666  if (chip != &ioapic_chip)
1667  continue;
1668 
1669  cfg = irq_get_chip_data(irq);
1670  if (!cfg)
1671  continue;
1672  entry = cfg->irq_2_pin;
1673  if (!entry)
1674  continue;
1675  printk(KERN_DEBUG "IRQ%d ", irq);
1676  for_each_irq_pin(entry, cfg->irq_2_pin)
1677  pr_cont("-> %d:%d", entry->apic, entry->pin);
1678  pr_cont("\n");
1679  }
1680 
1681  printk(KERN_INFO ".................................... done.\n");
1682 }
1683 
1684 __apicdebuginit(void) print_APIC_field(int base)
1685 {
1686  int i;
1687 
1688  printk(KERN_DEBUG);
1689 
1690  for (i = 0; i < 8; i++)
1691  pr_cont("%08x", apic_read(base + i*0x10));
1692 
1693  pr_cont("\n");
1694 }
1695 
1696 __apicdebuginit(void) print_local_APIC(void *dummy)
1697 {
1698  unsigned int i, v, ver, maxlvt;
1699  u64 icr;
1700 
1701  printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1703  v = apic_read(APIC_ID);
1704  printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1705  v = apic_read(APIC_LVR);
1706  printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1707  ver = GET_APIC_VERSION(v);
1708  maxlvt = lapic_get_maxlvt();
1709 
1710  v = apic_read(APIC_TASKPRI);
1711  printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1712 
1713  if (APIC_INTEGRATED(ver)) { /* !82489DX */
1714  if (!APIC_XAPIC(ver)) {
1715  v = apic_read(APIC_ARBPRI);
1716  printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1717  v & APIC_ARBPRI_MASK);
1718  }
1719  v = apic_read(APIC_PROCPRI);
1720  printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1721  }
1722 
1723  /*
1724  * Remote read supported only in the 82489DX and local APIC for
1725  * Pentium processors.
1726  */
1727  if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1728  v = apic_read(APIC_RRR);
1729  printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1730  }
1731 
1732  v = apic_read(APIC_LDR);
1733  printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1734  if (!x2apic_enabled()) {
1735  v = apic_read(APIC_DFR);
1736  printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1737  }
1738  v = apic_read(APIC_SPIV);
1739  printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1740 
1741  printk(KERN_DEBUG "... APIC ISR field:\n");
1742  print_APIC_field(APIC_ISR);
1743  printk(KERN_DEBUG "... APIC TMR field:\n");
1744  print_APIC_field(APIC_TMR);
1745  printk(KERN_DEBUG "... APIC IRR field:\n");
1746  print_APIC_field(APIC_IRR);
1747 
1748  if (APIC_INTEGRATED(ver)) { /* !82489DX */
1749  if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1750  apic_write(APIC_ESR, 0);
1751 
1752  v = apic_read(APIC_ESR);
1753  printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1754  }
1755 
1756  icr = apic_icr_read();
1757  printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1758  printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1759 
1760  v = apic_read(APIC_LVTT);
1761  printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1762 
1763  if (maxlvt > 3) { /* PC is LVT#4. */
1764  v = apic_read(APIC_LVTPC);
1765  printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1766  }
1767  v = apic_read(APIC_LVT0);
1768  printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1769  v = apic_read(APIC_LVT1);
1770  printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1771 
1772  if (maxlvt > 2) { /* ERR is LVT#3. */
1773  v = apic_read(APIC_LVTERR);
1774  printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1775  }
1776 
1777  v = apic_read(APIC_TMICT);
1778  printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1779  v = apic_read(APIC_TMCCT);
1780  printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1781  v = apic_read(APIC_TDCR);
1782  printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1783 
1784  if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1785  v = apic_read(APIC_EFEAT);
1786  maxlvt = (v >> 16) & 0xff;
1787  printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1788  v = apic_read(APIC_ECTRL);
1789  printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1790  for (i = 0; i < maxlvt; i++) {
1791  v = apic_read(APIC_EILVTn(i));
1792  printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1793  }
1794  }
1795  pr_cont("\n");
1796 }
1797 
1798 __apicdebuginit(void) print_local_APICs(int maxcpu)
1799 {
1800  int cpu;
1801 
1802  if (!maxcpu)
1803  return;
1804 
1805  preempt_disable();
1806  for_each_online_cpu(cpu) {
1807  if (cpu >= maxcpu)
1808  break;
1809  smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1810  }
1811  preempt_enable();
1812 }
1813 
1814 __apicdebuginit(void) print_PIC(void)
1815 {
1816  unsigned int v;
1817  unsigned long flags;
1818 
1819  if (!legacy_pic->nr_legacy_irqs)
1820  return;
1821 
1822  printk(KERN_DEBUG "\nprinting PIC contents\n");
1823 
1824  raw_spin_lock_irqsave(&i8259A_lock, flags);
1825 
1826  v = inb(0xa1) << 8 | inb(0x21);
1827  printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1828 
1829  v = inb(0xa0) << 8 | inb(0x20);
1830  printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1831 
1832  outb(0x0b,0xa0);
1833  outb(0x0b,0x20);
1834  v = inb(0xa0) << 8 | inb(0x20);
1835  outb(0x0a,0xa0);
1836  outb(0x0a,0x20);
1837 
1838  raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1839 
1840  printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1841 
1842  v = inb(0x4d1) << 8 | inb(0x4d0);
1843  printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1844 }
1845 
1846 static int __initdata show_lapic = 1;
1847 static __init int setup_show_lapic(char *arg)
1848 {
1849  int num = -1;
1850 
1851  if (strcmp(arg, "all") == 0) {
1852  show_lapic = CONFIG_NR_CPUS;
1853  } else {
1854  get_option(&arg, &num);
1855  if (num >= 0)
1856  show_lapic = num;
1857  }
1858 
1859  return 1;
1860 }
1861 __setup("show_lapic=", setup_show_lapic);
1862 
1863 __apicdebuginit(int) print_ICs(void)
1864 {
1865  if (apic_verbosity == APIC_QUIET)
1866  return 0;
1867 
1868  print_PIC();
1869 
1870  /* don't print out if apic is not there */
1871  if (!cpu_has_apic && !apic_from_smp_config())
1872  return 0;
1873 
1874  print_local_APICs(show_lapic);
1875  print_IO_APICs();
1876 
1877  return 0;
1878 }
1879 
1880 late_initcall(print_ICs);
1881 
1882 
1883 /* Where if anywhere is the i8259 connect in external int mode */
1884 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1885 
1887 {
1888  int i8259_apic, i8259_pin;
1889  int apic;
1890 
1891  if (!legacy_pic->nr_legacy_irqs)
1892  return;
1893 
1894  for(apic = 0; apic < nr_ioapics; apic++) {
1895  int pin;
1896  /* See if any of the pins is in ExtINT mode */
1897  for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1898  struct IO_APIC_route_entry entry;
1899  entry = ioapic_read_entry(apic, pin);
1900 
1901  /* If the interrupt line is enabled and in ExtInt mode
1902  * I have found the pin where the i8259 is connected.
1903  */
1904  if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1905  ioapic_i8259.apic = apic;
1906  ioapic_i8259.pin = pin;
1907  goto found_i8259;
1908  }
1909  }
1910  }
1911  found_i8259:
1912  /* Look to see what if the MP table has reported the ExtINT */
1913  /* If we could not find the appropriate pin by looking at the ioapic
1914  * the i8259 probably is not connected the ioapic but give the
1915  * mptable a chance anyway.
1916  */
1917  i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1918  i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1919  /* Trust the MP table if nothing is setup in the hardware */
1920  if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1921  printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1922  ioapic_i8259.pin = i8259_pin;
1923  ioapic_i8259.apic = i8259_apic;
1924  }
1925  /* Complain if the MP table and the hardware disagree */
1926  if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1927  (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1928  {
1929  printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1930  }
1931 
1932  /*
1933  * Do not trust the IO-APIC being empty at bootup
1934  */
1935  clear_IO_APIC();
1936 }
1937 
1938 /*
1939  * Not an __init, needed by the reboot code
1940  */
1942 {
1943  /*
1944  * Clear the IO-APIC before rebooting:
1945  */
1946  clear_IO_APIC();
1947 
1948  if (!legacy_pic->nr_legacy_irqs)
1949  return;
1950 
1951  /*
1952  * If the i8259 is routed through an IOAPIC
1953  * Put that IOAPIC in virtual wire mode
1954  * so legacy interrupts can be delivered.
1955  *
1956  * With interrupt-remapping, for now we will use virtual wire A mode,
1957  * as virtual wire B is little complex (need to configure both
1958  * IOAPIC RTE as well as interrupt-remapping table entry).
1959  * As this gets called during crash dump, keep this simple for now.
1960  */
1961  if (ioapic_i8259.pin != -1 && !irq_remapping_enabled) {
1962  struct IO_APIC_route_entry entry;
1963 
1964  memset(&entry, 0, sizeof(entry));
1965  entry.mask = 0; /* Enabled */
1966  entry.trigger = 0; /* Edge */
1967  entry.irr = 0;
1968  entry.polarity = 0; /* High */
1969  entry.delivery_status = 0;
1970  entry.dest_mode = 0; /* Physical */
1971  entry.delivery_mode = dest_ExtINT; /* ExtInt */
1972  entry.vector = 0;
1973  entry.dest = read_apic_id();
1974 
1975  /*
1976  * Add it to the IO-APIC irq-routing table:
1977  */
1978  ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1979  }
1980 
1981  /*
1982  * Use virtual wire A mode when interrupt remapping is enabled.
1983  */
1984  if (cpu_has_apic || apic_from_smp_config())
1986  ioapic_i8259.pin != -1);
1987 }
1988 
1989 #ifdef CONFIG_X86_32
1990 /*
1991  * function to set the IO-APIC physical IDs based on the
1992  * values stored in the MPC table.
1993  *
1994  * by Matt Domsch <[email protected]> Tue Dec 21 12:25:05 CST 1999
1995  */
1996 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1997 {
1998  union IO_APIC_reg_00 reg_00;
1999  physid_mask_t phys_id_present_map;
2000  int ioapic_idx;
2001  int i;
2002  unsigned char old_id;
2003  unsigned long flags;
2004 
2005  /*
2006  * This is broken; anything with a real cpu count has to
2007  * circumvent this idiocy regardless.
2008  */
2009  apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2010 
2011  /*
2012  * Set the IOAPIC ID to the value stored in the MPC table.
2013  */
2014  for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
2015  /* Read the register 0 value */
2016  raw_spin_lock_irqsave(&ioapic_lock, flags);
2017  reg_00.raw = io_apic_read(ioapic_idx, 0);
2018  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2019 
2020  old_id = mpc_ioapic_id(ioapic_idx);
2021 
2022  if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
2023  printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2024  ioapic_idx, mpc_ioapic_id(ioapic_idx));
2025  printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2026  reg_00.bits.ID);
2027  ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
2028  }
2029 
2030  /*
2031  * Sanity check, is the ID really free? Every APIC in a
2032  * system must have a unique ID or we get lots of nice
2033  * 'stuck on smp_invalidate_needed IPI wait' messages.
2034  */
2035  if (apic->check_apicid_used(&phys_id_present_map,
2036  mpc_ioapic_id(ioapic_idx))) {
2037  printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2038  ioapic_idx, mpc_ioapic_id(ioapic_idx));
2039  for (i = 0; i < get_physical_broadcast(); i++)
2040  if (!physid_isset(i, phys_id_present_map))
2041  break;
2042  if (i >= get_physical_broadcast())
2043  panic("Max APIC ID exceeded!\n");
2044  printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2045  i);
2046  physid_set(i, phys_id_present_map);
2047  ioapics[ioapic_idx].mp_config.apicid = i;
2048  } else {
2050  apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
2051  &tmp);
2052  apic_printk(APIC_VERBOSE, "Setting %d in the "
2053  "phys_id_present_map\n",
2054  mpc_ioapic_id(ioapic_idx));
2055  physids_or(phys_id_present_map, phys_id_present_map, tmp);
2056  }
2057 
2058  /*
2059  * We need to adjust the IRQ routing table
2060  * if the ID changed.
2061  */
2062  if (old_id != mpc_ioapic_id(ioapic_idx))
2063  for (i = 0; i < mp_irq_entries; i++)
2064  if (mp_irqs[i].dstapic == old_id)
2065  mp_irqs[i].dstapic
2066  = mpc_ioapic_id(ioapic_idx);
2067 
2068  /*
2069  * Update the ID register according to the right value
2070  * from the MPC table if they are different.
2071  */
2072  if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
2073  continue;
2074 
2076  "...changing IO-APIC physical APIC ID to %d ...",
2077  mpc_ioapic_id(ioapic_idx));
2078 
2079  reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2080  raw_spin_lock_irqsave(&ioapic_lock, flags);
2081  io_apic_write(ioapic_idx, 0, reg_00.raw);
2082  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2083 
2084  /*
2085  * Sanity check
2086  */
2087  raw_spin_lock_irqsave(&ioapic_lock, flags);
2088  reg_00.raw = io_apic_read(ioapic_idx, 0);
2089  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2090  if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
2091  pr_cont("could not set ID!\n");
2092  else
2093  apic_printk(APIC_VERBOSE, " ok.\n");
2094  }
2095 }
2096 
2098 {
2099 
2100  if (acpi_ioapic)
2101  return;
2102  /*
2103  * Don't check I/O APIC IDs for xAPIC systems. They have
2104  * no meaning without the serial APIC bus.
2105  */
2106  if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2108  return;
2109  setup_ioapic_ids_from_mpc_nocheck();
2110 }
2111 #endif
2112 
2114 
2115 static int __init notimercheck(char *s)
2116 {
2117  no_timer_check = 1;
2118  return 1;
2119 }
2120 __setup("no_timer_check", notimercheck);
2121 
2122 /*
2123  * There is a nasty bug in some older SMP boards, their mptable lies
2124  * about the timer IRQ. We do the following to work around the situation:
2125  *
2126  * - timer IRQ defaults to IO-APIC IRQ
2127  * - if this function detects that timer IRQs are defunct, then we fall
2128  * back to ISA timer IRQs
2129  */
2130 static int __init timer_irq_works(void)
2131 {
2132  unsigned long t1 = jiffies;
2133  unsigned long flags;
2134 
2135  if (no_timer_check)
2136  return 1;
2137 
2138  local_save_flags(flags);
2139  local_irq_enable();
2140  /* Let ten ticks pass... */
2141  mdelay((10 * 1000) / HZ);
2142  local_irq_restore(flags);
2143 
2144  /*
2145  * Expect a few ticks at least, to be sure some possible
2146  * glue logic does not lock up after one or two first
2147  * ticks in a non-ExtINT mode. Also the local APIC
2148  * might have cached one ExtINT interrupt. Finally, at
2149  * least one tick may be lost due to delays.
2150  */
2151 
2152  /* jiffies wrap? */
2153  if (time_after(jiffies, t1 + 4))
2154  return 1;
2155  return 0;
2156 }
2157 
2158 /*
2159  * In the SMP+IOAPIC case it might happen that there are an unspecified
2160  * number of pending IRQ events unhandled. These cases are very rare,
2161  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2162  * better to do it this way as thus we do not have to be aware of
2163  * 'pending' interrupts in the IRQ path, except at this point.
2164  */
2165 /*
2166  * Edge triggered needs to resend any interrupt
2167  * that was delayed but this is now handled in the device
2168  * independent code.
2169  */
2170 
2171 /*
2172  * Starting up a edge-triggered IO-APIC interrupt is
2173  * nasty - we need to make sure that we get the edge.
2174  * If it is already asserted for some reason, we need
2175  * return 1 to indicate that is was pending.
2176  *
2177  * This is not complete - we should be able to fake
2178  * an edge even if it isn't on the 8259A...
2179  */
2180 
2181 static unsigned int startup_ioapic_irq(struct irq_data *data)
2182 {
2183  int was_pending = 0, irq = data->irq;
2184  unsigned long flags;
2185 
2186  raw_spin_lock_irqsave(&ioapic_lock, flags);
2187  if (irq < legacy_pic->nr_legacy_irqs) {
2188  legacy_pic->mask(irq);
2189  if (legacy_pic->irq_pending(irq))
2190  was_pending = 1;
2191  }
2192  __unmask_ioapic(data->chip_data);
2193  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2194 
2195  return was_pending;
2196 }
2197 
2198 static int ioapic_retrigger_irq(struct irq_data *data)
2199 {
2200  struct irq_cfg *cfg = data->chip_data;
2201  unsigned long flags;
2202 
2203  raw_spin_lock_irqsave(&vector_lock, flags);
2204  apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2205  raw_spin_unlock_irqrestore(&vector_lock, flags);
2206 
2207  return 1;
2208 }
2209 
2210 /*
2211  * Level and edge triggered IO-APIC interrupts need different handling,
2212  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2213  * handled with the level-triggered descriptor, but that one has slightly
2214  * more overhead. Level-triggered interrupts cannot be handled with the
2215  * edge-triggered handler, without risking IRQ storms and other ugly
2216  * races.
2217  */
2218 
2219 #ifdef CONFIG_SMP
2220 void send_cleanup_vector(struct irq_cfg *cfg)
2221 {
2222  cpumask_var_t cleanup_mask;
2223 
2224  if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2225  unsigned int i;
2226  for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2227  apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2228  } else {
2229  cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2230  apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2231  free_cpumask_var(cleanup_mask);
2232  }
2233  cfg->move_in_progress = 0;
2234 }
2235 
2236 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2237 {
2238  unsigned vector, me;
2239 
2240  ack_APIC_irq();
2241  irq_enter();
2242  exit_idle();
2243 
2244  me = smp_processor_id();
2245  for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2246  unsigned int irq;
2247  unsigned int irr;
2248  struct irq_desc *desc;
2249  struct irq_cfg *cfg;
2250  irq = __this_cpu_read(vector_irq[vector]);
2251 
2252  if (irq == -1)
2253  continue;
2254 
2255  desc = irq_to_desc(irq);
2256  if (!desc)
2257  continue;
2258 
2259  cfg = irq_cfg(irq);
2260  if (!cfg)
2261  continue;
2262 
2263  raw_spin_lock(&desc->lock);
2264 
2265  /*
2266  * Check if the irq migration is in progress. If so, we
2267  * haven't received the cleanup request yet for this irq.
2268  */
2269  if (cfg->move_in_progress)
2270  goto unlock;
2271 
2272  if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2273  goto unlock;
2274 
2275  irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2276  /*
2277  * Check if the vector that needs to be cleanedup is
2278  * registered at the cpu's IRR. If so, then this is not
2279  * the best time to clean it up. Lets clean it up in the
2280  * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2281  * to myself.
2282  */
2283  if (irr & (1 << (vector % 32))) {
2284  apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2285  goto unlock;
2286  }
2287  __this_cpu_write(vector_irq[vector], -1);
2288 unlock:
2289  raw_spin_unlock(&desc->lock);
2290  }
2291 
2292  irq_exit();
2293 }
2294 
2295 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2296 {
2297  unsigned me;
2298 
2299  if (likely(!cfg->move_in_progress))
2300  return;
2301 
2302  me = smp_processor_id();
2303 
2304  if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2305  send_cleanup_vector(cfg);
2306 }
2307 
2308 static void irq_complete_move(struct irq_cfg *cfg)
2309 {
2310  __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2311 }
2312 
2313 void irq_force_complete_move(int irq)
2314 {
2315  struct irq_cfg *cfg = irq_get_chip_data(irq);
2316 
2317  if (!cfg)
2318  return;
2319 
2320  __irq_complete_move(cfg, cfg->vector);
2321 }
2322 #else
2323 static inline void irq_complete_move(struct irq_cfg *cfg) { }
2324 #endif
2325 
2326 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2327 {
2328  int apic, pin;
2329  struct irq_pin_list *entry;
2330  u8 vector = cfg->vector;
2331 
2332  for_each_irq_pin(entry, cfg->irq_2_pin) {
2333  unsigned int reg;
2334 
2335  apic = entry->apic;
2336  pin = entry->pin;
2337  /*
2338  * With interrupt-remapping, destination information comes
2339  * from interrupt-remapping table entry.
2340  */
2341  if (!irq_remapped(cfg))
2342  io_apic_write(apic, 0x11 + pin*2, dest);
2343  reg = io_apic_read(apic, 0x10 + pin*2);
2344  reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2345  reg |= vector;
2346  io_apic_modify(apic, 0x10 + pin*2, reg);
2347  }
2348 }
2349 
2350 /*
2351  * Either sets data->affinity to a valid value, and returns
2352  * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2353  * leaves data->affinity untouched.
2354  */
2355 int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2356  unsigned int *dest_id)
2357 {
2358  struct irq_cfg *cfg = data->chip_data;
2359  unsigned int irq = data->irq;
2360  int err;
2361 
2362  if (!config_enabled(CONFIG_SMP))
2363  return -1;
2364 
2365  if (!cpumask_intersects(mask, cpu_online_mask))
2366  return -EINVAL;
2367 
2368  err = assign_irq_vector(irq, cfg, mask);
2369  if (err)
2370  return err;
2371 
2372  err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, dest_id);
2373  if (err) {
2374  if (assign_irq_vector(irq, cfg, data->affinity))
2375  pr_err("Failed to recover vector for irq %d\n", irq);
2376  return err;
2377  }
2378 
2379  cpumask_copy(data->affinity, mask);
2380 
2381  return 0;
2382 }
2383 
2384 static int
2385 ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2386  bool force)
2387 {
2388  unsigned int dest, irq = data->irq;
2389  unsigned long flags;
2390  int ret;
2391 
2392  if (!config_enabled(CONFIG_SMP))
2393  return -1;
2394 
2395  raw_spin_lock_irqsave(&ioapic_lock, flags);
2396  ret = __ioapic_set_affinity(data, mask, &dest);
2397  if (!ret) {
2398  /* Only the high 8 bits are valid. */
2399  dest = SET_APIC_LOGICAL_ID(dest);
2400  __target_IO_APIC_irq(irq, dest, data->chip_data);
2401  ret = IRQ_SET_MASK_OK_NOCOPY;
2402  }
2403  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2404  return ret;
2405 }
2406 
2407 static void ack_apic_edge(struct irq_data *data)
2408 {
2409  irq_complete_move(data->chip_data);
2410  irq_move_irq(data);
2411  ack_APIC_irq();
2412 }
2413 
2415 
2416 #ifdef CONFIG_GENERIC_PENDING_IRQ
2417 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
2418 {
2419  struct irq_pin_list *entry;
2420  unsigned long flags;
2421 
2422  raw_spin_lock_irqsave(&ioapic_lock, flags);
2423  for_each_irq_pin(entry, cfg->irq_2_pin) {
2424  unsigned int reg;
2425  int pin;
2426 
2427  pin = entry->pin;
2428  reg = io_apic_read(entry->apic, 0x10 + pin*2);
2429  /* Is the remote IRR bit set? */
2430  if (reg & IO_APIC_REDIR_REMOTE_IRR) {
2431  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2432  return true;
2433  }
2434  }
2435  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2436 
2437  return false;
2438 }
2439 
2440 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2441 {
2442  /* If we are moving the irq we need to mask it */
2443  if (unlikely(irqd_is_setaffinity_pending(data))) {
2444  mask_ioapic(cfg);
2445  return true;
2446  }
2447  return false;
2448 }
2449 
2450 static inline void ioapic_irqd_unmask(struct irq_data *data,
2451  struct irq_cfg *cfg, bool masked)
2452 {
2453  if (unlikely(masked)) {
2454  /* Only migrate the irq if the ack has been received.
2455  *
2456  * On rare occasions the broadcast level triggered ack gets
2457  * delayed going to ioapics, and if we reprogram the
2458  * vector while Remote IRR is still set the irq will never
2459  * fire again.
2460  *
2461  * To prevent this scenario we read the Remote IRR bit
2462  * of the ioapic. This has two effects.
2463  * - On any sane system the read of the ioapic will
2464  * flush writes (and acks) going to the ioapic from
2465  * this cpu.
2466  * - We get to see if the ACK has actually been delivered.
2467  *
2468  * Based on failed experiments of reprogramming the
2469  * ioapic entry from outside of irq context starting
2470  * with masking the ioapic entry and then polling until
2471  * Remote IRR was clear before reprogramming the
2472  * ioapic I don't trust the Remote IRR bit to be
2473  * completey accurate.
2474  *
2475  * However there appears to be no other way to plug
2476  * this race, so if the Remote IRR bit is not
2477  * accurate and is causing problems then it is a hardware bug
2478  * and you can go talk to the chipset vendor about it.
2479  */
2480  if (!io_apic_level_ack_pending(cfg))
2481  irq_move_masked_irq(data);
2482  unmask_ioapic(cfg);
2483  }
2484 }
2485 #else
2486 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2487 {
2488  return false;
2489 }
2490 static inline void ioapic_irqd_unmask(struct irq_data *data,
2491  struct irq_cfg *cfg, bool masked)
2492 {
2493 }
2494 #endif
2495 
2496 static void ack_apic_level(struct irq_data *data)
2497 {
2498  struct irq_cfg *cfg = data->chip_data;
2499  int i, irq = data->irq;
2500  unsigned long v;
2501  bool masked;
2502 
2503  irq_complete_move(cfg);
2504  masked = ioapic_irqd_mask(data, cfg);
2505 
2506  /*
2507  * It appears there is an erratum which affects at least version 0x11
2508  * of I/O APIC (that's the 82093AA and cores integrated into various
2509  * chipsets). Under certain conditions a level-triggered interrupt is
2510  * erroneously delivered as edge-triggered one but the respective IRR
2511  * bit gets set nevertheless. As a result the I/O unit expects an EOI
2512  * message but it will never arrive and further interrupts are blocked
2513  * from the source. The exact reason is so far unknown, but the
2514  * phenomenon was observed when two consecutive interrupt requests
2515  * from a given source get delivered to the same CPU and the source is
2516  * temporarily disabled in between.
2517  *
2518  * A workaround is to simulate an EOI message manually. We achieve it
2519  * by setting the trigger mode to edge and then to level when the edge
2520  * trigger mode gets detected in the TMR of a local APIC for a
2521  * level-triggered interrupt. We mask the source for the time of the
2522  * operation to prevent an edge-triggered interrupt escaping meanwhile.
2523  * The idea is from Manfred Spraul. --macro
2524  *
2525  * Also in the case when cpu goes offline, fixup_irqs() will forward
2526  * any unhandled interrupt on the offlined cpu to the new cpu
2527  * destination that is handling the corresponding interrupt. This
2528  * interrupt forwarding is done via IPI's. Hence, in this case also
2529  * level-triggered io-apic interrupt will be seen as an edge
2530  * interrupt in the IRR. And we can't rely on the cpu's EOI
2531  * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2532  * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2533  * supporting EOI register, we do an explicit EOI to clear the
2534  * remote IRR and on IO-APIC's which don't have an EOI register,
2535  * we use the above logic (mask+edge followed by unmask+level) from
2536  * Manfred Spraul to clear the remote IRR.
2537  */
2538  i = cfg->vector;
2539  v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2540 
2541  /*
2542  * We must acknowledge the irq before we move it or the acknowledge will
2543  * not propagate properly.
2544  */
2545  ack_APIC_irq();
2546 
2547  /*
2548  * Tail end of clearing remote IRR bit (either by delivering the EOI
2549  * message via io-apic EOI register write or simulating it using
2550  * mask+edge followed by unnask+level logic) manually when the
2551  * level triggered interrupt is seen as the edge triggered interrupt
2552  * at the cpu.
2553  */
2554  if (!(v & (1 << (i & 0x1f)))) {
2555  atomic_inc(&irq_mis_count);
2556 
2557  eoi_ioapic_irq(irq, cfg);
2558  }
2559 
2560  ioapic_irqd_unmask(data, cfg, masked);
2561 }
2562 
2563 #ifdef CONFIG_IRQ_REMAP
2564 static void ir_ack_apic_edge(struct irq_data *data)
2565 {
2566  ack_APIC_irq();
2567 }
2568 
2569 static void ir_ack_apic_level(struct irq_data *data)
2570 {
2571  ack_APIC_irq();
2572  eoi_ioapic_irq(data->irq, data->chip_data);
2573 }
2574 
2575 static void ir_print_prefix(struct irq_data *data, struct seq_file *p)
2576 {
2577  seq_printf(p, " IR-%s", data->chip->name);
2578 }
2579 
2580 static void irq_remap_modify_chip_defaults(struct irq_chip *chip)
2581 {
2582  chip->irq_print_chip = ir_print_prefix;
2583  chip->irq_ack = ir_ack_apic_edge;
2584  chip->irq_eoi = ir_ack_apic_level;
2585 
2587 }
2588 #endif /* CONFIG_IRQ_REMAP */
2589 
2590 static struct irq_chip ioapic_chip __read_mostly = {
2591  .name = "IO-APIC",
2592  .irq_startup = startup_ioapic_irq,
2593  .irq_mask = mask_ioapic_irq,
2594  .irq_unmask = unmask_ioapic_irq,
2595  .irq_ack = ack_apic_edge,
2596  .irq_eoi = ack_apic_level,
2597  .irq_set_affinity = ioapic_set_affinity,
2598  .irq_retrigger = ioapic_retrigger_irq,
2599 };
2600 
2601 static inline void init_IO_APIC_traps(void)
2602 {
2603  struct irq_cfg *cfg;
2604  unsigned int irq;
2605 
2606  /*
2607  * NOTE! The local APIC isn't very good at handling
2608  * multiple interrupts at the same interrupt level.
2609  * As the interrupt level is determined by taking the
2610  * vector number and shifting that right by 4, we
2611  * want to spread these out a bit so that they don't
2612  * all fall in the same interrupt level.
2613  *
2614  * Also, we've got to be careful not to trash gate
2615  * 0x80, because int 0x80 is hm, kind of importantish. ;)
2616  */
2617  for_each_active_irq(irq) {
2618  cfg = irq_get_chip_data(irq);
2619  if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2620  /*
2621  * Hmm.. We don't have an entry for this,
2622  * so default to an old-fashioned 8259
2623  * interrupt if we can..
2624  */
2625  if (irq < legacy_pic->nr_legacy_irqs)
2626  legacy_pic->make_irq(irq);
2627  else
2628  /* Strange. Oh, well.. */
2629  irq_set_chip(irq, &no_irq_chip);
2630  }
2631  }
2632 }
2633 
2634 /*
2635  * The local APIC irq-chip implementation:
2636  */
2637 
2638 static void mask_lapic_irq(struct irq_data *data)
2639 {
2640  unsigned long v;
2641 
2642  v = apic_read(APIC_LVT0);
2643  apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2644 }
2645 
2646 static void unmask_lapic_irq(struct irq_data *data)
2647 {
2648  unsigned long v;
2649 
2650  v = apic_read(APIC_LVT0);
2651  apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2652 }
2653 
2654 static void ack_lapic_irq(struct irq_data *data)
2655 {
2656  ack_APIC_irq();
2657 }
2658 
2659 static struct irq_chip lapic_chip __read_mostly = {
2660  .name = "local-APIC",
2661  .irq_mask = mask_lapic_irq,
2662  .irq_unmask = unmask_lapic_irq,
2663  .irq_ack = ack_lapic_irq,
2664 };
2665 
2666 static void lapic_register_intr(int irq)
2667 {
2668  irq_clear_status_flags(irq, IRQ_LEVEL);
2670  "edge");
2671 }
2672 
2673 /*
2674  * This looks a bit hackish but it's about the only one way of sending
2675  * a few INTA cycles to 8259As and any associated glue logic. ICR does
2676  * not support the ExtINT mode, unfortunately. We need to send these
2677  * cycles as some i82489DX-based boards have glue logic that keeps the
2678  * 8259A interrupt line asserted until INTA. --macro
2679  */
2680 static inline void __init unlock_ExtINT_logic(void)
2681 {
2682  int apic, pin, i;
2683  struct IO_APIC_route_entry entry0, entry1;
2684  unsigned char save_control, save_freq_select;
2685 
2686  pin = find_isa_irq_pin(8, mp_INT);
2687  if (pin == -1) {
2688  WARN_ON_ONCE(1);
2689  return;
2690  }
2691  apic = find_isa_irq_apic(8, mp_INT);
2692  if (apic == -1) {
2693  WARN_ON_ONCE(1);
2694  return;
2695  }
2696 
2697  entry0 = ioapic_read_entry(apic, pin);
2698  clear_IO_APIC_pin(apic, pin);
2699 
2700  memset(&entry1, 0, sizeof(entry1));
2701 
2702  entry1.dest_mode = 0; /* physical delivery */
2703  entry1.mask = 0; /* unmask IRQ now */
2704  entry1.dest = hard_smp_processor_id();
2705  entry1.delivery_mode = dest_ExtINT;
2706  entry1.polarity = entry0.polarity;
2707  entry1.trigger = 0;
2708  entry1.vector = 0;
2709 
2710  ioapic_write_entry(apic, pin, entry1);
2711 
2712  save_control = CMOS_READ(RTC_CONTROL);
2713  save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2714  CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2715  RTC_FREQ_SELECT);
2716  CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2717 
2718  i = 100;
2719  while (i-- > 0) {
2720  mdelay(10);
2721  if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2722  i -= 10;
2723  }
2724 
2725  CMOS_WRITE(save_control, RTC_CONTROL);
2726  CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2727  clear_IO_APIC_pin(apic, pin);
2728 
2729  ioapic_write_entry(apic, pin, entry0);
2730 }
2731 
2732 static int disable_timer_pin_1 __initdata;
2733 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2734 static int __init disable_timer_pin_setup(char *arg)
2735 {
2736  disable_timer_pin_1 = 1;
2737  return 0;
2738 }
2739 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2740 
2741 int timer_through_8259 __initdata;
2742 
2743 /*
2744  * This code may look a bit paranoid, but it's supposed to cooperate with
2745  * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2746  * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2747  * fanatically on his truly buggy board.
2748  *
2749  * FIXME: really need to revamp this for all platforms.
2750  */
2751 static inline void __init check_timer(void)
2752 {
2753  struct irq_cfg *cfg = irq_get_chip_data(0);
2754  int node = cpu_to_node(0);
2755  int apic1, pin1, apic2, pin2;
2756  unsigned long flags;
2757  int no_pin1 = 0;
2758 
2759  local_irq_save(flags);
2760 
2761  /*
2762  * get/set the timer IRQ vector:
2763  */
2764  legacy_pic->mask(0);
2765  assign_irq_vector(0, cfg, apic->target_cpus());
2766 
2767  /*
2768  * As IRQ0 is to be enabled in the 8259A, the virtual
2769  * wire has to be disabled in the local APIC. Also
2770  * timer interrupts need to be acknowledged manually in
2771  * the 8259A for the i82489DX when using the NMI
2772  * watchdog as that APIC treats NMIs as level-triggered.
2773  * The AEOI mode will finish them in the 8259A
2774  * automatically.
2775  */
2776  apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2777  legacy_pic->init(1);
2778 
2779  pin1 = find_isa_irq_pin(0, mp_INT);
2780  apic1 = find_isa_irq_apic(0, mp_INT);
2781  pin2 = ioapic_i8259.pin;
2782  apic2 = ioapic_i8259.apic;
2783 
2784  apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2785  "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2786  cfg->vector, apic1, pin1, apic2, pin2);
2787 
2788  /*
2789  * Some BIOS writers are clueless and report the ExtINTA
2790  * I/O APIC input from the cascaded 8259A as the timer
2791  * interrupt input. So just in case, if only one pin
2792  * was found above, try it both directly and through the
2793  * 8259A.
2794  */
2795  if (pin1 == -1) {
2797  panic("BIOS bug: timer not connected to IO-APIC");
2798  pin1 = pin2;
2799  apic1 = apic2;
2800  no_pin1 = 1;
2801  } else if (pin2 == -1) {
2802  pin2 = pin1;
2803  apic2 = apic1;
2804  }
2805 
2806  if (pin1 != -1) {
2807  /*
2808  * Ok, does IRQ0 through the IOAPIC work?
2809  */
2810  if (no_pin1) {
2811  add_pin_to_irq_node(cfg, node, apic1, pin1);
2812  setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2813  } else {
2814  /* for edge trigger, setup_ioapic_irq already
2815  * leave it unmasked.
2816  * so only need to unmask if it is level-trigger
2817  * do we really have level trigger timer?
2818  */
2819  int idx;
2820  idx = find_irq_entry(apic1, pin1, mp_INT);
2821  if (idx != -1 && irq_trigger(idx))
2822  unmask_ioapic(cfg);
2823  }
2824  if (timer_irq_works()) {
2825  if (disable_timer_pin_1 > 0)
2826  clear_IO_APIC_pin(0, pin1);
2827  goto out;
2828  }
2830  panic("timer doesn't work through Interrupt-remapped IO-APIC");
2832  clear_IO_APIC_pin(apic1, pin1);
2833  if (!no_pin1)
2834  apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2835  "8254 timer not connected to IO-APIC\n");
2836 
2837  apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2838  "(IRQ0) through the 8259A ...\n");
2840  "..... (found apic %d pin %d) ...\n", apic2, pin2);
2841  /*
2842  * legacy devices should be connected to IO APIC #0
2843  */
2844  replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2845  setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2846  legacy_pic->unmask(0);
2847  if (timer_irq_works()) {
2848  apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2849  timer_through_8259 = 1;
2850  goto out;
2851  }
2852  /*
2853  * Cleanup, just in case ...
2854  */
2856  legacy_pic->mask(0);
2857  clear_IO_APIC_pin(apic2, pin2);
2858  apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2859  }
2860 
2862  "...trying to set up timer as Virtual Wire IRQ...\n");
2863 
2864  lapic_register_intr(0);
2865  apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2866  legacy_pic->unmask(0);
2867 
2868  if (timer_irq_works()) {
2869  apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2870  goto out;
2871  }
2873  legacy_pic->mask(0);
2874  apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2875  apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2876 
2878  "...trying to set up timer as ExtINT IRQ...\n");
2879 
2880  legacy_pic->init(0);
2881  legacy_pic->make_irq(0);
2882  apic_write(APIC_LVT0, APIC_DM_EXTINT);
2883 
2884  unlock_ExtINT_logic();
2885 
2886  if (timer_irq_works()) {
2887  apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2888  goto out;
2889  }
2891  apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2892  if (x2apic_preenabled)
2894  "Perhaps problem with the pre-enabled x2apic mode\n"
2895  "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2896  panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2897  "report. Then try booting with the 'noapic' option.\n");
2898 out:
2899  local_irq_restore(flags);
2900 }
2901 
2902 /*
2903  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2904  * to devices. However there may be an I/O APIC pin available for
2905  * this interrupt regardless. The pin may be left unconnected, but
2906  * typically it will be reused as an ExtINT cascade interrupt for
2907  * the master 8259A. In the MPS case such a pin will normally be
2908  * reported as an ExtINT interrupt in the MP table. With ACPI
2909  * there is no provision for ExtINT interrupts, and in the absence
2910  * of an override it would be treated as an ordinary ISA I/O APIC
2911  * interrupt, that is edge-triggered and unmasked by default. We
2912  * used to do this, but it caused problems on some systems because
2913  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2914  * the same ExtINT cascade interrupt to drive the local APIC of the
2915  * bootstrap processor. Therefore we refrain from routing IRQ2 to
2916  * the I/O APIC in all cases now. No actual device should request
2917  * it anyway. --macro
2918  */
2919 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2920 
2922 {
2923 
2924  /*
2925  * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2926  */
2928 
2929  apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2930  /*
2931  * Set up IO-APIC IRQ routing.
2932  */
2933  x86_init.mpparse.setup_ioapic_ids();
2934 
2935  sync_Arb_IDs();
2936  setup_IO_APIC_irqs();
2937  init_IO_APIC_traps();
2939  check_timer();
2940 }
2941 
2942 /*
2943  * Called after all the initialization is done. If we didn't find any
2944  * APIC bugs then we can allow the modify fast path
2945  */
2946 
2947 static int __init io_apic_bug_finalize(void)
2948 {
2949  if (sis_apic_bug == -1)
2950  sis_apic_bug = 0;
2951  return 0;
2952 }
2953 
2954 late_initcall(io_apic_bug_finalize);
2955 
2956 static void resume_ioapic_id(int ioapic_idx)
2957 {
2958  unsigned long flags;
2959  union IO_APIC_reg_00 reg_00;
2960 
2961  raw_spin_lock_irqsave(&ioapic_lock, flags);
2962  reg_00.raw = io_apic_read(ioapic_idx, 0);
2963  if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2964  reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2965  io_apic_write(ioapic_idx, 0, reg_00.raw);
2966  }
2967  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2968 }
2969 
2970 static void ioapic_resume(void)
2971 {
2972  int ioapic_idx;
2973 
2974  for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--)
2975  resume_ioapic_id(ioapic_idx);
2976 
2978 }
2979 
2980 static struct syscore_ops ioapic_syscore_ops = {
2981  .suspend = save_ioapic_entries,
2982  .resume = ioapic_resume,
2983 };
2984 
2985 static int __init ioapic_init_ops(void)
2986 {
2987  register_syscore_ops(&ioapic_syscore_ops);
2988 
2989  return 0;
2990 }
2991 
2992 device_initcall(ioapic_init_ops);
2993 
2994 /*
2995  * Dynamic irq allocate and deallocation
2996  */
2997 unsigned int create_irq_nr(unsigned int from, int node)
2998 {
2999  struct irq_cfg *cfg;
3000  unsigned long flags;
3001  unsigned int ret = 0;
3002  int irq;
3003 
3004  if (from < nr_irqs_gsi)
3005  from = nr_irqs_gsi;
3006 
3007  irq = alloc_irq_from(from, node);
3008  if (irq < 0)
3009  return 0;
3010  cfg = alloc_irq_cfg(irq, node);
3011  if (!cfg) {
3012  free_irq_at(irq, NULL);
3013  return 0;
3014  }
3015 
3017  if (!__assign_irq_vector(irq, cfg, apic->target_cpus()))
3018  ret = irq;
3020 
3021  if (ret) {
3022  irq_set_chip_data(irq, cfg);
3023  irq_clear_status_flags(irq, IRQ_NOREQUEST);
3024  } else {
3025  free_irq_at(irq, cfg);
3026  }
3027  return ret;
3028 }
3029 
3030 int create_irq(void)
3031 {
3032  int node = cpu_to_node(0);
3033  unsigned int irq_want;
3034  int irq;
3035 
3036  irq_want = nr_irqs_gsi;
3037  irq = create_irq_nr(irq_want, node);
3038 
3039  if (irq == 0)
3040  irq = -1;
3041 
3042  return irq;
3043 }
3044 
3045 void destroy_irq(unsigned int irq)
3046 {
3047  struct irq_cfg *cfg = irq_get_chip_data(irq);
3048  unsigned long flags;
3049 
3050  irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
3051 
3052  if (irq_remapped(cfg))
3053  free_remapped_irq(irq);
3055  __clear_irq_vector(irq, cfg);
3057  free_irq_at(irq, cfg);
3058 }
3059 
3060 /*
3061  * MSI message composition
3062  */
3063 #ifdef CONFIG_PCI_MSI
3064 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3065  struct msi_msg *msg, u8 hpet_id)
3066 {
3067  struct irq_cfg *cfg;
3068  int err;
3069  unsigned dest;
3070 
3071  if (disable_apic)
3072  return -ENXIO;
3073 
3074  cfg = irq_cfg(irq);
3075  err = assign_irq_vector(irq, cfg, apic->target_cpus());
3076  if (err)
3077  return err;
3078 
3079  err = apic->cpu_mask_to_apicid_and(cfg->domain,
3080  apic->target_cpus(), &dest);
3081  if (err)
3082  return err;
3083 
3084  if (irq_remapped(cfg)) {
3085  compose_remapped_msi_msg(pdev, irq, dest, msg, hpet_id);
3086  return err;
3087  }
3088 
3089  if (x2apic_enabled())
3090  msg->address_hi = MSI_ADDR_BASE_HI |
3091  MSI_ADDR_EXT_DEST_ID(dest);
3092  else
3094 
3095  msg->address_lo =
3097  ((apic->irq_dest_mode == 0) ?
3100  ((apic->irq_delivery_mode != dest_LowestPrio) ?
3103  MSI_ADDR_DEST_ID(dest);
3104 
3105  msg->data =
3108  ((apic->irq_delivery_mode != dest_LowestPrio) ?
3111  MSI_DATA_VECTOR(cfg->vector);
3112 
3113  return err;
3114 }
3115 
3116 static int
3117 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3118 {
3119  struct irq_cfg *cfg = data->chip_data;
3120  struct msi_msg msg;
3121  unsigned int dest;
3122 
3123  if (__ioapic_set_affinity(data, mask, &dest))
3124  return -1;
3125 
3126  __get_cached_msi_msg(data->msi_desc, &msg);
3127 
3128  msg.data &= ~MSI_DATA_VECTOR_MASK;
3129  msg.data |= MSI_DATA_VECTOR(cfg->vector);
3131  msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3132 
3133  __write_msi_msg(data->msi_desc, &msg);
3134 
3135  return IRQ_SET_MASK_OK_NOCOPY;
3136 }
3137 
3138 /*
3139  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3140  * which implement the MSI or MSI-X Capability Structure.
3141  */
3142 static struct irq_chip msi_chip = {
3143  .name = "PCI-MSI",
3144  .irq_unmask = unmask_msi_irq,
3145  .irq_mask = mask_msi_irq,
3146  .irq_ack = ack_apic_edge,
3147  .irq_set_affinity = msi_set_affinity,
3148  .irq_retrigger = ioapic_retrigger_irq,
3149 };
3150 
3151 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3152 {
3153  struct irq_chip *chip = &msi_chip;
3154  struct msi_msg msg;
3155  int ret;
3156 
3157  ret = msi_compose_msg(dev, irq, &msg, -1);
3158  if (ret < 0)
3159  return ret;
3160 
3161  irq_set_msi_desc(irq, msidesc);
3162  write_msi_msg(irq, &msg);
3163 
3164  if (irq_remapped(irq_get_chip_data(irq))) {
3165  irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3166  irq_remap_modify_chip_defaults(chip);
3167  }
3168 
3169  irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3170 
3171  dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3172 
3173  return 0;
3174 }
3175 
3176 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3177 {
3178  int node, ret, sub_handle, index = 0;
3179  unsigned int irq, irq_want;
3180  struct msi_desc *msidesc;
3181 
3182  /* x86 doesn't support multiple MSI yet */
3183  if (type == PCI_CAP_ID_MSI && nvec > 1)
3184  return 1;
3185 
3186  node = dev_to_node(&dev->dev);
3187  irq_want = nr_irqs_gsi;
3188  sub_handle = 0;
3189  list_for_each_entry(msidesc, &dev->msi_list, list) {
3190  irq = create_irq_nr(irq_want, node);
3191  if (irq == 0)
3192  return -1;
3193  irq_want = irq + 1;
3194  if (!irq_remapping_enabled)
3195  goto no_ir;
3196 
3197  if (!sub_handle) {
3198  /*
3199  * allocate the consecutive block of IRTE's
3200  * for 'nvec'
3201  */
3202  index = msi_alloc_remapped_irq(dev, irq, nvec);
3203  if (index < 0) {
3204  ret = index;
3205  goto error;
3206  }
3207  } else {
3208  ret = msi_setup_remapped_irq(dev, irq, index,
3209  sub_handle);
3210  if (ret < 0)
3211  goto error;
3212  }
3213 no_ir:
3214  ret = setup_msi_irq(dev, msidesc, irq);
3215  if (ret < 0)
3216  goto error;
3217  sub_handle++;
3218  }
3219  return 0;
3220 
3221 error:
3222  destroy_irq(irq);
3223  return ret;
3224 }
3225 
3226 void native_teardown_msi_irq(unsigned int irq)
3227 {
3228  destroy_irq(irq);
3229 }
3230 
3231 #ifdef CONFIG_DMAR_TABLE
3232 static int
3233 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3234  bool force)
3235 {
3236  struct irq_cfg *cfg = data->chip_data;
3237  unsigned int dest, irq = data->irq;
3238  struct msi_msg msg;
3239 
3240  if (__ioapic_set_affinity(data, mask, &dest))
3241  return -1;
3242 
3243  dmar_msi_read(irq, &msg);
3244 
3245  msg.data &= ~MSI_DATA_VECTOR_MASK;
3246  msg.data |= MSI_DATA_VECTOR(cfg->vector);
3248  msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3250 
3251  dmar_msi_write(irq, &msg);
3252 
3253  return IRQ_SET_MASK_OK_NOCOPY;
3254 }
3255 
3256 static struct irq_chip dmar_msi_type = {
3257  .name = "DMAR_MSI",
3258  .irq_unmask = dmar_msi_unmask,
3259  .irq_mask = dmar_msi_mask,
3260  .irq_ack = ack_apic_edge,
3261  .irq_set_affinity = dmar_msi_set_affinity,
3262  .irq_retrigger = ioapic_retrigger_irq,
3263 };
3264 
3265 int arch_setup_dmar_msi(unsigned int irq)
3266 {
3267  int ret;
3268  struct msi_msg msg;
3269 
3270  ret = msi_compose_msg(NULL, irq, &msg, -1);
3271  if (ret < 0)
3272  return ret;
3273  dmar_msi_write(irq, &msg);
3274  irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3275  "edge");
3276  return 0;
3277 }
3278 #endif
3279 
3280 #ifdef CONFIG_HPET_TIMER
3281 
3282 static int hpet_msi_set_affinity(struct irq_data *data,
3283  const struct cpumask *mask, bool force)
3284 {
3285  struct irq_cfg *cfg = data->chip_data;
3286  struct msi_msg msg;
3287  unsigned int dest;
3288 
3289  if (__ioapic_set_affinity(data, mask, &dest))
3290  return -1;
3291 
3292  hpet_msi_read(data->handler_data, &msg);
3293 
3294  msg.data &= ~MSI_DATA_VECTOR_MASK;
3295  msg.data |= MSI_DATA_VECTOR(cfg->vector);
3297  msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3298 
3299  hpet_msi_write(data->handler_data, &msg);
3300 
3301  return IRQ_SET_MASK_OK_NOCOPY;
3302 }
3303 
3304 static struct irq_chip hpet_msi_type = {
3305  .name = "HPET_MSI",
3306  .irq_unmask = hpet_msi_unmask,
3307  .irq_mask = hpet_msi_mask,
3308  .irq_ack = ack_apic_edge,
3309  .irq_set_affinity = hpet_msi_set_affinity,
3310  .irq_retrigger = ioapic_retrigger_irq,
3311 };
3312 
3313 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3314 {
3315  struct irq_chip *chip = &hpet_msi_type;
3316  struct msi_msg msg;
3317  int ret;
3318 
3319  if (irq_remapping_enabled) {
3320  if (!setup_hpet_msi_remapped(irq, id))
3321  return -1;
3322  }
3323 
3324  ret = msi_compose_msg(NULL, irq, &msg, id);
3325  if (ret < 0)
3326  return ret;
3327 
3328  hpet_msi_write(irq_get_handler_data(irq), &msg);
3329  irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3330  if (irq_remapped(irq_get_chip_data(irq)))
3331  irq_remap_modify_chip_defaults(chip);
3332 
3333  irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3334  return 0;
3335 }
3336 #endif
3337 
3338 #endif /* CONFIG_PCI_MSI */
3339 /*
3340  * Hypertransport interrupt support
3341  */
3342 #ifdef CONFIG_HT_IRQ
3343 
3344 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3345 {
3346  struct ht_irq_msg msg;
3347  fetch_ht_irq_msg(irq, &msg);
3348 
3351 
3352  msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3353  msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3354 
3355  write_ht_irq_msg(irq, &msg);
3356 }
3357 
3358 static int
3359 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3360 {
3361  struct irq_cfg *cfg = data->chip_data;
3362  unsigned int dest;
3363 
3364  if (__ioapic_set_affinity(data, mask, &dest))
3365  return -1;
3366 
3367  target_ht_irq(data->irq, dest, cfg->vector);
3368  return IRQ_SET_MASK_OK_NOCOPY;
3369 }
3370 
3371 static struct irq_chip ht_irq_chip = {
3372  .name = "PCI-HT",
3373  .irq_mask = mask_ht_irq,
3374  .irq_unmask = unmask_ht_irq,
3375  .irq_ack = ack_apic_edge,
3376  .irq_set_affinity = ht_set_affinity,
3377  .irq_retrigger = ioapic_retrigger_irq,
3378 };
3379 
3380 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3381 {
3382  struct irq_cfg *cfg;
3383  struct ht_irq_msg msg;
3384  unsigned dest;
3385  int err;
3386 
3387  if (disable_apic)
3388  return -ENXIO;
3389 
3390  cfg = irq_cfg(irq);
3391  err = assign_irq_vector(irq, cfg, apic->target_cpus());
3392  if (err)
3393  return err;
3394 
3395  err = apic->cpu_mask_to_apicid_and(cfg->domain,
3396  apic->target_cpus(), &dest);
3397  if (err)
3398  return err;
3399 
3400  msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3401 
3402  msg.address_lo =
3403  HT_IRQ_LOW_BASE |
3404  HT_IRQ_LOW_DEST_ID(dest) |
3405  HT_IRQ_LOW_VECTOR(cfg->vector) |
3406  ((apic->irq_dest_mode == 0) ?
3410  ((apic->irq_delivery_mode != dest_LowestPrio) ?
3414 
3415  write_ht_irq_msg(irq, &msg);
3416 
3417  irq_set_chip_and_handler_name(irq, &ht_irq_chip,
3418  handle_edge_irq, "edge");
3419 
3420  dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3421 
3422  return 0;
3423 }
3424 #endif /* CONFIG_HT_IRQ */
3425 
3426 static int
3427 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3428 {
3429  struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3430  int ret;
3431 
3432  if (!cfg)
3433  return -EINVAL;
3434  ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3435  if (!ret)
3436  setup_ioapic_irq(irq, cfg, attr);
3437  return ret;
3438 }
3439 
3440 int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3441  struct io_apic_irq_attr *attr)
3442 {
3443  unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin;
3444  int ret;
3445 
3446  /* Avoid redundant programming */
3447  if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) {
3448  pr_debug("Pin %d-%d already programmed\n",
3449  mpc_ioapic_id(ioapic_idx), pin);
3450  return 0;
3451  }
3452  ret = io_apic_setup_irq_pin(irq, node, attr);
3453  if (!ret)
3454  set_bit(pin, ioapics[ioapic_idx].pin_programmed);
3455  return ret;
3456 }
3457 
3458 static int __init io_apic_get_redir_entries(int ioapic)
3459 {
3460  union IO_APIC_reg_01 reg_01;
3461  unsigned long flags;
3462 
3463  raw_spin_lock_irqsave(&ioapic_lock, flags);
3464  reg_01.raw = io_apic_read(ioapic, 1);
3465  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3466 
3467  /* The register returns the maximum index redir index
3468  * supported, which is one less than the total number of redir
3469  * entries.
3470  */
3471  return reg_01.bits.entries + 1;
3472 }
3473 
3474 static void __init probe_nr_irqs_gsi(void)
3475 {
3476  int nr;
3477 
3478  nr = gsi_top + NR_IRQS_LEGACY;
3479  if (nr > nr_irqs_gsi)
3480  nr_irqs_gsi = nr;
3481 
3482  printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3483 }
3484 
3486 {
3487  return nr_irqs_gsi;
3488 }
3489 
3491 {
3492  int nr;
3493 
3494  if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3495  nr_irqs = NR_VECTORS * nr_cpu_ids;
3496 
3497  nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3498 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3499  /*
3500  * for MSI and HT dyn irq
3501  */
3502  nr += nr_irqs_gsi * 16;
3503 #endif
3504  if (nr < nr_irqs)
3505  nr_irqs = nr;
3506 
3507  return NR_IRQS_LEGACY;
3508 }
3509 
3510 int io_apic_set_pci_routing(struct device *dev, int irq,
3511  struct io_apic_irq_attr *irq_attr)
3512 {
3513  int node;
3514 
3515  if (!IO_APIC_IRQ(irq)) {
3516  apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3517  irq_attr->ioapic);
3518  return -EINVAL;
3519  }
3520 
3521  node = dev ? dev_to_node(dev) : cpu_to_node(0);
3522 
3523  return io_apic_setup_irq_pin_once(irq, node, irq_attr);
3524 }
3525 
3526 #ifdef CONFIG_X86_32
3527 static int __init io_apic_get_unique_id(int ioapic, int apic_id)
3528 {
3529  union IO_APIC_reg_00 reg_00;
3530  static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3532  unsigned long flags;
3533  int i = 0;
3534 
3535  /*
3536  * The P4 platform supports up to 256 APIC IDs on two separate APIC
3537  * buses (one for LAPICs, one for IOAPICs), where predecessors only
3538  * supports up to 16 on one shared APIC bus.
3539  *
3540  * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3541  * advantage of new APIC bus architecture.
3542  */
3543 
3544  if (physids_empty(apic_id_map))
3545  apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3546 
3547  raw_spin_lock_irqsave(&ioapic_lock, flags);
3548  reg_00.raw = io_apic_read(ioapic, 0);
3549  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3550 
3551  if (apic_id >= get_physical_broadcast()) {
3552  printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3553  "%d\n", ioapic, apic_id, reg_00.bits.ID);
3554  apic_id = reg_00.bits.ID;
3555  }
3556 
3557  /*
3558  * Every APIC in a system must have a unique ID or we get lots of nice
3559  * 'stuck on smp_invalidate_needed IPI wait' messages.
3560  */
3561  if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3562 
3563  for (i = 0; i < get_physical_broadcast(); i++) {
3564  if (!apic->check_apicid_used(&apic_id_map, i))
3565  break;
3566  }
3567 
3568  if (i == get_physical_broadcast())
3569  panic("Max apic_id exceeded!\n");
3570 
3571  printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3572  "trying %d\n", ioapic, apic_id, i);
3573 
3574  apic_id = i;
3575  }
3576 
3577  apic->apicid_to_cpu_present(apic_id, &tmp);
3578  physids_or(apic_id_map, apic_id_map, tmp);
3579 
3580  if (reg_00.bits.ID != apic_id) {
3581  reg_00.bits.ID = apic_id;
3582 
3583  raw_spin_lock_irqsave(&ioapic_lock, flags);
3584  io_apic_write(ioapic, 0, reg_00.raw);
3585  reg_00.raw = io_apic_read(ioapic, 0);
3586  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3587 
3588  /* Sanity check */
3589  if (reg_00.bits.ID != apic_id) {
3590  pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
3591  ioapic);
3592  return -1;
3593  }
3594  }
3595 
3597  "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3598 
3599  return apic_id;
3600 }
3601 
3602 static u8 __init io_apic_unique_id(u8 id)
3603 {
3604  if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3606  return io_apic_get_unique_id(nr_ioapics, id);
3607  else
3608  return id;
3609 }
3610 #else
3611 static u8 __init io_apic_unique_id(u8 id)
3612 {
3613  int i;
3614  DECLARE_BITMAP(used, 256);
3615 
3616  bitmap_zero(used, 256);
3617  for (i = 0; i < nr_ioapics; i++) {
3619  }
3620  if (!test_bit(id, used))
3621  return id;
3622  return find_first_zero_bit(used, 256);
3623 }
3624 #endif
3625 
3626 static int __init io_apic_get_version(int ioapic)
3627 {
3628  union IO_APIC_reg_01 reg_01;
3629  unsigned long flags;
3630 
3631  raw_spin_lock_irqsave(&ioapic_lock, flags);
3632  reg_01.raw = io_apic_read(ioapic, 1);
3633  raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3634 
3635  return reg_01.bits.version;
3636 }
3637 
3638 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3639 {
3640  int ioapic, pin, idx;
3641 
3642  if (skip_ioapic_setup)
3643  return -1;
3644 
3645  ioapic = mp_find_ioapic(gsi);
3646  if (ioapic < 0)
3647  return -1;
3648 
3649  pin = mp_find_ioapic_pin(ioapic, gsi);
3650  if (pin < 0)
3651  return -1;
3652 
3653  idx = find_irq_entry(ioapic, pin, mp_INT);
3654  if (idx < 0)
3655  return -1;
3656 
3657  *trigger = irq_trigger(idx);
3658  *polarity = irq_polarity(idx);
3659  return 0;
3660 }
3661 
3662 /*
3663  * This function currently is only a helper for the i386 smp boot process where
3664  * we need to reprogram the ioredtbls to cater for the cpus which have come online
3665  * so mask in all cases should simply be apic->target_cpus()
3666  */
3667 #ifdef CONFIG_SMP
3668 void __init setup_ioapic_dest(void)
3669 {
3670  int pin, ioapic, irq, irq_entry;
3671  const struct cpumask *mask;
3672  struct irq_data *idata;
3673 
3674  if (skip_ioapic_setup == 1)
3675  return;
3676 
3677  for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
3678  for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) {
3679  irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3680  if (irq_entry == -1)
3681  continue;
3682  irq = pin_2_irq(irq_entry, ioapic, pin);
3683 
3684  if ((ioapic > 0) && (irq > 16))
3685  continue;
3686 
3687  idata = irq_get_irq_data(irq);
3688 
3689  /*
3690  * Honour affinities which have been set in early boot
3691  */
3692  if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3693  mask = idata->affinity;
3694  else
3695  mask = apic->target_cpus();
3696 
3698  set_remapped_irq_affinity(idata, mask, false);
3699  else
3700  ioapic_set_affinity(idata, mask, false);
3701  }
3702 
3703 }
3704 #endif
3705 
3706 #define IOAPIC_RESOURCE_NAME_SIZE 11
3707 
3708 static struct resource *ioapic_resources;
3709 
3710 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
3711 {
3712  unsigned long n;
3713  struct resource *res;
3714  char *mem;
3715  int i;
3716 
3717  if (nr_ioapics <= 0)
3718  return NULL;
3719 
3720  n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3721  n *= nr_ioapics;
3722 
3723  mem = alloc_bootmem(n);
3724  res = (void *)mem;
3725 
3726  mem += sizeof(struct resource) * nr_ioapics;
3727 
3728  for (i = 0; i < nr_ioapics; i++) {
3729  res[i].name = mem;
3731  snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3733  }
3734 
3735  ioapic_resources = res;
3736 
3737  return res;
3738 }
3739 
3741 {
3742  unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3743  struct resource *ioapic_res;
3744  int i;
3745 
3746  ioapic_res = ioapic_setup_resources(nr_ioapics);
3747  for (i = 0; i < nr_ioapics; i++) {
3748  if (smp_found_config) {
3749  ioapic_phys = mpc_ioapic_addr(i);
3750 #ifdef CONFIG_X86_32
3751  if (!ioapic_phys) {
3753  "WARNING: bogus zero IO-APIC "
3754  "address found in MPTABLE, "
3755  "disabling IO/APIC support!\n");
3756  smp_found_config = 0;
3757  skip_ioapic_setup = 1;
3758  goto fake_ioapic_page;
3759  }
3760 #endif
3761  } else {
3762 #ifdef CONFIG_X86_32
3763 fake_ioapic_page:
3764 #endif
3765  ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3766  ioapic_phys = __pa(ioapic_phys);
3767  }
3768  set_fixmap_nocache(idx, ioapic_phys);
3769  apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3770  __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3771  ioapic_phys);
3772  idx++;
3773 
3774  ioapic_res->start = ioapic_phys;
3775  ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3776  ioapic_res++;
3777  }
3778 
3779  probe_nr_irqs_gsi();
3780 }
3781 
3783 {
3784  int i;
3785  struct resource *r = ioapic_resources;
3786 
3787  if (!r) {
3788  if (nr_ioapics > 0)
3790  "IO APIC resources couldn't be allocated.\n");
3791  return;
3792  }
3793 
3794  for (i = 0; i < nr_ioapics; i++) {
3796  r++;
3797  }
3798 }
3799 
3801 {
3802  int i = 0;
3803 
3804  if (nr_ioapics == 0)
3805  return -1;
3806 
3807  /* Find the IOAPIC that manages this GSI. */
3808  for (i = 0; i < nr_ioapics; i++) {
3809  struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
3810  if ((gsi >= gsi_cfg->gsi_base)
3811  && (gsi <= gsi_cfg->gsi_end))
3812  return i;
3813  }
3814 
3815  printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
3816  return -1;
3817 }
3818 
3819 int mp_find_ioapic_pin(int ioapic, u32 gsi)
3820 {
3821  struct mp_ioapic_gsi *gsi_cfg;
3822 
3823  if (WARN_ON(ioapic == -1))
3824  return -1;
3825 
3826  gsi_cfg = mp_ioapic_gsi_routing(ioapic);
3827  if (WARN_ON(gsi > gsi_cfg->gsi_end))
3828  return -1;
3829 
3830  return gsi - gsi_cfg->gsi_base;
3831 }
3832 
3833 static __init int bad_ioapic(unsigned long address)
3834 {
3835  if (nr_ioapics >= MAX_IO_APICS) {
3836  pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
3837  MAX_IO_APICS, nr_ioapics);
3838  return 1;
3839  }
3840  if (!address) {
3841  pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n");
3842  return 1;
3843  }
3844  return 0;
3845 }
3846 
3847 static __init int bad_ioapic_register(int idx)
3848 {
3849  union IO_APIC_reg_00 reg_00;
3850  union IO_APIC_reg_01 reg_01;
3851  union IO_APIC_reg_02 reg_02;
3852 
3853  reg_00.raw = io_apic_read(idx, 0);
3854  reg_01.raw = io_apic_read(idx, 1);
3855  reg_02.raw = io_apic_read(idx, 2);
3856 
3857  if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
3858  pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
3859  mpc_ioapic_addr(idx));
3860  return 1;
3861  }
3862 
3863  return 0;
3864 }
3865 
3866 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
3867 {
3868  int idx = 0;
3869  int entries;
3870  struct mp_ioapic_gsi *gsi_cfg;
3871 
3872  if (bad_ioapic(address))
3873  return;
3874 
3875  idx = nr_ioapics;
3876 
3877  ioapics[idx].mp_config.type = MP_IOAPIC;
3878  ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
3879  ioapics[idx].mp_config.apicaddr = address;
3880 
3881  set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
3882 
3883  if (bad_ioapic_register(idx)) {
3884  clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
3885  return;
3886  }
3887 
3888  ioapics[idx].mp_config.apicid = io_apic_unique_id(id);
3889  ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
3890 
3891  /*
3892  * Build basic GSI lookup table to facilitate gsi->io_apic lookups
3893  * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
3894  */
3895  entries = io_apic_get_redir_entries(idx);
3896  gsi_cfg = mp_ioapic_gsi_routing(idx);
3897  gsi_cfg->gsi_base = gsi_base;
3898  gsi_cfg->gsi_end = gsi_base + entries - 1;
3899 
3900  /*
3901  * The number of IO-APIC IRQ registers (== #pins):
3902  */
3903  ioapics[idx].nr_registers = entries;
3904 
3905  if (gsi_cfg->gsi_end >= gsi_top)
3906  gsi_top = gsi_cfg->gsi_end + 1;
3907 
3908  pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
3909  idx, mpc_ioapic_id(idx),
3910  mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
3911  gsi_cfg->gsi_base, gsi_cfg->gsi_end);
3912 
3913  nr_ioapics++;
3914 }
3915 
3916 /* Enable IOAPIC early just for system timer */
3918 {
3919  struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
3920 
3921  printk(KERN_INFO "Early APIC setup for system timer0\n");
3922 #ifndef CONFIG_SMP
3923  physid_set_mask_of_physid(boot_cpu_physical_apicid,
3925 #endif
3926  setup_local_APIC();
3927 
3928  io_apic_setup_irq_pin(0, 0, &attr);
3930  "edge");
3931 }