14 #define MASK(n) ((1ULL<<(n))-1)
15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
18 ((addr >> 25) & 0x3ff))
19 #define MS_WIN(addr) (addr & 0x0ffc0000)
20 #define QLA82XX_PCI_MN_2M (0)
21 #define QLA82XX_PCI_MS_2M (0x80000)
22 #define QLA82XX_PCI_OCM0_2M (0xc0000)
23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
24 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
25 #define BLOCK_PROTECT_BITS 0x0F
28 #define CRB_BLK(off) ((off >> 20) & 0x3f)
29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30 #define CRB_WINDOW_2M (0x130060)
31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
32 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
35 #define CRB_INDIRECT_2M (0x1e0000UL)
37 #define MAX_CRB_XFORM 60
41 #define qla82xx_crb_addr_transform(name) \
42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
45 static void qla82xx_crb_addr_transform_setup(
void)
107 {{{1, 0x0100000, 0x0102000, 0x120000},
108 {1, 0x0110000, 0x0120000, 0x130000},
109 {1, 0x0120000, 0x0122000, 0x124000},
110 {1, 0x0130000, 0x0132000, 0x126000},
111 {1, 0x0140000, 0x0142000, 0x128000},
112 {1, 0x0150000, 0x0152000, 0x12a000},
113 {1, 0x0160000, 0x0170000, 0x110000},
114 {1, 0x0170000, 0x0172000, 0x12e000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {1, 0x01e0000, 0x01e0800, 0x122000},
122 {0, 0x0000000, 0x0000000, 0x000000} } } ,
123 {{{1, 0x0200000, 0x0210000, 0x180000} } },
125 {{{1, 0x0400000, 0x0401000, 0x169000} } },
126 {{{1, 0x0500000, 0x0510000, 0x140000} } },
127 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
128 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
129 {{{1, 0x0800000, 0x0802000, 0x170000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {1, 0x08f0000, 0x08f2000, 0x172000} } },
145 {{{1, 0x0900000, 0x0902000, 0x174000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {1, 0x09f0000, 0x09f2000, 0x176000} } },
161 {{{0, 0x0a00000, 0x0a02000, 0x178000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
177 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
193 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
194 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
195 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
196 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
197 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
198 {{{1, 0x1100000, 0x1101000, 0x160000} } },
199 {{{1, 0x1200000, 0x1201000, 0x161000} } },
200 {{{1, 0x1300000, 0x1301000, 0x162000} } },
201 {{{1, 0x1400000, 0x1401000, 0x163000} } },
202 {{{1, 0x1500000, 0x1501000, 0x165000} } },
203 {{{1, 0x1600000, 0x1601000, 0x166000} } },
210 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
211 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
212 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
214 {{{1, 0x2100000, 0x2102000, 0x120000},
215 {1, 0x2110000, 0x2120000, 0x130000},
216 {1, 0x2120000, 0x2122000, 0x124000},
217 {1, 0x2130000, 0x2132000, 0x126000},
218 {1, 0x2140000, 0x2142000, 0x128000},
219 {1, 0x2150000, 0x2152000, 0x12a000},
220 {1, 0x2160000, 0x2170000, 0x110000},
221 {1, 0x2170000, 0x2172000, 0x12e000},
222 {0, 0x0000000, 0x0000000, 0x000000},
223 {0, 0x0000000, 0x0000000, 0x000000},
224 {0, 0x0000000, 0x0000000, 0x000000},
225 {0, 0x0000000, 0x0000000, 0x000000},
226 {0, 0x0000000, 0x0000000, 0x000000},
227 {0, 0x0000000, 0x0000000, 0x000000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000} } },
230 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
236 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
237 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
238 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
239 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
240 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
241 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
242 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
243 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
244 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
245 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
246 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
247 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
249 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
250 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
251 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
252 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
253 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
254 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
257 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
258 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
259 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
370 "%s: Written crbwin (0x%x) "
371 "!= Read crbwin (0x%x), off=0x%lx.\n",
372 __func__, ha->
crb_win, win_read, *off);
377 static inline unsigned long
412 "%s: Warning: unm_nic_pci_set_crbwindow "
413 "called with an unknown address(%llx).\n",
448 #define CRB_WIN_LOCK_TIMEOUT 100000000
449 static int qla82xx_crb_win_lock(
struct qla_hw_data *ha)
469 unsigned long flags = 0;
472 rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
478 qla82xx_crb_win_lock(ha);
479 qla82xx_pci_set_crbwindow_2M(ha, &off);
494 unsigned long flags = 0;
498 rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
504 qla82xx_crb_win_lock(ha);
505 qla82xx_pci_set_crbwindow_2M(ha, &off);
516 #define IDC_LOCK_TIMEOUT 100000000
536 for (i = 0; i < 20; i++)
550 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
551 (((addr) <= (high)) && ((addr) >= (low)))
557 qla82xx_pci_mem_bound_check(
struct qla_hw_data *ha,
564 ((size != 1) && (size != 2) && (size != 4) && (size != 8)))
573 qla82xx_pci_set_window(
struct qla_hw_data *ha,
unsigned long long addr)
588 if ((win_read << 17) != window) {
590 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
591 __func__, window, win_read);
597 if ((addr & 0x00ff800) == 0xff800) {
599 "%s: QM access not handled.\n", __func__);
608 temp1 = ((window & 0x1FF) << 7) |
609 ((window & 0x0FFFE0000) >> 17);
610 if (win_read != temp1) {
612 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
613 __func__, temp1, win_read);
626 if (win_read != window) {
628 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
629 __func__, window, win_read);
637 if ((qla82xx_pci_set_window_warning_count++ < 8) ||
638 (qla82xx_pci_set_window_warning_count%64 == 0)) {
640 "%s: Warning:%s Unknown address range!.\n",
649 static int qla82xx_pci_is_same_window(
struct qla_hw_data *ha,
650 unsigned long long addr)
653 unsigned long long qdr_max;
676 static int qla82xx_pci_mem_read_direct(
struct qla_hw_data *ha,
685 unsigned long mem_page;
694 start = qla82xx_pci_set_window(ha, off);
695 if ((start == -1
UL) ||
696 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
699 "%s out of bound pci memory "
700 "access, offset is 0x%llx.\n",
711 if (mem_page != ((start + size - 1) & PAGE_MASK))
715 if (mem_ptr == 0
UL) {
748 qla82xx_pci_mem_write_direct(
struct qla_hw_data *ha,
749 u64 off,
void *data,
int size)
757 unsigned long mem_page;
766 start = qla82xx_pci_set_window(ha, off);
767 if ((start == -1
UL) ||
768 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
771 "%s out of bount memory "
772 "access, offset is 0x%llx.\n",
783 if (mem_page != ((start + size - 1) & PAGE_MASK))
817 #define MTU_FUDGE_FACTOR 100
819 qla82xx_decode_crb_addr(
unsigned long addr)
822 unsigned long base_addr,
offset, pci_base;
825 qla82xx_crb_addr_transform_setup();
828 base_addr = addr & 0xfff00000;
829 offset = addr & 0x000fffff;
832 if (crb_addr_xform[i] == base_addr) {
842 static long rom_max_timeout = 100;
843 static long qla82xx_rom_lock_timeout = 100;
855 if (timeout >= qla82xx_rom_lock_timeout)
880 if (timeout >= rom_max_timeout) {
882 "%s: Timeout reached waiting for rom busy.\n",
901 if (timeout >= rom_max_timeout) {
903 "%s: Timeout reached waiting for rom done.\n",
921 off_value = (off & 0x0000FFFF);
935 qla82xx_do_rom_fast_read(
struct qla_hw_data *ha,
int addr,
int *valp)
940 (addr & 0x0000FFFF), 0, 0);
946 qla82xx_rom_fast_read(
struct qla_hw_data *ha,
int addr,
int *valp)
951 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
956 if (loops >= 50000) {
958 "Failed to aquire SEM2 lock.\n");
961 ret = qla82xx_do_rom_fast_read(ha, addr, valp);
962 qla82xx_rom_unlock(ha);
971 qla82xx_wait_rom_busy(ha);
972 if (qla82xx_wait_rom_done(ha)) {
974 "Error waiting for rom done.\n");
982 qla82xx_flash_wait_write_finish(
struct qla_hw_data *ha)
991 while ((done != 0) && (ret == 0)) {
992 ret = qla82xx_read_status_reg(ha, &val);
997 if (timeout >= 50000) {
999 "Timeout reached waiting for write finish.\n");
1007 qla82xx_flash_set_write_enable(
struct qla_hw_data *ha)
1010 qla82xx_wait_rom_busy(ha);
1013 qla82xx_wait_rom_busy(ha);
1014 if (qla82xx_wait_rom_done(ha))
1016 if (qla82xx_read_status_reg(ha, &val) != 0)
1027 if (qla82xx_flash_set_write_enable(ha))
1031 if (qla82xx_wait_rom_done(ha)) {
1033 "Error waiting for rom done.\n");
1036 return qla82xx_flash_wait_write_finish(ha);
1040 qla82xx_write_disable_flash(
struct qla_hw_data *ha)
1044 if (qla82xx_wait_rom_done(ha)) {
1046 "Error waiting for rom done.\n");
1058 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1063 if (loops >= 50000) {
1065 "ROM lock failed.\n");
1078 ret = ql82xx_rom_lock_d(ha);
1081 "ROM lock failed.\n");
1085 if (qla82xx_flash_set_write_enable(ha))
1092 qla82xx_wait_rom_busy(ha);
1093 if (qla82xx_wait_rom_done(ha)) {
1095 "Error waiting for rom done.\n");
1100 ret = qla82xx_flash_wait_write_finish(ha);
1103 qla82xx_rom_unlock(ha);
1126 qla82xx_rom_lock(ha);
1178 qla82xx_rom_unlock(ha);
1185 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1186 qla82xx_rom_fast_read(ha, 4, &n) != 0) {
1188 "Error Reading crb_init area: n: %08x.\n", n);
1195 offset = n & 0xffff
U;
1196 n = (n >> 16) & 0xffffU;
1201 "Card flash not initialized:n=0x%x.\n", n);
1206 "%d CRB init values found in ROM.\n", n);
1211 "Unable to allocate memory.\n");
1215 for (i = 0; i <
n; i++) {
1216 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1217 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
1226 for (i = 0; i <
n; i++) {
1230 off = qla82xx_decode_crb_addr((
unsigned long)buf[i].addr) +
1263 "Unknow addr: 0x%08lx.\n", buf[i].addr);
1302 u64 off,
void *data,
int size)
1304 int i,
j, ret = 0, loop, sz[2], off0;
1305 int scale, shift_amount, startword;
1316 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1317 return qla82xx_pci_mem_write_direct(ha,
1322 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1323 sz[1] = size - sz[0];
1325 off8 = off & 0xfffffff0;
1326 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1329 startword = (off & 0xf)/8;
1331 for (i = 0; i < loop; i++) {
1333 (i << shift_amount), &word[i * scale], 8))
1354 word[startword] = tmpw;
1357 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1358 word[startword] |= tmpw << (off0 * 8);
1361 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1362 word[startword+1] |= tmpw >> (sz[0] * 8);
1365 for (i = 0; i < loop; i++) {
1366 temp = off8 + (i << shift_amount);
1370 temp = word[i * scale] & 0xffffffff;
1372 temp = (word[i * scale] >> 32) & 0xffffffff;
1374 temp = word[i*scale + 1] & 0xffffffff;
1377 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1392 if (j >= MAX_CTL_CHECK) {
1393 if (printk_ratelimit())
1395 "failed to write through agent.\n");
1405 qla82xx_fw_load_from_flash(
struct qla_hw_data *ha)
1415 for (i = 0; i <
size; i++) {
1416 if ((qla82xx_rom_fast_read(ha, flashaddr, (
int *)&low)) ||
1417 (qla82xx_rom_fast_read(ha, flashaddr + 4, (
int *)&high))) {
1420 data = ((
u64)high << 32) |
low ;
1421 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1425 if (i % 0x1000 == 0)
1438 u64 off,
void *data,
int size)
1440 int i, j = 0,
k,
start,
end, loop, sz[2], off0[2];
1453 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1454 return qla82xx_pci_mem_read_direct(ha,
1458 off8 = off & 0xfffffff0;
1459 off0[0] = off & 0xf;
1460 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1462 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1464 sz[1] = size - sz[0];
1466 for (i = 0; i < loop; i++) {
1467 temp = off8 + (i << shift_amount);
1482 if (j >= MAX_CTL_CHECK) {
1483 if (printk_ratelimit())
1485 "failed to read through agent.\n");
1489 start = off0[
i] >> 2;
1490 end = (off0[
i] + sz[
i] - 1) >> 2;
1491 for (
k = start;
k <=
end;
k++) {
1494 word[
i] |= ((
uint64_t)temp << (32 * (
k & 1)));
1498 if (j >= MAX_CTL_CHECK)
1501 if ((off0[0] & 7) == 0) {
1504 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1505 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1527 qla82xx_get_table_desc(
const u8 *unirom,
int section)
1536 for (i = 0; i <
entries; i++) {
1541 if (tab_type == section)
1550 u32 section,
u32 idx_offset)
1552 const u8 *unirom = ha->
hablob->fw->data;
1557 tab_desc = qla82xx_get_table_desc(unirom, section);
1574 uri_desc = qla82xx_get_data_desc(ha,
1617 unsigned long val = 0;
1640 "Failed to reserver selected regions.\n");
1641 goto iospace_error_exit;
1647 "Region #0 not an MMIO resource, aborting.\n");
1648 goto iospace_error_exit;
1656 "Cannot remap pcibase MMIO, aborting.\n");
1658 goto iospace_error_exit;
1663 0xbc000 + (ha->
pdev->devfn << 11));
1668 (ha->
pdev->devfn << 12)), 4);
1671 "Cannot remap MMIO, aborting.\n");
1673 goto iospace_error_exit;
1680 (ha->
pdev->devfn * 8);
1690 "nx_pci_base=%p iobase=%p "
1691 "max_req_queues=%d msix_count=%d.\n",
1695 "nx_pci_base=%p iobase=%p "
1696 "max_req_queues=%d msix_count=%d.\n",
1725 "Chip revision:%d.\n",
1740 ha->
isp_ops->disable_intrs(ha);
1770 vha->
flags.online = 0;
1772 ha->
isp_ops->disable_intrs(ha);
1784 ptr64 = (
u64 *)qla82xx_get_bootld_offset(ha);
1787 for (i = 0; i <
size; i++) {
1789 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1795 size = (
__force u32)qla82xx_get_fw_size(ha) / 8;
1796 ptr64 = (
u64 *)qla82xx_get_fw_offs(ha);
1798 for (i = 0; i <
size; i++) {
1801 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1822 qla82xx_set_product_offset(
struct qla_hw_data *ha)
1834 ptab_desc = qla82xx_get_table_desc(unirom,
1841 for (i = 0; i <
entries; i++) {
1846 file_chiprev =
cpu_to_le32(*((
int *)&unirom[offset] +
1849 flagbit = mn_present ? 1 : 2;
1851 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
1870 if (qla82xx_set_product_offset(ha))
1882 if (fw->
size < min_size)
1888 qla82xx_check_cmdpeg_state(
struct qla_hw_data *ha)
1909 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n",
1914 }
while (--retries);
1917 "Cmd Peg initialization failed: 0x%x.\n", val);
1927 qla82xx_check_rcvpeg_state(
struct qla_hw_data *ha)
1948 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n",
1953 }
while (--retries);
1956 "Rcv Peg initializatin failed: 0x%x.\n", val);
1979 QLA82XX_LEGACY_INTR_CONFIG;
1996 ha->
flags.mbox_int = 1;
2006 "MBX pointer ERROR.\n");
2027 unsigned long flags;
2032 rsp = (
struct rsp_que *) dev_id;
2035 "%s: NULL response queue pointer.\n", __func__);
2040 if (!ha->
flags.msi_enabled) {
2060 vha = pci_get_drvdata(ha->
pdev);
2061 for (iter = 1; iter--; ) {
2066 switch (stat & 0xff) {
2071 qla82xx_mbx_completion(vha,
MSW(stat));
2086 "Unrecognized interrupt type (%d).\n",
2093 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2094 if (!ha->
flags.msi_enabled)
2097 #ifdef QL_DEBUG_LEVEL_17
2098 if (!irq && ha->
flags.eeh_busy)
2100 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n",
2120 unsigned long flags;
2124 rsp = (
struct rsp_que *) dev_id;
2127 "%s(): NULL response queue pointer.\n", __func__);
2135 vha = pci_get_drvdata(ha->
pdev);
2140 switch (stat & 0xff) {
2145 qla82xx_mbx_completion(vha,
MSW(stat));
2160 "Unrecognized interrupt type (%d).\n",
2168 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2170 #ifdef QL_DEBUG_LEVEL_17
2171 if (!irq && ha->
flags.eeh_busy)
2173 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n",
2192 unsigned long flags;
2194 rsp = (
struct rsp_que *) dev_id;
2197 "%s(): NULL response queue pointer.\n", __func__);
2204 vha = pci_get_drvdata(ha->
pdev);
2207 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2221 unsigned long flags;
2223 rsp = (
struct rsp_que *) dev_id;
2226 "%s(): NULL response queue pointer.\n", __func__);
2233 vha = pci_get_drvdata(ha->
pdev);
2237 switch (stat & 0xff) {
2242 qla82xx_mbx_completion(vha,
MSW(stat));
2257 "Unrecognized interrupt type (%d).\n",
2263 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2271 spin_lock_irq(&ha->hardware_lock);
2273 spin_unlock_irq(&ha->hardware_lock);
2282 spin_lock_irq(&ha->hardware_lock);
2284 spin_unlock_irq(&ha->hardware_lock);
2298 nx_legacy_intr = &legacy_intr[ha->
portnum];
2322 "qla2xxx driver IDC version %d is not compatible "
2323 "with IDC version %d of the other drivers\n",
2337 if (drv_active == 0xffffffff) {
2362 if (ha->
flags.nic_core_reset_owner)
2380 if (drv_state == 0xffffffff) {
2386 "drv_state = 0x%08x.\n", drv_state);
2430 "Error during CRB initialization.\n");
2437 rst &= ~((1 << 28) | (1 << 24));
2449 "Attempting to load firmware from flash.\n");
2451 if (qla82xx_fw_load_from_flash(ha) ==
QLA_SUCCESS) {
2453 "Firmware loaded successfully from flash.\n");
2457 "Firmware load from flash failed.\n");
2462 "Attempting to load firmware from blob.\n");
2468 "Firmware image not present.\n");
2469 goto fw_load_failed;
2479 "No valid firmware image found.\n");
2484 if (qla82xx_fw_load_from_blob(ha) ==
QLA_SUCCESS) {
2486 "Firmware loaded successfully from binary blob.\n");
2490 "Firmware load failed for binary blob.\n");
2493 goto fw_load_failed;
2522 "Error trying to start fw.\n");
2527 if (qla82xx_check_cmdpeg_state(ha) !=
QLA_SUCCESS) {
2529 "Error during card handshake.\n");
2538 return qla82xx_check_rcvpeg_state(ha);
2550 for (i = 0; i < length/4; i++, faddr += 4) {
2551 if (qla82xx_rom_fast_read(ha, faddr, &val)) {
2553 "Do ROM fast read failed.\n");
2569 ret = ql82xx_rom_lock_d(ha);
2572 "ROM Lock failed.\n");
2576 ret = qla82xx_read_status_reg(ha, &val);
2578 goto done_unprotect;
2581 ret = qla82xx_write_status_reg(ha, val);
2584 qla82xx_write_status_reg(ha, val);
2587 if (qla82xx_write_disable_flash(ha) != 0)
2589 "Write disable failed.\n");
2592 qla82xx_rom_unlock(ha);
2603 ret = ql82xx_rom_lock_d(ha);
2606 "ROM Lock failed.\n");
2610 ret = qla82xx_read_status_reg(ha, &val);
2616 ret = qla82xx_write_status_reg(ha, val);
2619 "Write status register failed.\n");
2621 if (qla82xx_write_disable_flash(ha) != 0)
2623 "Write disable failed.\n");
2625 qla82xx_rom_unlock(ha);
2630 qla82xx_erase_sector(
struct qla_hw_data *ha,
int addr)
2635 ret = ql82xx_rom_lock_d(ha);
2638 "ROM Lock failed.\n");
2642 qla82xx_flash_set_write_enable(ha);
2647 if (qla82xx_wait_rom_done(ha)) {
2649 "Error waiting for rom done.\n");
2653 ret = qla82xx_flash_wait_write_finish(ha);
2655 qla82xx_rom_unlock(ha);
2667 qla82xx_read_flash_data(vha, (
uint32_t *)buf, offset, length);
2680 void *optrom =
NULL;
2687 if (page_mode && !(faddr & 0xfff) &&
2693 "Unable to allocate memory "
2694 "for optrom burst write (%x KB).\n",
2700 sec_mask = ~rest_addr;
2702 ret = qla82xx_unprotect_flash(ha);
2705 "Unable to unprotect flash for update.\n");
2709 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
2711 if ((faddr & rest_addr) == 0) {
2713 ret = qla82xx_erase_sector(ha, faddr);
2716 "Unable to erase sector: address=%x.\n",
2732 "Unable to burst-write optrom segment "
2733 "(%x/%x/%llx).\n", ret,
2735 (
unsigned long long)optrom_dma);
2737 "Reverting to slow-write.\n");
2750 ret = qla82xx_write_flash_dword(ha, faddr,
2754 "Unable to program flash address=%x data=%x.\n",
2760 ret = qla82xx_protect_flash(ha);
2763 "Unable to protect flash after update.\n");
2779 rval = qla82xx_write_flash_data(vha, (
uint32_t *)buf, offset,
2808 dbval = 0x04 | (ha->
portnum << 5);
2810 dbval = dbval | (req->
id << 8) | (req->
ring_index << 16);
2828 if (qla82xx_rom_lock(ha))
2831 "Resetting rom_lock.\n");
2838 qla82xx_rom_unlock(ha);
2859 int need_reset = 0, peg_stuck = 1;
2861 need_reset = qla82xx_need_reset(ha);
2865 for (i = 0; i < 10; i++) {
2874 if (count != old_count)
2882 goto dev_initialize;
2888 goto dev_initialize;
2899 "HW State: INITIALIZING.\n");
2908 "HW State: FAILED.\n");
2916 "HW State: READY.\n");
2937 unsigned long reset_timeout;
2939 if (vha->
flags.online) {
2945 qla82xx_set_qsnt_ready(ha);
2953 drv_active = drv_active << 0x01;
2955 while (drv_state != drv_active) {
2962 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d "
2964 drv_active, drv_state);
2968 "HW State: DEV_READY.\n");
2983 drv_active = drv_active << 0x01;
2989 "HW State: DEV_QUIESCENT.\n");
3015 }
while (dev_state == curr_state);
3027 "Disabling the board.\n");
3038 vha->
flags.online = 0;
3039 vha->
flags.init_done = 0;
3058 unsigned long reset_timeout;
3062 if (vha->
flags.online) {
3066 ha->
isp_ops->nvram_config(vha);
3071 if (!ha->
flags.nic_core_reset_owner) {
3073 "reset_acknowledged by 0x%x\n", ha->
portnum);
3074 qla82xx_set_rst_ready(ha);
3077 drv_active &= active_mask;
3079 "active_mask: 0x%08x\n", active_mask);
3090 "drv_state: 0x%08x, drv_active: 0x%08x, "
3091 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3092 drv_state, drv_active, dev_state, active_mask);
3094 while (drv_state != drv_active &&
3098 "Reset timeout.\n");
3106 if (ha->
flags.nic_core_reset_owner)
3107 drv_active &= active_mask;
3112 "drv_state: 0x%08x, drv_active: 0x%08x, "
3113 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3114 drv_state, drv_active, dev_state, active_mask);
3117 "Device state is 0x%x = %s.\n",
3125 "HW State: COLD/RE-INIT.\n");
3127 qla82xx_set_rst_ready(ha);
3131 "Minidump not collected.\n");
3134 "Minidump disabled.\n");
3159 "Firmware version differs "
3160 "Previous version: %d:%d:%d - "
3161 "New version: %d:%d:%d\n",
3162 fw_major_version, fw_minor_version,
3163 fw_subminor_version,
3174 "Firmware dump available to retrieve\n");
3189 if (fw_heartbeat_counter == 0xffffffff) {
3191 "FW heartbeat counter is 0xffffffff, "
3192 "returning status=%d.\n", status);
3207 "Returning status=%d.\n", status);
3228 unsigned long dev_init_timeout;
3233 if (!vha->
flags.init_done) {
3241 "Device state is 0x%x = %s.\n",
3252 "Device init failed.\n");
3257 if (old_dev_state != dev_state) {
3261 if (loopcount < 5) {
3263 "Device state is 0x%x = %s.\n",
3269 switch (dev_state) {
3271 ha->
flags.nic_core_reset_owner = 0;
3274 rval = qla82xx_device_bootstrap(vha);
3283 qla82xx_need_reset_handler(vha);
3293 qla82xx_need_qsnt_handler(vha);
3302 if (ha->
flags.quiesce_owner)
3341 "Device temperature %d degrees C exceeds "
3342 " maximum allowed. Hardware has been shut down.\n",
3347 "Device temperature %d degrees C exceeds "
3348 "operating range. Immediate action needed.\n",
3358 if (ha->
flags.mbox_busy) {
3359 ha->
flags.mbox_int = 1;
3360 ha->
flags.mbox_busy = 0;
3362 "Doing premature completion of mbx command.\n");
3374 if (!ha->
flags.nic_core_reset_hdlr_active) {
3376 if (qla82xx_check_temp(vha)) {
3378 ha->
flags.isp82xx_fw_hung = 1;
3383 "Adapter reset needed.\n");
3388 "Quiescent needed.\n");
3392 vha->
flags.online == 1) {
3394 "Adapter state is failed. Offlining.\n");
3396 ha->
flags.isp82xx_fw_hung = 1;
3401 "disabling pause transmit on port 0 & 1.\n");
3407 "dumping hw/fw registers:.\n "
3408 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n "
3409 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n "
3410 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n "
3411 " PEG_NET_4_PC: 0x%x.\n", halt_status,
3423 if (((halt_status & 0x1fffff00) >> 8) == 0x67)
3425 "Firmware aborted with "
3426 "error code 0x00006700. Device is "
3433 "Detect abort needed.\n");
3437 ha->
flags.isp82xx_fw_hung = 1;
3461 "HW State: NEED RESET\n");
3464 ha->
flags.nic_core_reset_owner = 1;
3466 "reset_owner is 0x%x\n", ha->
portnum);
3469 "Device state is 0x%x = %s.\n",
3492 "Device in failed state, exiting.\n");
3495 ha->
flags.nic_core_reset_hdlr_active = 1;
3504 qla82xx_clear_rst_ready(ha);
3508 ha->
flags.isp82xx_fw_hung = 0;
3509 ha->
flags.nic_core_reset_hdlr_active = 0;
3514 vha->
flags.online = 1;
3518 "ISP error recover failed - board "
3524 ha->
isp_ops->reset_adapter(vha);
3525 vha->
flags.online = 0;
3532 "ISP abort - retry remaining %d.\n",
3539 "ISP error recovery - retrying (%d) more times.\n",
3565 if (vha->
flags.online) {
3596 unsigned long wait_reset;
3613 "%s: status=%d.\n", __func__, status);
3622 unsigned long flags;
3629 if (!ha->
flags.isp82xx_fw_hung) {
3630 for (i = 0; i < 2; i++) {
3633 ha->
flags.isp82xx_fw_hung = 1;
3640 "Entered %s fw_hung=%d.\n",
3641 __func__, ha->
flags.isp82xx_fw_hung);
3644 if (!ha->
flags.isp82xx_fw_hung) {
3657 if (!sp->
u.
scmd.ctx ||
3659 spin_unlock_irqrestore(
3660 &ha->hardware_lock, flags);
3661 if (ha->
isp_ops->abort_command(sp)) {
3664 "mbx abort failed.\n");
3668 "mbx abort success.\n");
3675 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3682 "pending commands.\n");
3696 unsigned long wtime;
3703 crb_addr = crb_entry->
addr;
3705 for (i = 0; i < crb_entry->
op_count; i++) {
3706 opcode = crb_entry->
crb_ctrl.opcode;
3710 opcode &= ~QLA82XX_DBG_OPCODE_WR;
3716 opcode &= ~QLA82XX_DBG_OPCODE_RW;
3721 read_value &= crb_entry->
value_2;
3722 opcode &= ~QLA82XX_DBG_OPCODE_AND;
3724 read_value |= crb_entry->
value_3;
3725 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3732 read_value |= crb_entry->
value_3;
3734 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3738 poll_time = crb_entry->
crb_strd.poll_timeout;
3743 if ((read_value & crb_entry->
value_2)
3754 opcode &= ~QLA82XX_DBG_OPCODE_POLL;
3758 if (crb_entry->
crb_strd.state_index_a) {
3759 index = crb_entry->
crb_strd.state_index_a;
3765 index = crb_entry->
crb_ctrl.state_index_v;
3767 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
3771 if (crb_entry->
crb_strd.state_index_a) {
3772 index = crb_entry->
crb_strd.state_index_a;
3777 if (crb_entry->
crb_ctrl.state_index_v) {
3778 index = crb_entry->
crb_ctrl.state_index_v;
3782 read_value = crb_entry->
value_1;
3785 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
3789 index = crb_entry->
crb_ctrl.state_index_v;
3791 read_value <<= crb_entry->
crb_ctrl.shl;
3792 read_value >>= crb_entry->
crb_ctrl.shr;
3794 read_value &= crb_entry->
value_2;
3795 read_value |= crb_entry->
value_3;
3796 read_value += crb_entry->
value_1;
3798 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
3800 crb_addr += crb_entry->
crb_strd.addr_stride;
3819 for (i = 0; i < loop_cnt; i++) {
3843 for (i = 0; i < loop_cnt; i++) {
3848 s_value += s_stride;
3863 r_addr = crb_hdr->
addr;
3864 r_stride = crb_hdr->
crb_strd.addr_stride;
3867 for (i = 0; i < loop_cnt; i++) {
3882 uint32_t i,
k, loop_count, t_value, r_cnt, r_value;
3883 unsigned long p_wait, w_time, p_mask;
3893 c_value_w = cache_hdr->
cache_ctrl.write_value;
3896 t_value = cache_hdr->
addr_ctrl.init_tag_value;
3897 r_cnt = cache_hdr->
read_ctrl.read_addr_cnt;
3901 for (i = 0; i < loop_count; i++) {
3910 if ((c_value_r & p_mask) == 0)
3915 "c_value_r: 0x%x, poll_mask: 0x%lx, "
3917 c_value_r, p_mask, w_time);
3924 for (k = 0; k < r_cnt; k++) {
3927 addr += cache_hdr->
read_ctrl.read_addr_stride;
3929 t_value += cache_hdr->
addr_ctrl.tag_value_stride;
3941 uint32_t i,
k, loop_count, t_value, r_cnt, r_value;
3950 c_value_w = cache_hdr->
cache_ctrl.write_value;
3953 t_value = cache_hdr->
addr_ctrl.init_tag_value;
3954 r_cnt = cache_hdr->
read_ctrl.read_addr_cnt;
3956 for (i = 0; i < loop_count; i++) {
3960 for (k = 0; k < r_cnt; k++) {
3963 addr += cache_hdr->
read_ctrl.read_addr_stride;
3965 t_value += cache_hdr->
addr_ctrl.tag_value_stride;
3983 r_cnt = q_hdr->
rd_strd.read_addr_cnt;
3984 r_stride = q_hdr->
rd_strd.read_addr_stride;
3987 for (i = 0; i < loop_cnt; i++) {
3990 for (k = 0; k < r_cnt; k++) {
3995 qid += q_hdr->
q_strd.queue_id_stride;
4014 for (i = 0; i < loop_cnt; i++) {
4016 (r_addr & 0xFFFF0000), 1);
4019 (r_addr & 0x0000FFFF), 0, 0);
4034 unsigned long flags;
4044 "Read addr 0x%x not 16 bytes aligned\n", r_addr);
4050 "Read data[0x%x] not multiple of 16 bytes\n",
4056 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
4060 for (i = 0; i < loop_cnt; i++) {
4076 if (j >= MAX_CTL_CHECK) {
4078 "failed to read through agent\n");
4083 for (j = 0; j < 4; j++) {
4085 MD_MIU_TEST_AGT_RDDATA[j], 0, 0);
4105 while (chksum >> 32)
4106 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32);
4116 "Skipping entry[%d]: "
4117 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4119 entry_hdr->
d_ctrl.entry_capture_mask);
4126 int no_entry_hdr = 0;
4130 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0;
4138 "Firmware has been previously dumped (%p) "
4139 "-- ignoring request.\n", ha->
fw_dump);
4147 "Memory not allocated for minidump capture\n");
4151 if (ha->
flags.isp82xx_no_md_cap) {
4153 "Forced reset from application, "
4154 "ignore minidump capture\n");
4155 ha->
flags.isp82xx_no_md_cap = 0;
4159 if (qla82xx_validate_template_chksum(vha)) {
4161 "Template checksum validation error\n");
4167 "No of entry headers in Template: 0x%x\n", no_entry_hdr);
4175 if ((f_capture_mask & 0x3) != 0x3) {
4177 "Minimum required capture mask[0x%x] level not set\n",
4191 "Total minidump data_size 0x%x to be captured\n", total_data_size);
4196 "Bad template header entry type: 0x%x obtained\n",
4205 for (i = 0; i < no_entry_hdr; i++) {
4207 if (data_collected > total_data_size) {
4209 "More MiniDump data collected: [0x%x]\n",
4214 if (!(entry_hdr->
d_ctrl.entry_capture_mask &
4216 entry_hdr->
d_ctrl.driver_flags |=
4219 "Skipping entry[%d]: "
4220 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4222 entry_hdr->
d_ctrl.entry_capture_mask);
4223 goto skip_nxt_entry;
4227 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n"
4228 "entry_type: 0x%x, captrue_mask: 0x%x\n",
4229 __func__, i, data_ptr, entry_hdr,
4231 entry_hdr->
d_ctrl.entry_capture_mask);
4234 "Data collected: [0x%x], Dump size left:[0x%x]\n",
4241 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4244 rval = qla82xx_minidump_process_control(vha,
4245 entry_hdr, &data_ptr);
4247 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4252 qla82xx_minidump_process_rdcrb(vha,
4253 entry_hdr, &data_ptr);
4256 rval = qla82xx_minidump_process_rdmem(vha,
4257 entry_hdr, &data_ptr);
4259 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4265 qla82xx_minidump_process_rdrom(vha,
4266 entry_hdr, &data_ptr);
4272 rval = qla82xx_minidump_process_l2tag(vha,
4273 entry_hdr, &data_ptr);
4275 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4281 qla82xx_minidump_process_l1cache(vha,
4282 entry_hdr, &data_ptr);
4285 qla82xx_minidump_process_rdocm(vha,
4286 entry_hdr, &data_ptr);
4289 qla82xx_minidump_process_rdmux(vha,
4290 entry_hdr, &data_ptr);
4293 qla82xx_minidump_process_queue(vha,
4294 entry_hdr, &data_ptr);
4298 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4303 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr);
4305 data_collected = (
uint8_t *)data_ptr -
4312 if (data_collected != total_data_size) {
4314 "MiniDump data mismatch: Data collected: [0x%x],"
4315 "total_data_size:[0x%x]\n",
4316 data_collected, total_data_size);
4321 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
4339 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) {
4342 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n",
4353 "Firmware dump previously allocated.\n");
4360 "Unable to allocate memory for Minidump size "
4375 "Free MiniDump template: %p, size (%d KB)\n",
4385 "Free MiniDump memory: %p, size (%d KB)\n",
4403 "MiniDump Template size obtained (%d KB)\n",
4410 "MiniDump Template obtained\n");
4416 "MiniDump memory allocated (%d KB)\n",
4420 "Free MiniDump template: %p, size: (%d KB)\n",
4444 "mbx set led config failed in %s\n", __func__);
4464 "mbx set led config failed in %s\n", __func__);