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rt61pci.c
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1 /*
2  Copyright (C) 2004 - 2009 Ivo van Doorn <[email protected]>
3  <http://rt2x00.serialmonkey.com>
4 
5  This program is free software; you can redistribute it and/or modify
6  it under the terms of the GNU General Public License as published by
7  the Free Software Foundation; either version 2 of the License, or
8  (at your option) any later version.
9 
10  This program is distributed in the hope that it will be useful,
11  but WITHOUT ANY WARRANTY; without even the implied warranty of
12  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13  GNU General Public License for more details.
14 
15  You should have received a copy of the GNU General Public License
16  along with this program; if not, write to the
17  Free Software Foundation, Inc.,
18  59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20 
21 /*
22  Module: rt61pci
23  Abstract: rt61pci device specific routines.
24  Supported chipsets: RT2561, RT2561s, RT2661.
25  */
26 
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/slab.h>
34 #include <linux/pci.h>
35 #include <linux/eeprom_93cx6.h>
36 
37 #include "rt2x00.h"
38 #include "rt2x00pci.h"
39 #include "rt61pci.h"
40 
41 /*
42  * Allow hardware encryption to be disabled.
43  */
44 static bool modparam_nohwcrypt = false;
45 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
47 
48 /*
49  * Register access.
50  * BBP and RF register require indirect register access,
51  * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
52  * These indirect registers work with busy bits,
53  * and we will try maximal REGISTER_BUSY_COUNT times to access
54  * the register while taking a REGISTER_BUSY_DELAY us delay
55  * between each attempt. When the busy bit is still set at that time,
56  * the access attempt is considered to have failed,
57  * and we will print an error.
58  */
59 #define WAIT_FOR_BBP(__dev, __reg) \
60  rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
61 #define WAIT_FOR_RF(__dev, __reg) \
62  rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
63 #define WAIT_FOR_MCU(__dev, __reg) \
64  rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
65  H2M_MAILBOX_CSR_OWNER, (__reg))
66 
67 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68  const unsigned int word, const u8 value)
69 {
70  u32 reg;
71 
72  mutex_lock(&rt2x00dev->csr_mutex);
73 
74  /*
75  * Wait until the BBP becomes available, afterwards we
76  * can safely write the new data into the register.
77  */
78  if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
79  reg = 0;
80  rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
84 
85  rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
86  }
87 
88  mutex_unlock(&rt2x00dev->csr_mutex);
89 }
90 
91 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
92  const unsigned int word, u8 *value)
93 {
94  u32 reg;
95 
96  mutex_lock(&rt2x00dev->csr_mutex);
97 
98  /*
99  * Wait until the BBP becomes available, afterwards we
100  * can safely write the read request into the register.
101  * After the data has been written, we wait until hardware
102  * returns the correct value, if at any time the register
103  * doesn't become available in time, reg will be 0xffffffff
104  * which means we return 0xff to the caller.
105  */
106  if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
107  reg = 0;
108  rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
111 
112  rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
113 
114  WAIT_FOR_BBP(rt2x00dev, &reg);
115  }
116 
117  *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
118 
119  mutex_unlock(&rt2x00dev->csr_mutex);
120 }
121 
122 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
123  const unsigned int word, const u32 value)
124 {
125  u32 reg;
126 
127  mutex_lock(&rt2x00dev->csr_mutex);
128 
129  /*
130  * Wait until the RF becomes available, afterwards we
131  * can safely write the new data into the register.
132  */
133  if (WAIT_FOR_RF(rt2x00dev, &reg)) {
134  reg = 0;
135  rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
139 
140  rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
141  rt2x00_rf_write(rt2x00dev, word, value);
142  }
143 
144  mutex_unlock(&rt2x00dev->csr_mutex);
145 }
146 
147 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
148  const u8 command, const u8 token,
149  const u8 arg0, const u8 arg1)
150 {
151  u32 reg;
152 
153  mutex_lock(&rt2x00dev->csr_mutex);
154 
155  /*
156  * Wait until the MCU becomes available, afterwards we
157  * can safely write the new data into the register.
158  */
159  if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
164  rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
165 
166  rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
169  rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
170  }
171 
172  mutex_unlock(&rt2x00dev->csr_mutex);
173 
174 }
175 
176 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
177 {
178  struct rt2x00_dev *rt2x00dev = eeprom->data;
179  u32 reg;
180 
181  rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
182 
185  eeprom->reg_data_clock =
187  eeprom->reg_chip_select =
189 }
190 
191 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
192 {
193  struct rt2x00_dev *rt2x00dev = eeprom->data;
194  u32 reg = 0;
195 
199  !!eeprom->reg_data_clock);
201  !!eeprom->reg_chip_select);
202 
203  rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
204 }
205 
206 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
207 static const struct rt2x00debug rt61pci_rt2x00debug = {
208  .owner = THIS_MODULE,
209  .csr = {
210  .read = rt2x00pci_register_read,
211  .write = rt2x00pci_register_write,
212  .flags = RT2X00DEBUGFS_OFFSET,
213  .word_base = CSR_REG_BASE,
214  .word_size = sizeof(u32),
215  .word_count = CSR_REG_SIZE / sizeof(u32),
216  },
217  .eeprom = {
218  .read = rt2x00_eeprom_read,
219  .write = rt2x00_eeprom_write,
220  .word_base = EEPROM_BASE,
221  .word_size = sizeof(u16),
222  .word_count = EEPROM_SIZE / sizeof(u16),
223  },
224  .bbp = {
225  .read = rt61pci_bbp_read,
226  .write = rt61pci_bbp_write,
227  .word_base = BBP_BASE,
228  .word_size = sizeof(u8),
229  .word_count = BBP_SIZE / sizeof(u8),
230  },
231  .rf = {
232  .read = rt2x00_rf_read,
233  .write = rt61pci_rf_write,
234  .word_base = RF_BASE,
235  .word_size = sizeof(u32),
236  .word_count = RF_SIZE / sizeof(u32),
237  },
238 };
239 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
240 
241 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
242 {
243  u32 reg;
244 
245  rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
246  return rt2x00_get_field32(reg, MAC_CSR13_VAL5);
247 }
248 
249 #ifdef CONFIG_RT2X00_LIB_LEDS
250 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
252 {
253  struct rt2x00_led *led =
254  container_of(led_cdev, struct rt2x00_led, led_dev);
255  unsigned int enabled = brightness != LED_OFF;
256  unsigned int a_mode =
257  (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
258  unsigned int bg_mode =
259  (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
260 
261  if (led->type == LED_TYPE_RADIO) {
262  rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
263  MCU_LEDCS_RADIO_STATUS, enabled);
264 
265  rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
266  (led->rt2x00dev->led_mcu_reg & 0xff),
267  ((led->rt2x00dev->led_mcu_reg >> 8)));
268  } else if (led->type == LED_TYPE_ASSOC) {
269  rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
270  MCU_LEDCS_LINK_BG_STATUS, bg_mode);
271  rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
272  MCU_LEDCS_LINK_A_STATUS, a_mode);
273 
274  rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
275  (led->rt2x00dev->led_mcu_reg & 0xff),
276  ((led->rt2x00dev->led_mcu_reg >> 8)));
277  } else if (led->type == LED_TYPE_QUALITY) {
278  /*
279  * The brightness is divided into 6 levels (0 - 5),
280  * this means we need to convert the brightness
281  * argument into the matching level within that range.
282  */
283  rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
284  brightness / (LED_FULL / 6), 0);
285  }
286 }
287 
288 static int rt61pci_blink_set(struct led_classdev *led_cdev,
289  unsigned long *delay_on,
290  unsigned long *delay_off)
291 {
292  struct rt2x00_led *led =
293  container_of(led_cdev, struct rt2x00_led, led_dev);
294  u32 reg;
295 
296  rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
297  rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
298  rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
299  rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
300 
301  return 0;
302 }
303 
304 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
305  struct rt2x00_led *led,
306  enum led_type type)
307 {
308  led->rt2x00dev = rt2x00dev;
309  led->type = type;
310  led->led_dev.brightness_set = rt61pci_brightness_set;
311  led->led_dev.blink_set = rt61pci_blink_set;
312  led->flags = LED_INITIALIZED;
313 }
314 #endif /* CONFIG_RT2X00_LIB_LEDS */
315 
316 /*
317  * Configuration handlers.
318  */
319 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
320  struct rt2x00lib_crypto *crypto,
321  struct ieee80211_key_conf *key)
322 {
323  struct hw_key_entry key_entry;
324  struct rt2x00_field32 field;
325  u32 mask;
326  u32 reg;
327 
328  if (crypto->cmd == SET_KEY) {
329  /*
330  * rt2x00lib can't determine the correct free
331  * key_idx for shared keys. We have 1 register
332  * with key valid bits. The goal is simple, read
333  * the register, if that is full we have no slots
334  * left.
335  * Note that each BSS is allowed to have up to 4
336  * shared keys, so put a mask over the allowed
337  * entries.
338  */
339  mask = (0xf << crypto->bssidx);
340 
341  rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
342  reg &= mask;
343 
344  if (reg && reg == mask)
345  return -ENOSPC;
346 
347  key->hw_key_idx += reg ? ffz(reg) : 0;
348 
349  /*
350  * Upload key to hardware
351  */
352  memcpy(key_entry.key, crypto->key,
353  sizeof(key_entry.key));
354  memcpy(key_entry.tx_mic, crypto->tx_mic,
355  sizeof(key_entry.tx_mic));
356  memcpy(key_entry.rx_mic, crypto->rx_mic,
357  sizeof(key_entry.rx_mic));
358 
359  reg = SHARED_KEY_ENTRY(key->hw_key_idx);
360  rt2x00pci_register_multiwrite(rt2x00dev, reg,
361  &key_entry, sizeof(key_entry));
362 
363  /*
364  * The cipher types are stored over 2 registers.
365  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
366  * bssidx 1 and 2 keys are stored in SEC_CSR5.
367  * Using the correct defines correctly will cause overhead,
368  * so just calculate the correct offset.
369  */
370  if (key->hw_key_idx < 8) {
371  field.bit_offset = (3 * key->hw_key_idx);
372  field.bit_mask = 0x7 << field.bit_offset;
373 
374  rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
375  rt2x00_set_field32(&reg, field, crypto->cipher);
376  rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
377  } else {
378  field.bit_offset = (3 * (key->hw_key_idx - 8));
379  field.bit_mask = 0x7 << field.bit_offset;
380 
381  rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
382  rt2x00_set_field32(&reg, field, crypto->cipher);
383  rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
384  }
385 
386  /*
387  * The driver does not support the IV/EIV generation
388  * in hardware. However it doesn't support the IV/EIV
389  * inside the ieee80211 frame either, but requires it
390  * to be provided separately for the descriptor.
391  * rt2x00lib will cut the IV/EIV data out of all frames
392  * given to us by mac80211, but we must tell mac80211
393  * to generate the IV/EIV data.
394  */
396  }
397 
398  /*
399  * SEC_CSR0 contains only single-bit fields to indicate
400  * a particular key is valid. Because using the FIELD32()
401  * defines directly will cause a lot of overhead, we use
402  * a calculation to determine the correct bit directly.
403  */
404  mask = 1 << key->hw_key_idx;
405 
406  rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
407  if (crypto->cmd == SET_KEY)
408  reg |= mask;
409  else if (crypto->cmd == DISABLE_KEY)
410  reg &= ~mask;
411  rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
412 
413  return 0;
414 }
415 
416 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
417  struct rt2x00lib_crypto *crypto,
418  struct ieee80211_key_conf *key)
419 {
420  struct hw_pairwise_ta_entry addr_entry;
421  struct hw_key_entry key_entry;
422  u32 mask;
423  u32 reg;
424 
425  if (crypto->cmd == SET_KEY) {
426  /*
427  * rt2x00lib can't determine the correct free
428  * key_idx for pairwise keys. We have 2 registers
429  * with key valid bits. The goal is simple: read
430  * the first register. If that is full, move to
431  * the next register.
432  * When both registers are full, we drop the key.
433  * Otherwise, we use the first invalid entry.
434  */
435  rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
436  if (reg && reg == ~0) {
437  key->hw_key_idx = 32;
438  rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
439  if (reg && reg == ~0)
440  return -ENOSPC;
441  }
442 
443  key->hw_key_idx += reg ? ffz(reg) : 0;
444 
445  /*
446  * Upload key to hardware
447  */
448  memcpy(key_entry.key, crypto->key,
449  sizeof(key_entry.key));
450  memcpy(key_entry.tx_mic, crypto->tx_mic,
451  sizeof(key_entry.tx_mic));
452  memcpy(key_entry.rx_mic, crypto->rx_mic,
453  sizeof(key_entry.rx_mic));
454 
455  memset(&addr_entry, 0, sizeof(addr_entry));
456  memcpy(&addr_entry, crypto->address, ETH_ALEN);
457  addr_entry.cipher = crypto->cipher;
458 
459  reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
460  rt2x00pci_register_multiwrite(rt2x00dev, reg,
461  &key_entry, sizeof(key_entry));
462 
463  reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
464  rt2x00pci_register_multiwrite(rt2x00dev, reg,
465  &addr_entry, sizeof(addr_entry));
466 
467  /*
468  * Enable pairwise lookup table for given BSS idx.
469  * Without this, received frames will not be decrypted
470  * by the hardware.
471  */
472  rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
473  reg |= (1 << crypto->bssidx);
474  rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
475 
476  /*
477  * The driver does not support the IV/EIV generation
478  * in hardware. However it doesn't support the IV/EIV
479  * inside the ieee80211 frame either, but requires it
480  * to be provided separately for the descriptor.
481  * rt2x00lib will cut the IV/EIV data out of all frames
482  * given to us by mac80211, but we must tell mac80211
483  * to generate the IV/EIV data.
484  */
486  }
487 
488  /*
489  * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
490  * a particular key is valid. Because using the FIELD32()
491  * defines directly will cause a lot of overhead, we use
492  * a calculation to determine the correct bit directly.
493  */
494  if (key->hw_key_idx < 32) {
495  mask = 1 << key->hw_key_idx;
496 
497  rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
498  if (crypto->cmd == SET_KEY)
499  reg |= mask;
500  else if (crypto->cmd == DISABLE_KEY)
501  reg &= ~mask;
502  rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
503  } else {
504  mask = 1 << (key->hw_key_idx - 32);
505 
506  rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
507  if (crypto->cmd == SET_KEY)
508  reg |= mask;
509  else if (crypto->cmd == DISABLE_KEY)
510  reg &= ~mask;
511  rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
512  }
513 
514  return 0;
515 }
516 
517 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
518  const unsigned int filter_flags)
519 {
520  u32 reg;
521 
522  /*
523  * Start configuration steps.
524  * Note that the version error will always be dropped
525  * and broadcast frames will always be accepted since
526  * there is no filter for it at this time.
527  */
528  rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
530  !(filter_flags & FIF_FCSFAIL));
532  !(filter_flags & FIF_PLCPFAIL));
534  !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
536  !(filter_flags & FIF_PROMISC_IN_BSS));
538  !(filter_flags & FIF_PROMISC_IN_BSS) &&
539  !rt2x00dev->intf_ap_count);
542  !(filter_flags & FIF_ALLMULTI));
545  !(filter_flags & FIF_CONTROL));
546  rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
547 }
548 
549 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
550  struct rt2x00_intf *intf,
551  struct rt2x00intf_conf *conf,
552  const unsigned int flags)
553 {
554  u32 reg;
555 
556  if (flags & CONFIG_UPDATE_TYPE) {
557  /*
558  * Enable synchronisation.
559  */
560  rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
562  rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
563  }
564 
565  if (flags & CONFIG_UPDATE_MAC) {
566  reg = le32_to_cpu(conf->mac[1]);
568  conf->mac[1] = cpu_to_le32(reg);
569 
570  rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
571  conf->mac, sizeof(conf->mac));
572  }
573 
574  if (flags & CONFIG_UPDATE_BSSID) {
575  reg = le32_to_cpu(conf->bssid[1]);
577  conf->bssid[1] = cpu_to_le32(reg);
578 
579  rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
580  conf->bssid, sizeof(conf->bssid));
581  }
582 }
583 
584 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
585  struct rt2x00lib_erp *erp,
586  u32 changed)
587 {
588  u32 reg;
589 
590  rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
593  rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
594 
595  if (changed & BSS_CHANGED_ERP_PREAMBLE) {
596  rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
599  !!erp->short_preamble);
600  rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
601  }
602 
603  if (changed & BSS_CHANGED_BASIC_RATES)
604  rt2x00pci_register_write(rt2x00dev, TXRX_CSR5,
605  erp->basic_rates);
606 
607  if (changed & BSS_CHANGED_BEACON_INT) {
608  rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
610  erp->beacon_int * 16);
611  rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
612  }
613 
614  if (changed & BSS_CHANGED_ERP_SLOT) {
615  rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
617  rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
618 
619  rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
623  rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
624  }
625 }
626 
627 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
628  struct antenna_setup *ant)
629 {
630  u8 r3;
631  u8 r4;
632  u8 r77;
633 
634  rt61pci_bbp_read(rt2x00dev, 3, &r3);
635  rt61pci_bbp_read(rt2x00dev, 4, &r4);
636  rt61pci_bbp_read(rt2x00dev, 77, &r77);
637 
638  rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
639 
640  /*
641  * Configure the RX antenna.
642  */
643  switch (ant->rx) {
647  (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
648  break;
649  case ANTENNA_A:
652  if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
654  else
656  break;
657  case ANTENNA_B:
658  default:
661  if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
663  else
665  break;
666  }
667 
668  rt61pci_bbp_write(rt2x00dev, 77, r77);
669  rt61pci_bbp_write(rt2x00dev, 3, r3);
670  rt61pci_bbp_write(rt2x00dev, 4, r4);
671 }
672 
673 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
674  struct antenna_setup *ant)
675 {
676  u8 r3;
677  u8 r4;
678  u8 r77;
679 
680  rt61pci_bbp_read(rt2x00dev, 3, &r3);
681  rt61pci_bbp_read(rt2x00dev, 4, &r4);
682  rt61pci_bbp_read(rt2x00dev, 77, &r77);
683 
684  rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
686  !test_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags));
687 
688  /*
689  * Configure the RX antenna.
690  */
691  switch (ant->rx) {
694  break;
695  case ANTENNA_A:
698  break;
699  case ANTENNA_B:
700  default:
703  break;
704  }
705 
706  rt61pci_bbp_write(rt2x00dev, 77, r77);
707  rt61pci_bbp_write(rt2x00dev, 3, r3);
708  rt61pci_bbp_write(rt2x00dev, 4, r4);
709 }
710 
711 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
712  const int p1, const int p2)
713 {
714  u32 reg;
715 
716  rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
717 
720 
723 
724  rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
725 }
726 
727 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
728  struct antenna_setup *ant)
729 {
730  u8 r3;
731  u8 r4;
732  u8 r77;
733 
734  rt61pci_bbp_read(rt2x00dev, 3, &r3);
735  rt61pci_bbp_read(rt2x00dev, 4, &r4);
736  rt61pci_bbp_read(rt2x00dev, 77, &r77);
737 
738  /*
739  * Configure the RX antenna.
740  */
741  switch (ant->rx) {
742  case ANTENNA_A:
745  rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
746  break;
748  /*
749  * FIXME: Antenna selection for the rf 2529 is very confusing
750  * in the legacy driver. Just default to antenna B until the
751  * legacy code can be properly translated into rt2x00 code.
752  */
753  case ANTENNA_B:
754  default:
757  rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
758  break;
759  }
760 
761  rt61pci_bbp_write(rt2x00dev, 77, r77);
762  rt61pci_bbp_write(rt2x00dev, 3, r3);
763  rt61pci_bbp_write(rt2x00dev, 4, r4);
764 }
765 
766 struct antenna_sel {
768  /*
769  * value[0] -> non-LNA
770  * value[1] -> LNA
771  */
772  u8 value[2];
773 };
774 
775 static const struct antenna_sel antenna_sel_a[] = {
776  { 96, { 0x58, 0x78 } },
777  { 104, { 0x38, 0x48 } },
778  { 75, { 0xfe, 0x80 } },
779  { 86, { 0xfe, 0x80 } },
780  { 88, { 0xfe, 0x80 } },
781  { 35, { 0x60, 0x60 } },
782  { 97, { 0x58, 0x58 } },
783  { 98, { 0x58, 0x58 } },
784 };
785 
786 static const struct antenna_sel antenna_sel_bg[] = {
787  { 96, { 0x48, 0x68 } },
788  { 104, { 0x2c, 0x3c } },
789  { 75, { 0xfe, 0x80 } },
790  { 86, { 0xfe, 0x80 } },
791  { 88, { 0xfe, 0x80 } },
792  { 35, { 0x50, 0x50 } },
793  { 97, { 0x48, 0x48 } },
794  { 98, { 0x48, 0x48 } },
795 };
796 
797 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
798  struct antenna_setup *ant)
799 {
800  const struct antenna_sel *sel;
801  unsigned int lna;
802  unsigned int i;
803  u32 reg;
804 
805  /*
806  * We should never come here because rt2x00lib is supposed
807  * to catch this and send us the correct antenna explicitely.
808  */
809  BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
810  ant->tx == ANTENNA_SW_DIVERSITY);
811 
812  if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
813  sel = antenna_sel_a;
814  lna = test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
815  } else {
816  sel = antenna_sel_bg;
817  lna = test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
818  }
819 
820  for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
821  rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
822 
823  rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
824 
826  rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
828  rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
829 
830  rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
831 
832  if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
833  rt61pci_config_antenna_5x(rt2x00dev, ant);
834  else if (rt2x00_rf(rt2x00dev, RF2527))
835  rt61pci_config_antenna_2x(rt2x00dev, ant);
836  else if (rt2x00_rf(rt2x00dev, RF2529)) {
837  if (test_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags))
838  rt61pci_config_antenna_2x(rt2x00dev, ant);
839  else
840  rt61pci_config_antenna_2529(rt2x00dev, ant);
841  }
842 }
843 
844 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
845  struct rt2x00lib_conf *libconf)
846 {
847  u16 eeprom;
848  short lna_gain = 0;
849 
850  if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
852  lna_gain += 14;
853 
854  rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
855  lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
856  } else {
857  if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
858  lna_gain += 14;
859 
860  rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
861  lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
862  }
863 
864  rt2x00dev->lna_gain = lna_gain;
865 }
866 
867 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
868  struct rf_channel *rf, const int txpower)
869 {
870  u8 r3;
871  u8 r94;
872  u8 smart;
873 
876 
877  smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
878 
879  rt61pci_bbp_read(rt2x00dev, 3, &r3);
881  rt61pci_bbp_write(rt2x00dev, 3, r3);
882 
883  r94 = 6;
884  if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
885  r94 += txpower - MAX_TXPOWER;
886  else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
887  r94 += txpower;
888  rt61pci_bbp_write(rt2x00dev, 94, r94);
889 
890  rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
891  rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
892  rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
893  rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
894 
895  udelay(200);
896 
897  rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
898  rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
899  rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
900  rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
901 
902  udelay(200);
903 
904  rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
905  rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
906  rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
907  rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
908 
909  msleep(1);
910 }
911 
912 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
913  const int txpower)
914 {
915  struct rf_channel rf;
916 
917  rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
918  rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
919  rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
920  rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
921 
922  rt61pci_config_channel(rt2x00dev, &rf, txpower);
923 }
924 
925 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
926  struct rt2x00lib_conf *libconf)
927 {
928  u32 reg;
929 
930  rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
935  libconf->conf->long_frame_max_tx_count);
937  libconf->conf->short_frame_max_tx_count);
938  rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
939 }
940 
941 static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
942  struct rt2x00lib_conf *libconf)
943 {
944  enum dev_state state =
945  (libconf->conf->flags & IEEE80211_CONF_PS) ?
947  u32 reg;
948 
949  if (state == STATE_SLEEP) {
950  rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
952  rt2x00dev->beacon_int - 10);
954  libconf->conf->listen_interval - 1);
956 
957  /* We must first disable autowake before it can be enabled */
959  rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
960 
962  rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
963 
964  rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
965  rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
966  rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
967 
968  rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
969  } else {
970  rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
975  rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
976 
977  rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
978  rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
979  rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
980 
981  rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
982  }
983 }
984 
985 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
986  struct rt2x00lib_conf *libconf,
987  const unsigned int flags)
988 {
989  /* Always recalculate LNA gain before changing configuration */
990  rt61pci_config_lna_gain(rt2x00dev, libconf);
991 
992  if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
993  rt61pci_config_channel(rt2x00dev, &libconf->rf,
994  libconf->conf->power_level);
995  if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
996  !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
997  rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
999  rt61pci_config_retry_limit(rt2x00dev, libconf);
1000  if (flags & IEEE80211_CONF_CHANGE_PS)
1001  rt61pci_config_ps(rt2x00dev, libconf);
1002 }
1003 
1004 /*
1005  * Link tuning
1006  */
1007 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1008  struct link_qual *qual)
1009 {
1010  u32 reg;
1011 
1012  /*
1013  * Update FCS error count from register.
1014  */
1015  rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1017 
1018  /*
1019  * Update False CCA count from register.
1020  */
1021  rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1023 }
1024 
1025 static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1026  struct link_qual *qual, u8 vgc_level)
1027 {
1028  if (qual->vgc_level != vgc_level) {
1029  rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
1030  qual->vgc_level = vgc_level;
1031  qual->vgc_level_reg = vgc_level;
1032  }
1033 }
1034 
1035 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1036  struct link_qual *qual)
1037 {
1038  rt61pci_set_vgc(rt2x00dev, qual, 0x20);
1039 }
1040 
1041 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1042  struct link_qual *qual, const u32 count)
1043 {
1044  u8 up_bound;
1045  u8 low_bound;
1046 
1047  /*
1048  * Determine r17 bounds.
1049  */
1050  if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1051  low_bound = 0x28;
1052  up_bound = 0x48;
1053  if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags)) {
1054  low_bound += 0x10;
1055  up_bound += 0x10;
1056  }
1057  } else {
1058  low_bound = 0x20;
1059  up_bound = 0x40;
1060  if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags)) {
1061  low_bound += 0x10;
1062  up_bound += 0x10;
1063  }
1064  }
1065 
1066  /*
1067  * If we are not associated, we should go straight to the
1068  * dynamic CCA tuning.
1069  */
1070  if (!rt2x00dev->intf_associated)
1071  goto dynamic_cca_tune;
1072 
1073  /*
1074  * Special big-R17 for very short distance
1075  */
1076  if (qual->rssi >= -35) {
1077  rt61pci_set_vgc(rt2x00dev, qual, 0x60);
1078  return;
1079  }
1080 
1081  /*
1082  * Special big-R17 for short distance
1083  */
1084  if (qual->rssi >= -58) {
1085  rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1086  return;
1087  }
1088 
1089  /*
1090  * Special big-R17 for middle-short distance
1091  */
1092  if (qual->rssi >= -66) {
1093  rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
1094  return;
1095  }
1096 
1097  /*
1098  * Special mid-R17 for middle distance
1099  */
1100  if (qual->rssi >= -74) {
1101  rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1102  return;
1103  }
1104 
1105  /*
1106  * Special case: Change up_bound based on the rssi.
1107  * Lower up_bound when rssi is weaker then -74 dBm.
1108  */
1109  up_bound -= 2 * (-74 - qual->rssi);
1110  if (low_bound > up_bound)
1111  up_bound = low_bound;
1112 
1113  if (qual->vgc_level > up_bound) {
1114  rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1115  return;
1116  }
1117 
1118 dynamic_cca_tune:
1119 
1120  /*
1121  * r17 does not yet exceed upper limit, continue and base
1122  * the r17 tuning on the false CCA count.
1123  */
1124  if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1125  rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1126  else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1127  rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
1128 }
1129 
1130 /*
1131  * Queue handlers.
1132  */
1133 static void rt61pci_start_queue(struct data_queue *queue)
1134 {
1135  struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1136  u32 reg;
1137 
1138  switch (queue->qid) {
1139  case QID_RX:
1140  rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1142  rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1143  break;
1144  case QID_BEACON:
1145  rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1149  rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1150  break;
1151  default:
1152  break;
1153  }
1154 }
1155 
1156 static void rt61pci_kick_queue(struct data_queue *queue)
1157 {
1158  struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1159  u32 reg;
1160 
1161  switch (queue->qid) {
1162  case QID_AC_VO:
1163  rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1165  rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1166  break;
1167  case QID_AC_VI:
1168  rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1170  rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1171  break;
1172  case QID_AC_BE:
1173  rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1175  rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1176  break;
1177  case QID_AC_BK:
1178  rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1180  rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1181  break;
1182  default:
1183  break;
1184  }
1185 }
1186 
1187 static void rt61pci_stop_queue(struct data_queue *queue)
1188 {
1189  struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1190  u32 reg;
1191 
1192  switch (queue->qid) {
1193  case QID_AC_VO:
1194  rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1196  rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1197  break;
1198  case QID_AC_VI:
1199  rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1201  rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1202  break;
1203  case QID_AC_BE:
1204  rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1206  rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1207  break;
1208  case QID_AC_BK:
1209  rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1211  rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1212  break;
1213  case QID_RX:
1214  rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1216  rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1217  break;
1218  case QID_BEACON:
1219  rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1223  rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1224 
1225  /*
1226  * Wait for possibly running tbtt tasklets.
1227  */
1228  tasklet_kill(&rt2x00dev->tbtt_tasklet);
1229  break;
1230  default:
1231  break;
1232  }
1233 }
1234 
1235 /*
1236  * Firmware functions
1237  */
1238 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1239 {
1240  u16 chip;
1241  char *fw_name;
1242 
1243  pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
1244  switch (chip) {
1245  case RT2561_PCI_ID:
1246  fw_name = FIRMWARE_RT2561;
1247  break;
1248  case RT2561s_PCI_ID:
1249  fw_name = FIRMWARE_RT2561s;
1250  break;
1251  case RT2661_PCI_ID:
1252  fw_name = FIRMWARE_RT2661;
1253  break;
1254  default:
1255  fw_name = NULL;
1256  break;
1257  }
1258 
1259  return fw_name;
1260 }
1261 
1262 static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1263  const u8 *data, const size_t len)
1264 {
1265  u16 fw_crc;
1266  u16 crc;
1267 
1268  /*
1269  * Only support 8kb firmware files.
1270  */
1271  if (len != 8192)
1272  return FW_BAD_LENGTH;
1273 
1274  /*
1275  * The last 2 bytes in the firmware array are the crc checksum itself.
1276  * This means that we should never pass those 2 bytes to the crc
1277  * algorithm.
1278  */
1279  fw_crc = (data[len - 2] << 8 | data[len - 1]);
1280 
1281  /*
1282  * Use the crc itu-t algorithm.
1283  */
1284  crc = crc_itu_t(0, data, len - 2);
1285  crc = crc_itu_t_byte(crc, 0);
1286  crc = crc_itu_t_byte(crc, 0);
1287 
1288  return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1289 }
1290 
1291 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1292  const u8 *data, const size_t len)
1293 {
1294  int i;
1295  u32 reg;
1296 
1297  /*
1298  * Wait for stable hardware.
1299  */
1300  for (i = 0; i < 100; i++) {
1301  rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1302  if (reg)
1303  break;
1304  msleep(1);
1305  }
1306 
1307  if (!reg) {
1308  ERROR(rt2x00dev, "Unstable hardware.\n");
1309  return -EBUSY;
1310  }
1311 
1312  /*
1313  * Prepare MCU and mailbox for firmware loading.
1314  */
1315  reg = 0;
1317  rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1318  rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1319  rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1320  rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1321 
1322  /*
1323  * Write firmware to device.
1324  */
1325  reg = 0;
1328  rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1329 
1330  rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1331  data, len);
1332 
1334  rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1335 
1337  rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1338 
1339  for (i = 0; i < 100; i++) {
1340  rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1342  break;
1343  msleep(1);
1344  }
1345 
1346  if (i == 100) {
1347  ERROR(rt2x00dev, "MCU Control register not ready.\n");
1348  return -EBUSY;
1349  }
1350 
1351  /*
1352  * Hardware needs another millisecond before it is ready.
1353  */
1354  msleep(1);
1355 
1356  /*
1357  * Reset MAC and BBP registers.
1358  */
1359  reg = 0;
1362  rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1363 
1364  rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1367  rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1368 
1369  rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1371  rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1372 
1373  return 0;
1374 }
1375 
1376 /*
1377  * Initialization functions.
1378  */
1379 static bool rt61pci_get_entry_state(struct queue_entry *entry)
1380 {
1381  struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1382  u32 word;
1383 
1384  if (entry->queue->qid == QID_RX) {
1385  rt2x00_desc_read(entry_priv->desc, 0, &word);
1386 
1387  return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1388  } else {
1389  rt2x00_desc_read(entry_priv->desc, 0, &word);
1390 
1391  return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1393  }
1394 }
1395 
1396 static void rt61pci_clear_entry(struct queue_entry *entry)
1397 {
1398  struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1399  struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1400  u32 word;
1401 
1402  if (entry->queue->qid == QID_RX) {
1403  rt2x00_desc_read(entry_priv->desc, 5, &word);
1405  skbdesc->skb_dma);
1406  rt2x00_desc_write(entry_priv->desc, 5, word);
1407 
1408  rt2x00_desc_read(entry_priv->desc, 0, &word);
1410  rt2x00_desc_write(entry_priv->desc, 0, word);
1411  } else {
1412  rt2x00_desc_read(entry_priv->desc, 0, &word);
1413  rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1415  rt2x00_desc_write(entry_priv->desc, 0, word);
1416  }
1417 }
1418 
1419 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1420 {
1421  struct queue_entry_priv_pci *entry_priv;
1422  u32 reg;
1423 
1424  /*
1425  * Initialize registers.
1426  */
1427  rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1429  rt2x00dev->tx[0].limit);
1431  rt2x00dev->tx[1].limit);
1433  rt2x00dev->tx[2].limit);
1435  rt2x00dev->tx[3].limit);
1436  rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1437 
1438  rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1440  rt2x00dev->tx[0].desc_size / 4);
1441  rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1442 
1443  entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1444  rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1446  entry_priv->desc_dma);
1447  rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1448 
1449  entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1450  rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1452  entry_priv->desc_dma);
1453  rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1454 
1455  entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1456  rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1458  entry_priv->desc_dma);
1459  rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1460 
1461  entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1462  rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1464  entry_priv->desc_dma);
1465  rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1466 
1467  rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1468  rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1470  rt2x00dev->rx->desc_size / 4);
1472  rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1473 
1474  entry_priv = rt2x00dev->rx->entries[0].priv_data;
1475  rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1477  entry_priv->desc_dma);
1478  rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1479 
1480  rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1485  rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1486 
1487  rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1492  rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1493 
1494  rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1496  rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1497 
1498  return 0;
1499 }
1500 
1501 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1502 {
1503  u32 reg;
1504 
1505  rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1509  rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1510 
1511  rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1512  rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1514  rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1516  rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1518  rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1520  rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1521 
1522  /*
1523  * CCK TXD BBP registers
1524  */
1525  rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1534  rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1535 
1536  /*
1537  * OFDM TXD BBP registers
1538  */
1539  rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1546  rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1547 
1548  rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1553  rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1554 
1555  rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1560  rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1561 
1562  rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1569  rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1570 
1571  rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1572 
1573  rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1574 
1575  rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1577  rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1578 
1579  rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1580 
1581  if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1582  return -EBUSY;
1583 
1584  rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1585 
1586  /*
1587  * Invalidate all Shared Keys (SEC_CSR0),
1588  * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1589  */
1590  rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1591  rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1592  rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1593 
1594  rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1595  rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1596  rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1597  rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1598 
1599  rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1600 
1601  rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1602 
1603  rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1604 
1605  /*
1606  * Clear all beacons
1607  * For the Beacon base registers we only need to clear
1608  * the first byte since that byte contains the VALID and OWNER
1609  * bits which (when set to 0) will invalidate the entire beacon.
1610  */
1611  rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1612  rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1613  rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1614  rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1615 
1616  /*
1617  * We must clear the error counters.
1618  * These registers are cleared on read,
1619  * so we may pass a useless variable to store the value.
1620  */
1621  rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1622  rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1623  rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1624 
1625  /*
1626  * Reset MAC and BBP registers.
1627  */
1628  rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1631  rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1632 
1633  rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1636  rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1637 
1638  rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1640  rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1641 
1642  return 0;
1643 }
1644 
1645 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1646 {
1647  unsigned int i;
1648  u8 value;
1649 
1650  for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1651  rt61pci_bbp_read(rt2x00dev, 0, &value);
1652  if ((value != 0xff) && (value != 0x00))
1653  return 0;
1655  }
1656 
1657  ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1658  return -EACCES;
1659 }
1660 
1661 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1662 {
1663  unsigned int i;
1664  u16 eeprom;
1665  u8 reg_id;
1666  u8 value;
1667 
1668  if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1669  return -EACCES;
1670 
1671  rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1672  rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1673  rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1674  rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1675  rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1676  rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1677  rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1678  rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1679  rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1680  rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1681  rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1682  rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1683  rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1684  rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1685  rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1686  rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1687  rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1688  rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1689  rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1690  rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1691  rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1692  rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1693  rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1694  rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1695 
1696  for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1697  rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1698 
1699  if (eeprom != 0xffff && eeprom != 0x0000) {
1700  reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1701  value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1702  rt61pci_bbp_write(rt2x00dev, reg_id, value);
1703  }
1704  }
1705 
1706  return 0;
1707 }
1708 
1709 /*
1710  * Device state switch handlers.
1711  */
1712 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1713  enum dev_state state)
1714 {
1715  int mask = (state == STATE_RADIO_IRQ_OFF);
1716  u32 reg;
1717  unsigned long flags;
1718 
1719  /*
1720  * When interrupts are being enabled, the interrupt registers
1721  * should clear the register to assure a clean state.
1722  */
1723  if (state == STATE_RADIO_IRQ_ON) {
1724  rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1725  rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1726 
1727  rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1728  rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1729  }
1730 
1731  /*
1732  * Only toggle the interrupts bits we are going to use.
1733  * Non-checked interrupt bits are disabled by default.
1734  */
1735  spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1736 
1737  rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1743  rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1744 
1745  rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1755  rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1756 
1757  spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1758 
1759  if (state == STATE_RADIO_IRQ_OFF) {
1760  /*
1761  * Ensure that all tasklets are finished.
1762  */
1763  tasklet_kill(&rt2x00dev->txstatus_tasklet);
1764  tasklet_kill(&rt2x00dev->rxdone_tasklet);
1765  tasklet_kill(&rt2x00dev->autowake_tasklet);
1766  tasklet_kill(&rt2x00dev->tbtt_tasklet);
1767  }
1768 }
1769 
1770 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1771 {
1772  u32 reg;
1773 
1774  /*
1775  * Initialize all registers.
1776  */
1777  if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1778  rt61pci_init_registers(rt2x00dev) ||
1779  rt61pci_init_bbp(rt2x00dev)))
1780  return -EIO;
1781 
1782  /*
1783  * Enable RX.
1784  */
1785  rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1787  rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1788 
1789  return 0;
1790 }
1791 
1792 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1793 {
1794  /*
1795  * Disable power
1796  */
1797  rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1798 }
1799 
1800 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1801 {
1802  u32 reg, reg2;
1803  unsigned int i;
1804  char put_to_sleep;
1805 
1806  put_to_sleep = (state != STATE_AWAKE);
1807 
1808  rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1809  rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1810  rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1811  rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1812 
1813  /*
1814  * Device is not guaranteed to be in the requested state yet.
1815  * We must wait until the register indicates that the
1816  * device has entered the correct state.
1817  */
1818  for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1819  rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg2);
1821  if (state == !put_to_sleep)
1822  return 0;
1823  rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1824  msleep(10);
1825  }
1826 
1827  return -EBUSY;
1828 }
1829 
1830 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1831  enum dev_state state)
1832 {
1833  int retval = 0;
1834 
1835  switch (state) {
1836  case STATE_RADIO_ON:
1837  retval = rt61pci_enable_radio(rt2x00dev);
1838  break;
1839  case STATE_RADIO_OFF:
1840  rt61pci_disable_radio(rt2x00dev);
1841  break;
1842  case STATE_RADIO_IRQ_ON:
1843  case STATE_RADIO_IRQ_OFF:
1844  rt61pci_toggle_irq(rt2x00dev, state);
1845  break;
1846  case STATE_DEEP_SLEEP:
1847  case STATE_SLEEP:
1848  case STATE_STANDBY:
1849  case STATE_AWAKE:
1850  retval = rt61pci_set_state(rt2x00dev, state);
1851  break;
1852  default:
1853  retval = -ENOTSUPP;
1854  break;
1855  }
1856 
1857  if (unlikely(retval))
1858  ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1859  state, retval);
1860 
1861  return retval;
1862 }
1863 
1864 /*
1865  * TX descriptor initialization
1866  */
1867 static void rt61pci_write_tx_desc(struct queue_entry *entry,
1868  struct txentry_desc *txdesc)
1869 {
1870  struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1871  struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1872  __le32 *txd = entry_priv->desc;
1873  u32 word;
1874 
1875  /*
1876  * Start writing the descriptor words.
1877  */
1878  rt2x00_desc_read(txd, 1, &word);
1879  rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
1880  rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
1881  rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1882  rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
1887  rt2x00_desc_write(txd, 1, word);
1888 
1889  rt2x00_desc_read(txd, 2, &word);
1890  rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
1891  rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
1893  txdesc->u.plcp.length_low);
1895  txdesc->u.plcp.length_high);
1896  rt2x00_desc_write(txd, 2, word);
1897 
1898  if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1899  _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1900  _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1901  }
1902 
1903  rt2x00_desc_read(txd, 5, &word);
1904  rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1906  skbdesc->entry->entry_idx);
1908  TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
1910  rt2x00_desc_write(txd, 5, word);
1911 
1912  if (entry->queue->qid != QID_BEACON) {
1913  rt2x00_desc_read(txd, 6, &word);
1915  skbdesc->skb_dma);
1916  rt2x00_desc_write(txd, 6, word);
1917 
1918  rt2x00_desc_read(txd, 11, &word);
1920  txdesc->length);
1921  rt2x00_desc_write(txd, 11, word);
1922  }
1923 
1924  /*
1925  * Writing TXD word 0 must the last to prevent a race condition with
1926  * the device, whereby the device may take hold of the TXD before we
1927  * finished updating it.
1928  */
1929  rt2x00_desc_read(txd, 0, &word);
1931  rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1933  test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1935  test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1939  (txdesc->rate_mode == RATE_MODE_OFDM));
1940  rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1942  test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1947  rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1950  test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1951  rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1952  rt2x00_desc_write(txd, 0, word);
1953 
1954  /*
1955  * Register descriptor details in skb frame descriptor.
1956  */
1957  skbdesc->desc = txd;
1958  skbdesc->desc_len = (entry->queue->qid == QID_BEACON) ? TXINFO_SIZE :
1959  TXD_DESC_SIZE;
1960 }
1961 
1962 /*
1963  * TX data initialization
1964  */
1965 static void rt61pci_write_beacon(struct queue_entry *entry,
1966  struct txentry_desc *txdesc)
1967 {
1968  struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1969  struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1970  unsigned int beacon_base;
1971  unsigned int padding_len;
1972  u32 orig_reg, reg;
1973 
1974  /*
1975  * Disable beaconing while we are reloading the beacon data,
1976  * otherwise we might be sending out invalid data.
1977  */
1978  rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1979  orig_reg = reg;
1981  rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1982 
1983  /*
1984  * Write the TX descriptor for the beacon.
1985  */
1986  rt61pci_write_tx_desc(entry, txdesc);
1987 
1988  /*
1989  * Dump beacon to userspace through debugfs.
1990  */
1991  rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1992 
1993  /*
1994  * Write entire beacon with descriptor and padding to register.
1995  */
1996  padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1997  if (padding_len && skb_pad(entry->skb, padding_len)) {
1998  ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
1999  /* skb freed by skb_pad() on failure */
2000  entry->skb = NULL;
2001  rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
2002  return;
2003  }
2004 
2005  beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2006  rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
2007  entry_priv->desc, TXINFO_SIZE);
2008  rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
2009  entry->skb->data,
2010  entry->skb->len + padding_len);
2011 
2012  /*
2013  * Enable beaconing again.
2014  *
2015  * For Wi-Fi faily generated beacons between participating
2016  * stations. Set TBTT phase adaptive adjustment step to 8us.
2017  */
2018  rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
2019 
2021  rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2022 
2023  /*
2024  * Clean up beacon skb.
2025  */
2026  dev_kfree_skb_any(entry->skb);
2027  entry->skb = NULL;
2028 }
2029 
2030 static void rt61pci_clear_beacon(struct queue_entry *entry)
2031 {
2032  struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2033  u32 reg;
2034 
2035  /*
2036  * Disable beaconing while we are reloading the beacon data,
2037  * otherwise we might be sending out invalid data.
2038  */
2039  rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
2041  rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2042 
2043  /*
2044  * Clear beacon.
2045  */
2046  rt2x00pci_register_write(rt2x00dev,
2047  HW_BEACON_OFFSET(entry->entry_idx), 0);
2048 
2049  /*
2050  * Enable beaconing again.
2051  */
2053  rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2054 }
2055 
2056 /*
2057  * RX control handlers
2058  */
2059 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
2060 {
2061  u8 offset = rt2x00dev->lna_gain;
2062  u8 lna;
2063 
2064  lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
2065  switch (lna) {
2066  case 3:
2067  offset += 90;
2068  break;
2069  case 2:
2070  offset += 74;
2071  break;
2072  case 1:
2073  offset += 64;
2074  break;
2075  default:
2076  return 0;
2077  }
2078 
2079  if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
2080  if (lna == 3 || lna == 2)
2081  offset += 10;
2082  }
2083 
2084  return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
2085 }
2086 
2087 static void rt61pci_fill_rxdone(struct queue_entry *entry,
2088  struct rxdone_entry_desc *rxdesc)
2089 {
2090  struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2091  struct queue_entry_priv_pci *entry_priv = entry->priv_data;
2092  u32 word0;
2093  u32 word1;
2094 
2095  rt2x00_desc_read(entry_priv->desc, 0, &word0);
2096  rt2x00_desc_read(entry_priv->desc, 1, &word1);
2097 
2099  rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2100 
2101  rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
2103 
2104  if (rxdesc->cipher != CIPHER_NONE) {
2105  _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
2106  _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
2107  rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
2108 
2109  _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
2110  rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
2111 
2112  /*
2113  * Hardware has stripped IV/EIV data from 802.11 frame during
2114  * decryption. It has provided the data separately but rt2x00lib
2115  * should decide if it should be reinserted.
2116  */
2117  rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2118 
2119  /*
2120  * The hardware has already checked the Michael Mic and has
2121  * stripped it from the frame. Signal this to mac80211.
2122  */
2123  rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2124 
2125  if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2126  rxdesc->flags |= RX_FLAG_DECRYPTED;
2127  else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2128  rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2129  }
2130 
2131  /*
2132  * Obtain the status about this packet.
2133  * When frame was received with an OFDM bitrate,
2134  * the signal is the PLCP value. If it was received with
2135  * a CCK bitrate the signal is the rate in 100kbit/s.
2136  */
2137  rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
2138  rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
2139  rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
2140 
2141  if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2142  rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
2143  else
2144  rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
2145  if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2146  rxdesc->dev_flags |= RXDONE_MY_BSS;
2147 }
2148 
2149 /*
2150  * Interrupt functions.
2151  */
2152 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2153 {
2154  struct data_queue *queue;
2155  struct queue_entry *entry;
2156  struct queue_entry *entry_done;
2157  struct queue_entry_priv_pci *entry_priv;
2158  struct txdone_entry_desc txdesc;
2159  u32 word;
2160  u32 reg;
2161  int type;
2162  int index;
2163  int i;
2164 
2165  /*
2166  * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
2167  * at most X times and also stop processing once the TX_STA_FIFO_VALID
2168  * flag is not set anymore.
2169  *
2170  * The legacy drivers use X=TX_RING_SIZE but state in a comment
2171  * that the TX_STA_FIFO stack has a size of 16. We stick to our
2172  * tx ring size for now.
2173  */
2174  for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
2175  rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2177  break;
2178 
2179  /*
2180  * Skip this entry when it contains an invalid
2181  * queue identication number.
2182  */
2184  queue = rt2x00queue_get_tx_queue(rt2x00dev, type);
2185  if (unlikely(!queue))
2186  continue;
2187 
2188  /*
2189  * Skip this entry when it contains an invalid
2190  * index number.
2191  */
2193  if (unlikely(index >= queue->limit))
2194  continue;
2195 
2196  entry = &queue->entries[index];
2197  entry_priv = entry->priv_data;
2198  rt2x00_desc_read(entry_priv->desc, 0, &word);
2199 
2200  if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2202  return;
2203 
2204  entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2205  while (entry != entry_done) {
2206  /* Catch up.
2207  * Just report any entries we missed as failed.
2208  */
2209  WARNING(rt2x00dev,
2210  "TX status report missed for entry %d\n",
2211  entry_done->entry_idx);
2212 
2214  entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2215  }
2216 
2217  /*
2218  * Obtain the status about this packet.
2219  */
2220  txdesc.flags = 0;
2221  switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2222  case 0: /* Success, maybe with retry */
2223  __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2224  break;
2225  case 6: /* Failure, excessive retries */
2227  /* Don't break, this is a failed frame! */
2228  default: /* Failure */
2229  __set_bit(TXDONE_FAILURE, &txdesc.flags);
2230  }
2231  txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2232 
2233  /*
2234  * the frame was retried at least once
2235  * -> hw used fallback rates
2236  */
2237  if (txdesc.retry)
2238  __set_bit(TXDONE_FALLBACK, &txdesc.flags);
2239 
2240  rt2x00lib_txdone(entry, &txdesc);
2241  }
2242 }
2243 
2244 static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2245 {
2246  struct rt2x00lib_conf libconf = { .conf = &rt2x00dev->hw->conf };
2247 
2248  rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2249 }
2250 
2251 static inline void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
2252  struct rt2x00_field32 irq_field)
2253 {
2254  u32 reg;
2255 
2256  /*
2257  * Enable a single interrupt. The interrupt mask register
2258  * access needs locking.
2259  */
2260  spin_lock_irq(&rt2x00dev->irqmask_lock);
2261 
2262  rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2263  rt2x00_set_field32(&reg, irq_field, 0);
2264  rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
2265 
2266  spin_unlock_irq(&rt2x00dev->irqmask_lock);
2267 }
2268 
2269 static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev,
2270  struct rt2x00_field32 irq_field)
2271 {
2272  u32 reg;
2273 
2274  /*
2275  * Enable a single MCU interrupt. The interrupt mask register
2276  * access needs locking.
2277  */
2278  spin_lock_irq(&rt2x00dev->irqmask_lock);
2279 
2280  rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2281  rt2x00_set_field32(&reg, irq_field, 0);
2282  rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2283 
2284  spin_unlock_irq(&rt2x00dev->irqmask_lock);
2285 }
2286 
2287 static void rt61pci_txstatus_tasklet(unsigned long data)
2288 {
2289  struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2290  rt61pci_txdone(rt2x00dev);
2291  if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2292  rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TXDONE);
2293 }
2294 
2295 static void rt61pci_tbtt_tasklet(unsigned long data)
2296 {
2297  struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2298  rt2x00lib_beacondone(rt2x00dev);
2299  if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2300  rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_BEACON_DONE);
2301 }
2302 
2303 static void rt61pci_rxdone_tasklet(unsigned long data)
2304 {
2305  struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2306  if (rt2x00pci_rxdone(rt2x00dev))
2307  tasklet_schedule(&rt2x00dev->rxdone_tasklet);
2308  else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2309  rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RXDONE);
2310 }
2311 
2312 static void rt61pci_autowake_tasklet(unsigned long data)
2313 {
2314  struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2315  rt61pci_wakeup(rt2x00dev);
2316  rt2x00pci_register_write(rt2x00dev,
2317  M2H_CMD_DONE_CSR, 0xffffffff);
2318  if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2319  rt61pci_enable_mcu_interrupt(rt2x00dev, MCU_INT_MASK_CSR_TWAKEUP);
2320 }
2321 
2322 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2323 {
2324  struct rt2x00_dev *rt2x00dev = dev_instance;
2325  u32 reg_mcu, mask_mcu;
2326  u32 reg, mask;
2327 
2328  /*
2329  * Get the interrupt sources & saved to local variable.
2330  * Write register value back to clear pending interrupts.
2331  */
2332  rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2333  rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2334 
2335  rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2336  rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2337 
2338  if (!reg && !reg_mcu)
2339  return IRQ_NONE;
2340 
2341  if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2342  return IRQ_HANDLED;
2343 
2344  /*
2345  * Schedule tasklets for interrupt handling.
2346  */
2348  tasklet_schedule(&rt2x00dev->rxdone_tasklet);
2349 
2351  tasklet_schedule(&rt2x00dev->txstatus_tasklet);
2352 
2354  tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
2355 
2357  tasklet_schedule(&rt2x00dev->autowake_tasklet);
2358 
2359  /*
2360  * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
2361  * for interrupts and interrupt masks we can just use the value of
2362  * INT_SOURCE_CSR to create the interrupt mask.
2363  */
2364  mask = reg;
2365  mask_mcu = reg_mcu;
2366 
2367  /*
2368  * Disable all interrupts for which a tasklet was scheduled right now,
2369  * the tasklet will reenable the appropriate interrupts.
2370  */
2371  spin_lock(&rt2x00dev->irqmask_lock);
2372 
2373  rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2374  reg |= mask;
2375  rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
2376 
2377  rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2378  reg |= mask_mcu;
2379  rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2380 
2381  spin_unlock(&rt2x00dev->irqmask_lock);
2382 
2383  return IRQ_HANDLED;
2384 }
2385 
2386 /*
2387  * Device probe functions.
2388  */
2389 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2390 {
2391  struct eeprom_93cx6 eeprom;
2392  u32 reg;
2393  u16 word;
2394  u8 *mac;
2395  s8 value;
2396 
2397  rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2398 
2399  eeprom.data = rt2x00dev;
2400  eeprom.register_read = rt61pci_eepromregister_read;
2401  eeprom.register_write = rt61pci_eepromregister_write;
2402  eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2404  eeprom.reg_data_in = 0;
2405  eeprom.reg_data_out = 0;
2406  eeprom.reg_data_clock = 0;
2407  eeprom.reg_chip_select = 0;
2408 
2409  eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2410  EEPROM_SIZE / sizeof(u16));
2411 
2412  /*
2413  * Start validation of the data that has been read.
2414  */
2415  mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2416  if (!is_valid_ether_addr(mac)) {
2417  eth_random_addr(mac);
2418  EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2419  }
2420 
2421  rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2422  if (word == 0xffff) {
2425  ANTENNA_B);
2427  ANTENNA_B);
2432  rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2433  EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2434  }
2435 
2436  rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2437  if (word == 0xffff) {
2445  rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2446  EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2447  }
2448 
2449  rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2450  if (word == 0xffff) {
2453  rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2454  EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2455  }
2456 
2457  rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2458  if (word == 0xffff) {
2461  rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2462  EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2463  }
2464 
2465  rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2466  if (word == 0xffff) {
2469  rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2470  EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2471  } else {
2473  if (value < -10 || value > 10)
2476  if (value < -10 || value > 10)
2478  rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2479  }
2480 
2481  rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2482  if (word == 0xffff) {
2485  rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2486  EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2487  } else {
2489  if (value < -10 || value > 10)
2492  if (value < -10 || value > 10)
2494  rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2495  }
2496 
2497  return 0;
2498 }
2499 
2500 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2501 {
2502  u32 reg;
2503  u16 value;
2504  u16 eeprom;
2505 
2506  /*
2507  * Read EEPROM word for configuration.
2508  */
2509  rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2510 
2511  /*
2512  * Identify RF chipset.
2513  */
2514  value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2515  rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2516  rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2517  value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2518 
2519  if (!rt2x00_rf(rt2x00dev, RF5225) &&
2520  !rt2x00_rf(rt2x00dev, RF5325) &&
2521  !rt2x00_rf(rt2x00dev, RF2527) &&
2522  !rt2x00_rf(rt2x00dev, RF2529)) {
2523  ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2524  return -ENODEV;
2525  }
2526 
2527  /*
2528  * Determine number of antennas.
2529  */
2530  if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2532 
2533  /*
2534  * Identify default antenna configuration.
2535  */
2536  rt2x00dev->default_ant.tx =
2538  rt2x00dev->default_ant.rx =
2540 
2541  /*
2542  * Read the Frame type.
2543  */
2546 
2547  /*
2548  * Detect if this device has a hardware controlled radio.
2549  */
2552 
2553  /*
2554  * Read frequency offset and RF programming sequence.
2555  */
2556  rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2557  if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2559 
2560  rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2561 
2562  /*
2563  * Read external LNA informations.
2564  */
2565  rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2566 
2571 
2572  /*
2573  * When working with a RF2529 chip without double antenna,
2574  * the antenna settings should be gathered from the NIC
2575  * eeprom word.
2576  */
2577  if (rt2x00_rf(rt2x00dev, RF2529) &&
2578  !test_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags)) {
2579  rt2x00dev->default_ant.rx =
2581  rt2x00dev->default_ant.tx =
2583 
2585  rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2587  rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2588  }
2589 
2590  /*
2591  * Store led settings, for correct led behaviour.
2592  * If the eeprom value is invalid,
2593  * switch to default led mode.
2594  */
2595 #ifdef CONFIG_RT2X00_LIB_LEDS
2596  rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2597  value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2598 
2599  rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2600  rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2601  if (value == LED_MODE_SIGNAL_STRENGTH)
2602  rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2604 
2605  rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2606  rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2607  rt2x00_get_field16(eeprom,
2609  rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2610  rt2x00_get_field16(eeprom,
2612  rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2613  rt2x00_get_field16(eeprom,
2615  rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2616  rt2x00_get_field16(eeprom,
2618  rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2619  rt2x00_get_field16(eeprom,
2621  rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2623  rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2624  rt2x00_get_field16(eeprom,
2626  rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2627  rt2x00_get_field16(eeprom,
2629 #endif /* CONFIG_RT2X00_LIB_LEDS */
2630 
2631  return 0;
2632 }
2633 
2634 /*
2635  * RF value list for RF5225 & RF5325
2636  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2637  */
2638 static const struct rf_channel rf_vals_noseq[] = {
2639  { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2640  { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2641  { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2642  { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2643  { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2644  { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2645  { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2646  { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2647  { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2648  { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2649  { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2650  { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2651  { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2652  { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2653 
2654  /* 802.11 UNI / HyperLan 2 */
2655  { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2656  { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2657  { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2658  { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2659  { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2660  { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2661  { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2662  { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2663 
2664  /* 802.11 HyperLan 2 */
2665  { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2666  { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2667  { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2668  { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2669  { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2670  { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2671  { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2672  { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2673  { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2674  { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2675 
2676  /* 802.11 UNII */
2677  { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2678  { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2679  { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2680  { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2681  { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2682  { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2683 
2684  /* MMAC(Japan)J52 ch 34,38,42,46 */
2685  { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2686  { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2687  { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2688  { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2689 };
2690 
2691 /*
2692  * RF value list for RF5225 & RF5325
2693  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2694  */
2695 static const struct rf_channel rf_vals_seq[] = {
2696  { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2697  { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2698  { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2699  { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2700  { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2701  { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2702  { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2703  { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2704  { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2705  { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2706  { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2707  { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2708  { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2709  { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2710 
2711  /* 802.11 UNI / HyperLan 2 */
2712  { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2713  { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2714  { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2715  { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2716  { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2717  { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2718  { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2719  { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2720 
2721  /* 802.11 HyperLan 2 */
2722  { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2723  { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2724  { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2725  { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2726  { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2727  { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2728  { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2729  { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2730  { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2731  { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2732 
2733  /* 802.11 UNII */
2734  { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2735  { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2736  { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2737  { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2738  { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2739  { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2740 
2741  /* MMAC(Japan)J52 ch 34,38,42,46 */
2742  { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2743  { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2744  { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2745  { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2746 };
2747 
2748 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2749 {
2750  struct hw_mode_spec *spec = &rt2x00dev->spec;
2751  struct channel_info *info;
2752  char *tx_power;
2753  unsigned int i;
2754 
2755  /*
2756  * Disable powersaving as default.
2757  */
2758  rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2759 
2760  /*
2761  * Initialize all hw fields.
2762  */
2763  rt2x00dev->hw->flags =
2768 
2769  SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2770  SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2771  rt2x00_eeprom_addr(rt2x00dev,
2773 
2774  /*
2775  * As rt61 has a global fallback table we cannot specify
2776  * more then one tx rate per frame but since the hw will
2777  * try several rates (based on the fallback table) we should
2778  * initialize max_report_rates to the maximum number of rates
2779  * we are going to try. Otherwise mac80211 will truncate our
2780  * reported tx rates and the rc algortihm will end up with
2781  * incorrect data.
2782  */
2783  rt2x00dev->hw->max_rates = 1;
2784  rt2x00dev->hw->max_report_rates = 7;
2785  rt2x00dev->hw->max_rate_tries = 1;
2786 
2787  /*
2788  * Initialize hw_mode information.
2789  */
2792 
2793  if (!test_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags)) {
2794  spec->num_channels = 14;
2795  spec->channels = rf_vals_noseq;
2796  } else {
2797  spec->num_channels = 14;
2798  spec->channels = rf_vals_seq;
2799  }
2800 
2801  if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
2803  spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2804  }
2805 
2806  /*
2807  * Create channel information array
2808  */
2809  info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
2810  if (!info)
2811  return -ENOMEM;
2812 
2813  spec->channels_info = info;
2814 
2815  tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2816  for (i = 0; i < 14; i++) {
2817  info[i].max_power = MAX_TXPOWER;
2818  info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2819  }
2820 
2821  if (spec->num_channels > 14) {
2822  tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2823  for (i = 14; i < spec->num_channels; i++) {
2824  info[i].max_power = MAX_TXPOWER;
2825  info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2826  }
2827  }
2828 
2829  return 0;
2830 }
2831 
2832 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2833 {
2834  int retval;
2835  u32 reg;
2836 
2837  /*
2838  * Disable power saving.
2839  */
2840  rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
2841 
2842  /*
2843  * Allocate eeprom data.
2844  */
2845  retval = rt61pci_validate_eeprom(rt2x00dev);
2846  if (retval)
2847  return retval;
2848 
2849  retval = rt61pci_init_eeprom(rt2x00dev);
2850  if (retval)
2851  return retval;
2852 
2853  /*
2854  * Enable rfkill polling by setting GPIO direction of the
2855  * rfkill switch GPIO pin correctly.
2856  */
2857  rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
2859  rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
2860 
2861  /*
2862  * Initialize hw specifications.
2863  */
2864  retval = rt61pci_probe_hw_mode(rt2x00dev);
2865  if (retval)
2866  return retval;
2867 
2868  /*
2869  * This device has multiple filters for control frames,
2870  * but has no a separate filter for PS Poll frames.
2871  */
2873 
2874  /*
2875  * This device requires firmware and DMA mapped skbs.
2876  */
2877  __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
2878  __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
2879  if (!modparam_nohwcrypt)
2882 
2883  /*
2884  * Set the rssi offset.
2885  */
2886  rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2887 
2888  return 0;
2889 }
2890 
2891 /*
2892  * IEEE80211 stack callback functions.
2893  */
2894 static int rt61pci_conf_tx(struct ieee80211_hw *hw,
2895  struct ieee80211_vif *vif, u16 queue_idx,
2896  const struct ieee80211_tx_queue_params *params)
2897 {
2898  struct rt2x00_dev *rt2x00dev = hw->priv;
2899  struct data_queue *queue;
2900  struct rt2x00_field32 field;
2901  int retval;
2902  u32 reg;
2903  u32 offset;
2904 
2905  /*
2906  * First pass the configuration through rt2x00lib, that will
2907  * update the queue settings and validate the input. After that
2908  * we are free to update the registers based on the value
2909  * in the queue parameter.
2910  */
2911  retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2912  if (retval)
2913  return retval;
2914 
2915  /*
2916  * We only need to perform additional register initialization
2917  * for WMM queues.
2918  */
2919  if (queue_idx >= 4)
2920  return 0;
2921 
2922  queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2923 
2924  /* Update WMM TXOP register */
2925  offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2926  field.bit_offset = (queue_idx & 1) * 16;
2927  field.bit_mask = 0xffff << field.bit_offset;
2928 
2929  rt2x00pci_register_read(rt2x00dev, offset, &reg);
2930  rt2x00_set_field32(&reg, field, queue->txop);
2931  rt2x00pci_register_write(rt2x00dev, offset, reg);
2932 
2933  /* Update WMM registers */
2934  field.bit_offset = queue_idx * 4;
2935  field.bit_mask = 0xf << field.bit_offset;
2936 
2937  rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
2938  rt2x00_set_field32(&reg, field, queue->aifs);
2939  rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2940 
2941  rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
2942  rt2x00_set_field32(&reg, field, queue->cw_min);
2943  rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2944 
2945  rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
2946  rt2x00_set_field32(&reg, field, queue->cw_max);
2947  rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2948 
2949  return 0;
2950 }
2951 
2952 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2953 {
2954  struct rt2x00_dev *rt2x00dev = hw->priv;
2955  u64 tsf;
2956  u32 reg;
2957 
2958  rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2959  tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2960  rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2962 
2963  return tsf;
2964 }
2965 
2966 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2967  .tx = rt2x00mac_tx,
2968  .start = rt2x00mac_start,
2969  .stop = rt2x00mac_stop,
2970  .add_interface = rt2x00mac_add_interface,
2971  .remove_interface = rt2x00mac_remove_interface,
2972  .config = rt2x00mac_config,
2973  .configure_filter = rt2x00mac_configure_filter,
2974  .set_key = rt2x00mac_set_key,
2975  .sw_scan_start = rt2x00mac_sw_scan_start,
2976  .sw_scan_complete = rt2x00mac_sw_scan_complete,
2977  .get_stats = rt2x00mac_get_stats,
2978  .bss_info_changed = rt2x00mac_bss_info_changed,
2979  .conf_tx = rt61pci_conf_tx,
2980  .get_tsf = rt61pci_get_tsf,
2981  .rfkill_poll = rt2x00mac_rfkill_poll,
2982  .flush = rt2x00mac_flush,
2983  .set_antenna = rt2x00mac_set_antenna,
2984  .get_antenna = rt2x00mac_get_antenna,
2985  .get_ringparam = rt2x00mac_get_ringparam,
2986  .tx_frames_pending = rt2x00mac_tx_frames_pending,
2987 };
2988 
2989 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2990  .irq_handler = rt61pci_interrupt,
2991  .txstatus_tasklet = rt61pci_txstatus_tasklet,
2992  .tbtt_tasklet = rt61pci_tbtt_tasklet,
2993  .rxdone_tasklet = rt61pci_rxdone_tasklet,
2994  .autowake_tasklet = rt61pci_autowake_tasklet,
2995  .probe_hw = rt61pci_probe_hw,
2996  .get_firmware_name = rt61pci_get_firmware_name,
2997  .check_firmware = rt61pci_check_firmware,
2998  .load_firmware = rt61pci_load_firmware,
2999  .initialize = rt2x00pci_initialize,
3000  .uninitialize = rt2x00pci_uninitialize,
3001  .get_entry_state = rt61pci_get_entry_state,
3002  .clear_entry = rt61pci_clear_entry,
3003  .set_device_state = rt61pci_set_device_state,
3004  .rfkill_poll = rt61pci_rfkill_poll,
3005  .link_stats = rt61pci_link_stats,
3006  .reset_tuner = rt61pci_reset_tuner,
3007  .link_tuner = rt61pci_link_tuner,
3008  .start_queue = rt61pci_start_queue,
3009  .kick_queue = rt61pci_kick_queue,
3010  .stop_queue = rt61pci_stop_queue,
3011  .flush_queue = rt2x00pci_flush_queue,
3012  .write_tx_desc = rt61pci_write_tx_desc,
3013  .write_beacon = rt61pci_write_beacon,
3014  .clear_beacon = rt61pci_clear_beacon,
3015  .fill_rxdone = rt61pci_fill_rxdone,
3016  .config_shared_key = rt61pci_config_shared_key,
3017  .config_pairwise_key = rt61pci_config_pairwise_key,
3018  .config_filter = rt61pci_config_filter,
3019  .config_intf = rt61pci_config_intf,
3020  .config_erp = rt61pci_config_erp,
3021  .config_ant = rt61pci_config_ant,
3022  .config = rt61pci_config,
3023 };
3024 
3025 static const struct data_queue_desc rt61pci_queue_rx = {
3026  .entry_num = 32,
3027  .data_size = DATA_FRAME_SIZE,
3028  .desc_size = RXD_DESC_SIZE,
3029  .priv_size = sizeof(struct queue_entry_priv_pci),
3030 };
3031 
3032 static const struct data_queue_desc rt61pci_queue_tx = {
3033  .entry_num = 32,
3034  .data_size = DATA_FRAME_SIZE,
3035  .desc_size = TXD_DESC_SIZE,
3036  .priv_size = sizeof(struct queue_entry_priv_pci),
3037 };
3038 
3039 static const struct data_queue_desc rt61pci_queue_bcn = {
3040  .entry_num = 4,
3041  .data_size = 0, /* No DMA required for beacons */
3042  .desc_size = TXINFO_SIZE,
3043  .priv_size = sizeof(struct queue_entry_priv_pci),
3044 };
3045 
3046 static const struct rt2x00_ops rt61pci_ops = {
3047  .name = KBUILD_MODNAME,
3048  .max_ap_intf = 4,
3049  .eeprom_size = EEPROM_SIZE,
3050  .rf_size = RF_SIZE,
3051  .tx_queues = NUM_TX_QUEUES,
3052  .extra_tx_headroom = 0,
3053  .rx = &rt61pci_queue_rx,
3054  .tx = &rt61pci_queue_tx,
3055  .bcn = &rt61pci_queue_bcn,
3056  .lib = &rt61pci_rt2x00_ops,
3057  .hw = &rt61pci_mac80211_ops,
3058 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
3059  .debugfs = &rt61pci_rt2x00debug,
3060 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
3061 };
3062 
3063 /*
3064  * RT61pci module information.
3065  */
3066 static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
3067  /* RT2561s */
3068  { PCI_DEVICE(0x1814, 0x0301) },
3069  /* RT2561 v2 */
3070  { PCI_DEVICE(0x1814, 0x0302) },
3071  /* RT2661 */
3072  { PCI_DEVICE(0x1814, 0x0401) },
3073  { 0, }
3074 };
3075 
3078 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
3079 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
3080  "PCI & PCMCIA chipset based cards");
3081 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
3085 MODULE_LICENSE("GPL");
3086 
3087 static int rt61pci_probe(struct pci_dev *pci_dev,
3088  const struct pci_device_id *id)
3089 {
3090  return rt2x00pci_probe(pci_dev, &rt61pci_ops);
3091 }
3092 
3093 static struct pci_driver rt61pci_driver = {
3094  .name = KBUILD_MODNAME,
3095  .id_table = rt61pci_device_table,
3096  .probe = rt61pci_probe,
3097  .remove = __devexit_p(rt2x00pci_remove),
3098  .suspend = rt2x00pci_suspend,
3099  .resume = rt2x00pci_resume,
3100 };
3101 
3102 module_pci_driver(rt61pci_driver);