31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/slab.h>
34 #include <linux/pci.h>
44 static bool modparam_nohwcrypt =
false;
59 #define WAIT_FOR_BBP(__dev, __reg) \
60 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
61 #define WAIT_FOR_RF(__dev, __reg) \
62 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
63 #define WAIT_FOR_MCU(__dev, __reg) \
64 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
65 H2M_MAILBOX_CSR_OWNER, (__reg))
67 static void rt61pci_bbp_write(
struct rt2x00_dev *rt2x00dev,
85 rt2x00pci_register_write(rt2x00dev,
PHY_CSR3, reg);
91 static void rt61pci_bbp_read(
struct rt2x00_dev *rt2x00dev,
112 rt2x00pci_register_write(rt2x00dev,
PHY_CSR3, reg);
122 static void rt61pci_rf_write(
struct rt2x00_dev *rt2x00dev,
123 const unsigned int word,
const u32 value)
140 rt2x00pci_register_write(rt2x00dev,
PHY_CSR4, reg);
141 rt2x00_rf_write(rt2x00dev, word, value);
147 static void rt61pci_mcu_request(
struct rt2x00_dev *rt2x00dev,
181 rt2x00pci_register_read(rt2x00dev,
E2PROM_CSR, ®);
203 rt2x00pci_register_write(rt2x00dev,
E2PROM_CSR, reg);
206 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
207 static const struct rt2x00debug rt61pci_rt2x00debug = {
210 .read = rt2x00pci_register_read,
211 .write = rt2x00pci_register_write,
214 .word_size =
sizeof(
u32),
218 .read = rt2x00_eeprom_read,
219 .write = rt2x00_eeprom_write,
221 .word_size =
sizeof(
u16),
225 .read = rt61pci_bbp_read,
226 .write = rt61pci_bbp_write,
228 .word_size =
sizeof(
u8),
232 .read = rt2x00_rf_read,
233 .write = rt61pci_rf_write,
235 .word_size =
sizeof(
u32),
241 static int rt61pci_rfkill_poll(
struct rt2x00_dev *rt2x00dev)
245 rt2x00pci_register_read(rt2x00dev,
MAC_CSR13, ®);
249 #ifdef CONFIG_RT2X00_LIB_LEDS
250 static void rt61pci_brightness_set(
struct led_classdev *led_cdev,
256 unsigned int a_mode =
258 unsigned int bg_mode =
288 static int rt61pci_blink_set(
struct led_classdev *led_cdev,
289 unsigned long *delay_on,
290 unsigned long *delay_off)
304 static void rt61pci_init_led(
struct rt2x00_dev *rt2x00dev,
310 led->
led_dev.brightness_set = rt61pci_brightness_set;
311 led->
led_dev.blink_set = rt61pci_blink_set;
319 static int rt61pci_config_shared_key(
struct rt2x00_dev *rt2x00dev,
339 mask = (0xf << crypto->
bssidx);
341 rt2x00pci_register_read(rt2x00dev,
SEC_CSR0, ®);
344 if (reg && reg == mask)
353 sizeof(key_entry.key));
355 sizeof(key_entry.tx_mic));
357 sizeof(key_entry.rx_mic));
360 rt2x00pci_register_multiwrite(rt2x00dev, reg,
361 &key_entry,
sizeof(key_entry));
374 rt2x00pci_register_read(rt2x00dev,
SEC_CSR1, ®);
376 rt2x00pci_register_write(rt2x00dev,
SEC_CSR1, reg);
381 rt2x00pci_register_read(rt2x00dev,
SEC_CSR5, ®);
383 rt2x00pci_register_write(rt2x00dev,
SEC_CSR5, reg);
406 rt2x00pci_register_read(rt2x00dev,
SEC_CSR0, ®);
411 rt2x00pci_register_write(rt2x00dev,
SEC_CSR0, reg);
416 static int rt61pci_config_pairwise_key(
struct rt2x00_dev *rt2x00dev,
435 rt2x00pci_register_read(rt2x00dev,
SEC_CSR2, ®);
436 if (reg && reg == ~0) {
438 rt2x00pci_register_read(rt2x00dev,
SEC_CSR3, ®);
439 if (reg && reg == ~0)
449 sizeof(key_entry.key));
451 sizeof(key_entry.tx_mic));
453 sizeof(key_entry.rx_mic));
455 memset(&addr_entry, 0,
sizeof(addr_entry));
457 addr_entry.cipher = crypto->
cipher;
460 rt2x00pci_register_multiwrite(rt2x00dev, reg,
461 &key_entry,
sizeof(key_entry));
464 rt2x00pci_register_multiwrite(rt2x00dev, reg,
465 &addr_entry,
sizeof(addr_entry));
472 rt2x00pci_register_read(rt2x00dev,
SEC_CSR4, ®);
473 reg |= (1 << crypto->
bssidx);
474 rt2x00pci_register_write(rt2x00dev,
SEC_CSR4, reg);
497 rt2x00pci_register_read(rt2x00dev,
SEC_CSR2, ®);
502 rt2x00pci_register_write(rt2x00dev,
SEC_CSR2, reg);
506 rt2x00pci_register_read(rt2x00dev,
SEC_CSR3, ®);
511 rt2x00pci_register_write(rt2x00dev,
SEC_CSR3, reg);
517 static void rt61pci_config_filter(
struct rt2x00_dev *rt2x00dev,
518 const unsigned int filter_flags)
528 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR0, ®);
546 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR0, reg);
549 static void rt61pci_config_intf(
struct rt2x00_dev *rt2x00dev,
552 const unsigned int flags)
560 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR9, ®);
562 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR9, reg);
570 rt2x00pci_register_multiwrite(rt2x00dev,
MAC_CSR2,
571 conf->
mac,
sizeof(conf->
mac));
579 rt2x00pci_register_multiwrite(rt2x00dev,
MAC_CSR4,
584 static void rt61pci_config_erp(
struct rt2x00_dev *rt2x00dev,
590 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR0, ®);
593 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR0, reg);
596 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR4, ®);
600 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR4, reg);
604 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR5,
608 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR9, ®);
611 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR9, reg);
615 rt2x00pci_register_read(rt2x00dev,
MAC_CSR9, ®);
617 rt2x00pci_register_write(rt2x00dev,
MAC_CSR9, reg);
619 rt2x00pci_register_read(rt2x00dev,
MAC_CSR8, ®);
623 rt2x00pci_register_write(rt2x00dev,
MAC_CSR8, reg);
627 static void rt61pci_config_antenna_5x(
struct rt2x00_dev *rt2x00dev,
634 rt61pci_bbp_read(rt2x00dev, 3, &r3);
635 rt61pci_bbp_read(rt2x00dev, 4, &r4);
636 rt61pci_bbp_read(rt2x00dev, 77, &r77);
668 rt61pci_bbp_write(rt2x00dev, 77, r77);
669 rt61pci_bbp_write(rt2x00dev, 3, r3);
670 rt61pci_bbp_write(rt2x00dev, 4, r4);
673 static void rt61pci_config_antenna_2x(
struct rt2x00_dev *rt2x00dev,
680 rt61pci_bbp_read(rt2x00dev, 3, &r3);
681 rt61pci_bbp_read(rt2x00dev, 4, &r4);
682 rt61pci_bbp_read(rt2x00dev, 77, &r77);
706 rt61pci_bbp_write(rt2x00dev, 77, r77);
707 rt61pci_bbp_write(rt2x00dev, 3, r3);
708 rt61pci_bbp_write(rt2x00dev, 4, r4);
711 static void rt61pci_config_antenna_2529_rx(
struct rt2x00_dev *rt2x00dev,
712 const int p1,
const int p2)
716 rt2x00pci_register_read(rt2x00dev,
MAC_CSR13, ®);
724 rt2x00pci_register_write(rt2x00dev,
MAC_CSR13, reg);
727 static void rt61pci_config_antenna_2529(
struct rt2x00_dev *rt2x00dev,
734 rt61pci_bbp_read(rt2x00dev, 3, &r3);
735 rt61pci_bbp_read(rt2x00dev, 4, &r4);
736 rt61pci_bbp_read(rt2x00dev, 77, &r77);
745 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
757 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
761 rt61pci_bbp_write(rt2x00dev, 77, r77);
762 rt61pci_bbp_write(rt2x00dev, 3, r3);
763 rt61pci_bbp_write(rt2x00dev, 4, r4);
775 static const struct antenna_sel antenna_sel_a[] = {
776 { 96, { 0x58, 0x78 } },
777 { 104, { 0x38, 0x48 } },
778 { 75, { 0xfe, 0x80 } },
779 { 86, { 0xfe, 0x80 } },
780 { 88, { 0xfe, 0x80 } },
781 { 35, { 0x60, 0x60 } },
782 { 97, { 0x58, 0x58 } },
783 { 98, { 0x58, 0x58 } },
786 static const struct antenna_sel antenna_sel_bg[] = {
787 { 96, { 0x48, 0x68 } },
788 { 104, { 0x2c, 0x3c } },
789 { 75, { 0xfe, 0x80 } },
790 { 86, { 0xfe, 0x80 } },
791 { 88, { 0xfe, 0x80 } },
792 { 35, { 0x50, 0x50 } },
793 { 97, { 0x48, 0x48 } },
794 { 98, { 0x48, 0x48 } },
797 static void rt61pci_config_ant(
struct rt2x00_dev *rt2x00dev,
816 sel = antenna_sel_bg;
820 for (i = 0; i <
ARRAY_SIZE(antenna_sel_a); i++)
821 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
823 rt2x00pci_register_read(rt2x00dev,
PHY_CSR0, ®);
830 rt2x00pci_register_write(rt2x00dev,
PHY_CSR0, reg);
832 if (rt2x00_rf(rt2x00dev,
RF5225) || rt2x00_rf(rt2x00dev,
RF5325))
833 rt61pci_config_antenna_5x(rt2x00dev, ant);
834 else if (rt2x00_rf(rt2x00dev,
RF2527))
835 rt61pci_config_antenna_2x(rt2x00dev, ant);
836 else if (rt2x00_rf(rt2x00dev,
RF2529)) {
838 rt61pci_config_antenna_2x(rt2x00dev, ant);
840 rt61pci_config_antenna_2529(rt2x00dev, ant);
844 static void rt61pci_config_lna_gain(
struct rt2x00_dev *rt2x00dev,
867 static void rt61pci_config_channel(
struct rt2x00_dev *rt2x00dev,
877 smart = !(rt2x00_rf(rt2x00dev,
RF5225) || rt2x00_rf(rt2x00dev,
RF2527));
879 rt61pci_bbp_read(rt2x00dev, 3, &r3);
881 rt61pci_bbp_write(rt2x00dev, 3, r3);
886 else if (txpower < MIN_TXPOWER && txpower >= (
MIN_TXPOWER - r94))
888 rt61pci_bbp_write(rt2x00dev, 94, r94);
890 rt61pci_rf_write(rt2x00dev, 1, rf->
rf1);
891 rt61pci_rf_write(rt2x00dev, 2, rf->
rf2);
892 rt61pci_rf_write(rt2x00dev, 3, rf->
rf3 & ~0x00000004);
893 rt61pci_rf_write(rt2x00dev, 4, rf->
rf4);
897 rt61pci_rf_write(rt2x00dev, 1, rf->
rf1);
898 rt61pci_rf_write(rt2x00dev, 2, rf->
rf2);
899 rt61pci_rf_write(rt2x00dev, 3, rf->
rf3 | 0x00000004);
900 rt61pci_rf_write(rt2x00dev, 4, rf->
rf4);
904 rt61pci_rf_write(rt2x00dev, 1, rf->
rf1);
905 rt61pci_rf_write(rt2x00dev, 2, rf->
rf2);
906 rt61pci_rf_write(rt2x00dev, 3, rf->
rf3 & ~0x00000004);
907 rt61pci_rf_write(rt2x00dev, 4, rf->
rf4);
912 static void rt61pci_config_txpower(
struct rt2x00_dev *rt2x00dev,
917 rt2x00_rf_read(rt2x00dev, 1, &rf.
rf1);
918 rt2x00_rf_read(rt2x00dev, 2, &rf.
rf2);
919 rt2x00_rf_read(rt2x00dev, 3, &rf.
rf3);
920 rt2x00_rf_read(rt2x00dev, 4, &rf.
rf4);
922 rt61pci_config_channel(rt2x00dev, &rf, txpower);
925 static void rt61pci_config_retry_limit(
struct rt2x00_dev *rt2x00dev,
930 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR4, ®);
935 libconf->
conf->long_frame_max_tx_count);
937 libconf->
conf->short_frame_max_tx_count);
938 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR4, reg);
941 static void rt61pci_config_ps(
struct rt2x00_dev *rt2x00dev,
950 rt2x00pci_register_read(rt2x00dev,
MAC_CSR11, ®);
954 libconf->
conf->listen_interval - 1);
959 rt2x00pci_register_write(rt2x00dev,
MAC_CSR11, reg);
962 rt2x00pci_register_write(rt2x00dev,
MAC_CSR11, reg);
965 rt2x00pci_register_write(rt2x00dev,
IO_CNTL_CSR, 0x0000001c);
966 rt2x00pci_register_write(rt2x00dev,
PCI_USEC_CSR, 0x00000060);
968 rt61pci_mcu_request(rt2x00dev,
MCU_SLEEP, 0xff, 0, 0);
970 rt2x00pci_register_read(rt2x00dev,
MAC_CSR11, ®);
975 rt2x00pci_register_write(rt2x00dev,
MAC_CSR11, reg);
978 rt2x00pci_register_write(rt2x00dev,
IO_CNTL_CSR, 0x00000018);
979 rt2x00pci_register_write(rt2x00dev,
PCI_USEC_CSR, 0x00000020);
981 rt61pci_mcu_request(rt2x00dev,
MCU_WAKEUP, 0xff, 0, 0);
985 static void rt61pci_config(
struct rt2x00_dev *rt2x00dev,
987 const unsigned int flags)
990 rt61pci_config_lna_gain(rt2x00dev, libconf);
993 rt61pci_config_channel(rt2x00dev, &libconf->
rf,
994 libconf->
conf->power_level);
996 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
997 rt61pci_config_txpower(rt2x00dev, libconf->
conf->power_level);
999 rt61pci_config_retry_limit(rt2x00dev, libconf);
1001 rt61pci_config_ps(rt2x00dev, libconf);
1007 static void rt61pci_link_stats(
struct rt2x00_dev *rt2x00dev,
1015 rt2x00pci_register_read(rt2x00dev,
STA_CSR0, ®);
1021 rt2x00pci_register_read(rt2x00dev,
STA_CSR1, ®);
1025 static inline void rt61pci_set_vgc(
struct rt2x00_dev *rt2x00dev,
1029 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
1035 static void rt61pci_reset_tuner(
struct rt2x00_dev *rt2x00dev,
1038 rt61pci_set_vgc(rt2x00dev, qual, 0x20);
1041 static void rt61pci_link_tuner(
struct rt2x00_dev *rt2x00dev,
1071 goto dynamic_cca_tune;
1076 if (qual->
rssi >= -35) {
1077 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
1084 if (qual->
rssi >= -58) {
1085 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1092 if (qual->
rssi >= -66) {
1093 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
1100 if (qual->
rssi >= -74) {
1101 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1109 up_bound -= 2 * (-74 - qual->
rssi);
1110 if (low_bound > up_bound)
1111 up_bound = low_bound;
1114 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1125 rt61pci_set_vgc(rt2x00dev, qual, ++qual->
vgc_level);
1127 rt61pci_set_vgc(rt2x00dev, qual, --qual->
vgc_level);
1138 switch (queue->
qid) {
1140 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR0, ®);
1142 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR0, reg);
1145 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR9, ®);
1149 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR9, reg);
1156 static void rt61pci_kick_queue(
struct data_queue *queue)
1161 switch (queue->
qid) {
1163 rt2x00pci_register_read(rt2x00dev,
TX_CNTL_CSR, ®);
1165 rt2x00pci_register_write(rt2x00dev,
TX_CNTL_CSR, reg);
1168 rt2x00pci_register_read(rt2x00dev,
TX_CNTL_CSR, ®);
1170 rt2x00pci_register_write(rt2x00dev,
TX_CNTL_CSR, reg);
1173 rt2x00pci_register_read(rt2x00dev,
TX_CNTL_CSR, ®);
1175 rt2x00pci_register_write(rt2x00dev,
TX_CNTL_CSR, reg);
1178 rt2x00pci_register_read(rt2x00dev,
TX_CNTL_CSR, ®);
1180 rt2x00pci_register_write(rt2x00dev,
TX_CNTL_CSR, reg);
1187 static void rt61pci_stop_queue(
struct data_queue *queue)
1192 switch (queue->
qid) {
1194 rt2x00pci_register_read(rt2x00dev,
TX_CNTL_CSR, ®);
1196 rt2x00pci_register_write(rt2x00dev,
TX_CNTL_CSR, reg);
1199 rt2x00pci_register_read(rt2x00dev,
TX_CNTL_CSR, ®);
1201 rt2x00pci_register_write(rt2x00dev,
TX_CNTL_CSR, reg);
1204 rt2x00pci_register_read(rt2x00dev,
TX_CNTL_CSR, ®);
1206 rt2x00pci_register_write(rt2x00dev,
TX_CNTL_CSR, reg);
1209 rt2x00pci_register_read(rt2x00dev,
TX_CNTL_CSR, ®);
1211 rt2x00pci_register_write(rt2x00dev,
TX_CNTL_CSR, reg);
1214 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR0, ®);
1216 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR0, reg);
1219 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR9, ®);
1223 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR9, reg);
1238 static char *rt61pci_get_firmware_name(
struct rt2x00_dev *rt2x00dev)
1262 static int rt61pci_check_firmware(
struct rt2x00_dev *rt2x00dev,
1263 const u8 *
data,
const size_t len)
1279 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1285 crc = crc_itu_t_byte(crc, 0);
1286 crc = crc_itu_t_byte(crc, 0);
1291 static int rt61pci_load_firmware(
struct rt2x00_dev *rt2x00dev,
1292 const u8 *data,
const size_t len)
1300 for (i = 0; i < 100; i++) {
1301 rt2x00pci_register_read(rt2x00dev,
MAC_CSR0, ®);
1308 ERROR(rt2x00dev,
"Unstable hardware.\n");
1317 rt2x00pci_register_write(rt2x00dev,
MCU_CNTL_CSR, reg);
1328 rt2x00pci_register_write(rt2x00dev,
MCU_CNTL_CSR, reg);
1334 rt2x00pci_register_write(rt2x00dev,
MCU_CNTL_CSR, reg);
1337 rt2x00pci_register_write(rt2x00dev,
MCU_CNTL_CSR, reg);
1339 for (i = 0; i < 100; i++) {
1340 rt2x00pci_register_read(rt2x00dev,
MCU_CNTL_CSR, ®);
1347 ERROR(rt2x00dev,
"MCU Control register not ready.\n");
1362 rt2x00pci_register_write(rt2x00dev,
MAC_CSR1, reg);
1364 rt2x00pci_register_read(rt2x00dev,
MAC_CSR1, ®);
1367 rt2x00pci_register_write(rt2x00dev,
MAC_CSR1, reg);
1369 rt2x00pci_register_read(rt2x00dev,
MAC_CSR1, ®);
1371 rt2x00pci_register_write(rt2x00dev,
MAC_CSR1, reg);
1379 static bool rt61pci_get_entry_state(
struct queue_entry *
entry)
1384 if (entry->queue->qid ==
QID_RX) {
1385 rt2x00_desc_read(entry_priv->
desc, 0, &word);
1389 rt2x00_desc_read(entry_priv->
desc, 0, &word);
1396 static void rt61pci_clear_entry(
struct queue_entry *entry)
1402 if (entry->queue->qid ==
QID_RX) {
1403 rt2x00_desc_read(entry_priv->
desc, 5, &word);
1406 rt2x00_desc_write(entry_priv->
desc, 5, word);
1408 rt2x00_desc_read(entry_priv->
desc, 0, &word);
1410 rt2x00_desc_write(entry_priv->
desc, 0, word);
1412 rt2x00_desc_read(entry_priv->
desc, 0, &word);
1415 rt2x00_desc_write(entry_priv->
desc, 0, word);
1419 static int rt61pci_init_queues(
struct rt2x00_dev *rt2x00dev)
1427 rt2x00pci_register_read(rt2x00dev,
TX_RING_CSR0, ®);
1429 rt2x00dev->
tx[0].limit);
1431 rt2x00dev->
tx[1].limit);
1433 rt2x00dev->
tx[2].limit);
1435 rt2x00dev->
tx[3].limit);
1436 rt2x00pci_register_write(rt2x00dev,
TX_RING_CSR0, reg);
1438 rt2x00pci_register_read(rt2x00dev,
TX_RING_CSR1, ®);
1440 rt2x00dev->
tx[0].desc_size / 4);
1441 rt2x00pci_register_write(rt2x00dev,
TX_RING_CSR1, reg);
1443 entry_priv = rt2x00dev->
tx[0].entries[0].priv_data;
1444 rt2x00pci_register_read(rt2x00dev,
AC0_BASE_CSR, ®);
1447 rt2x00pci_register_write(rt2x00dev,
AC0_BASE_CSR, reg);
1449 entry_priv = rt2x00dev->
tx[1].entries[0].priv_data;
1450 rt2x00pci_register_read(rt2x00dev,
AC1_BASE_CSR, ®);
1453 rt2x00pci_register_write(rt2x00dev,
AC1_BASE_CSR, reg);
1455 entry_priv = rt2x00dev->
tx[2].entries[0].priv_data;
1456 rt2x00pci_register_read(rt2x00dev,
AC2_BASE_CSR, ®);
1459 rt2x00pci_register_write(rt2x00dev,
AC2_BASE_CSR, reg);
1461 entry_priv = rt2x00dev->
tx[3].entries[0].priv_data;
1462 rt2x00pci_register_read(rt2x00dev,
AC3_BASE_CSR, ®);
1465 rt2x00pci_register_write(rt2x00dev,
AC3_BASE_CSR, reg);
1467 rt2x00pci_register_read(rt2x00dev,
RX_RING_CSR, ®);
1470 rt2x00dev->
rx->desc_size / 4);
1472 rt2x00pci_register_write(rt2x00dev,
RX_RING_CSR, reg);
1474 entry_priv = rt2x00dev->
rx->entries[0].priv_data;
1475 rt2x00pci_register_read(rt2x00dev,
RX_BASE_CSR, ®);
1478 rt2x00pci_register_write(rt2x00dev,
RX_BASE_CSR, reg);
1494 rt2x00pci_register_read(rt2x00dev,
RX_CNTL_CSR, ®);
1496 rt2x00pci_register_write(rt2x00dev,
RX_CNTL_CSR, reg);
1501 static int rt61pci_init_registers(
struct rt2x00_dev *rt2x00dev)
1505 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR0, ®);
1509 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR0, reg);
1511 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR1, ®);
1520 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR1, reg);
1525 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR2, ®);
1534 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR2, reg);
1539 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR3, ®);
1546 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR3, reg);
1548 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR7, ®);
1553 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR7, reg);
1555 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR8, ®);
1560 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR8, reg);
1562 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR9, ®);
1569 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR9, reg);
1571 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR15, 0x0000000f);
1573 rt2x00pci_register_write(rt2x00dev,
MAC_CSR6, 0x00000fff);
1575 rt2x00pci_register_read(rt2x00dev,
MAC_CSR9, ®);
1577 rt2x00pci_register_write(rt2x00dev,
MAC_CSR9, reg);
1579 rt2x00pci_register_write(rt2x00dev,
MAC_CSR10, 0x0000071c);
1581 if (rt2x00dev->
ops->lib->set_device_state(rt2x00dev,
STATE_AWAKE))
1584 rt2x00pci_register_write(rt2x00dev,
MAC_CSR13, 0x0000e000);
1590 rt2x00pci_register_write(rt2x00dev,
SEC_CSR0, 0x00000000);
1591 rt2x00pci_register_write(rt2x00dev,
SEC_CSR1, 0x00000000);
1592 rt2x00pci_register_write(rt2x00dev,
SEC_CSR5, 0x00000000);
1594 rt2x00pci_register_write(rt2x00dev,
PHY_CSR1, 0x000023b0);
1595 rt2x00pci_register_write(rt2x00dev,
PHY_CSR5, 0x060a100c);
1596 rt2x00pci_register_write(rt2x00dev,
PHY_CSR6, 0x00080606);
1597 rt2x00pci_register_write(rt2x00dev,
PHY_CSR7, 0x00000a08);
1599 rt2x00pci_register_write(rt2x00dev,
PCI_CFG_CSR, 0x28ca4404);
1601 rt2x00pci_register_write(rt2x00dev,
TEST_MODE_CSR, 0x00000200);
1621 rt2x00pci_register_read(rt2x00dev,
STA_CSR0, ®);
1622 rt2x00pci_register_read(rt2x00dev,
STA_CSR1, ®);
1623 rt2x00pci_register_read(rt2x00dev,
STA_CSR2, ®);
1628 rt2x00pci_register_read(rt2x00dev,
MAC_CSR1, ®);
1631 rt2x00pci_register_write(rt2x00dev,
MAC_CSR1, reg);
1633 rt2x00pci_register_read(rt2x00dev,
MAC_CSR1, ®);
1636 rt2x00pci_register_write(rt2x00dev,
MAC_CSR1, reg);
1638 rt2x00pci_register_read(rt2x00dev,
MAC_CSR1, ®);
1640 rt2x00pci_register_write(rt2x00dev,
MAC_CSR1, reg);
1645 static int rt61pci_wait_bbp_ready(
struct rt2x00_dev *rt2x00dev)
1651 rt61pci_bbp_read(rt2x00dev, 0, &value);
1652 if ((value != 0xff) && (value != 0x00))
1657 ERROR(rt2x00dev,
"BBP register access failed, aborting.\n");
1661 static int rt61pci_init_bbp(
struct rt2x00_dev *rt2x00dev)
1668 if (
unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1671 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1672 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1673 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1674 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1675 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1676 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1677 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1678 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1679 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1680 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1681 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1682 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1683 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1684 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1685 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1686 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1687 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1688 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1689 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1690 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1691 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1692 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1693 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1694 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1699 if (eeprom != 0xffff && eeprom != 0x0000) {
1702 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1712 static void rt61pci_toggle_irq(
struct rt2x00_dev *rt2x00dev,
1717 unsigned long flags;
1737 rt2x00pci_register_read(rt2x00dev,
INT_MASK_CSR, ®);
1743 rt2x00pci_register_write(rt2x00dev,
INT_MASK_CSR, reg);
1757 spin_unlock_irqrestore(&rt2x00dev->
irqmask_lock, flags);
1770 static int rt61pci_enable_radio(
struct rt2x00_dev *rt2x00dev)
1777 if (
unlikely(rt61pci_init_queues(rt2x00dev) ||
1778 rt61pci_init_registers(rt2x00dev) ||
1779 rt61pci_init_bbp(rt2x00dev)))
1785 rt2x00pci_register_read(rt2x00dev,
RX_CNTL_CSR, ®);
1787 rt2x00pci_register_write(rt2x00dev,
RX_CNTL_CSR, reg);
1792 static void rt61pci_disable_radio(
struct rt2x00_dev *rt2x00dev)
1797 rt2x00pci_register_write(rt2x00dev,
MAC_CSR10, 0x00001818);
1808 rt2x00pci_register_read(rt2x00dev,
MAC_CSR12, ®);
1811 rt2x00pci_register_write(rt2x00dev,
MAC_CSR12, reg);
1819 rt2x00pci_register_read(rt2x00dev,
MAC_CSR12, ®2);
1821 if (state == !put_to_sleep)
1823 rt2x00pci_register_write(rt2x00dev,
MAC_CSR12, reg);
1830 static int rt61pci_set_device_state(
struct rt2x00_dev *rt2x00dev,
1837 retval = rt61pci_enable_radio(rt2x00dev);
1840 rt61pci_disable_radio(rt2x00dev);
1844 rt61pci_toggle_irq(rt2x00dev, state);
1850 retval = rt61pci_set_state(rt2x00dev, state);
1858 ERROR(rt2x00dev,
"Device failed to enter state %d (%d).\n",
1867 static void rt61pci_write_tx_desc(
struct queue_entry *entry,
1878 rt2x00_desc_read(txd, 1, &word);
1887 rt2x00_desc_write(txd, 1, word);
1889 rt2x00_desc_read(txd, 2, &word);
1893 txdesc->
u.
plcp.length_low);
1895 txdesc->
u.
plcp.length_high);
1896 rt2x00_desc_write(txd, 2, word);
1899 _rt2x00_desc_write(txd, 3, skbdesc->
iv[0]);
1900 _rt2x00_desc_write(txd, 4, skbdesc->
iv[1]);
1903 rt2x00_desc_read(txd, 5, &word);
1906 skbdesc->
entry->entry_idx);
1910 rt2x00_desc_write(txd, 5, word);
1913 rt2x00_desc_read(txd, 6, &word);
1916 rt2x00_desc_write(txd, 6, word);
1918 rt2x00_desc_read(txd, 11, &word);
1921 rt2x00_desc_write(txd, 11, word);
1929 rt2x00_desc_read(txd, 0, &word);
1952 rt2x00_desc_write(txd, 0, word);
1957 skbdesc->
desc = txd;
1965 static void rt61pci_write_beacon(
struct queue_entry *entry,
1968 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1970 unsigned int beacon_base;
1971 unsigned int padding_len;
1978 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR9, ®);
1981 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR9, reg);
1986 rt61pci_write_tx_desc(entry, txdesc);
1996 padding_len =
roundup(entry->skb->len, 4) - entry->skb->len;
1997 if (padding_len &&
skb_pad(entry->skb, padding_len)) {
1998 ERROR(rt2x00dev,
"Failure padding beacon, aborting\n");
2001 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR9, orig_reg);
2006 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
2008 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base +
TXINFO_SIZE,
2010 entry->skb->len + padding_len);
2018 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR10, 0x00001008);
2021 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR9, reg);
2030 static void rt61pci_clear_beacon(
struct queue_entry *entry)
2032 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2039 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR9, ®);
2041 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR9, reg);
2046 rt2x00pci_register_write(rt2x00dev,
2053 rt2x00pci_register_write(rt2x00dev,
TXRX_CSR9, reg);
2059 static int rt61pci_agc_to_rssi(
struct rt2x00_dev *rt2x00dev,
int rxd_w1)
2080 if (lna == 3 || lna == 2)
2087 static void rt61pci_fill_rxdone(
struct queue_entry *entry,
2090 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2095 rt2x00_desc_read(entry_priv->
desc, 0, &word0);
2096 rt2x00_desc_read(entry_priv->
desc, 1, &word1);
2105 _rt2x00_desc_read(entry_priv->
desc, 2, &rxdesc->
iv[0]);
2106 _rt2x00_desc_read(entry_priv->
desc, 3, &rxdesc->
iv[1]);
2109 _rt2x00_desc_read(entry_priv->
desc, 4, &rxdesc->
icv);
2138 rxdesc->
rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
2152 static void rt61pci_txdone(
struct rt2x00_dev *rt2x00dev)
2155 struct queue_entry *
entry;
2156 struct queue_entry *entry_done;
2174 for (i = 0; i < rt2x00dev->
ops->tx->entry_num; i++) {
2175 rt2x00pci_register_read(rt2x00dev,
STA_CSR4, ®);
2184 queue = rt2x00queue_get_tx_queue(rt2x00dev, type);
2197 entry_priv = entry->priv_data;
2198 rt2x00_desc_read(entry_priv->
desc, 0, &word);
2205 while (entry != entry_done) {
2210 "TX status report missed for entry %d\n",
2211 entry_done->entry_idx);
2244 static void rt61pci_wakeup(
struct rt2x00_dev *rt2x00dev)
2251 static inline void rt61pci_enable_interrupt(
struct rt2x00_dev *rt2x00dev,
2262 rt2x00pci_register_read(rt2x00dev,
INT_MASK_CSR, ®);
2264 rt2x00pci_register_write(rt2x00dev,
INT_MASK_CSR, reg);
2269 static void rt61pci_enable_mcu_interrupt(
struct rt2x00_dev *rt2x00dev,
2287 static void rt61pci_txstatus_tasklet(
unsigned long data)
2290 rt61pci_txdone(rt2x00dev);
2295 static void rt61pci_tbtt_tasklet(
unsigned long data)
2303 static void rt61pci_rxdone_tasklet(
unsigned long data)
2312 static void rt61pci_autowake_tasklet(
unsigned long data)
2315 rt61pci_wakeup(rt2x00dev);
2316 rt2x00pci_register_write(rt2x00dev,
2322 static irqreturn_t rt61pci_interrupt(
int irq,
void *dev_instance)
2325 u32 reg_mcu, mask_mcu;
2338 if (!reg && !reg_mcu)
2373 rt2x00pci_register_read(rt2x00dev,
INT_MASK_CSR, ®);
2375 rt2x00pci_register_write(rt2x00dev,
INT_MASK_CSR, reg);
2389 static int rt61pci_validate_eeprom(
struct rt2x00_dev *rt2x00dev)
2397 rt2x00pci_register_read(rt2x00dev,
E2PROM_CSR, ®);
2399 eeprom.data = rt2x00dev;
2400 eeprom.register_read = rt61pci_eepromregister_read;
2401 eeprom.register_write = rt61pci_eepromregister_write;
2404 eeprom.reg_data_in = 0;
2405 eeprom.reg_data_out = 0;
2406 eeprom.reg_data_clock = 0;
2407 eeprom.reg_chip_select = 0;
2416 if (!is_valid_ether_addr(mac)) {
2417 eth_random_addr(mac);
2418 EEPROM(rt2x00dev,
"MAC: %pM\n", mac);
2422 if (word == 0xffff) {
2433 EEPROM(rt2x00dev,
"Antenna: 0x%04x\n", word);
2436 rt2x00_eeprom_read(rt2x00dev,
EEPROM_NIC, &word);
2437 if (word == 0xffff) {
2445 rt2x00_eeprom_write(rt2x00dev,
EEPROM_NIC, word);
2446 EEPROM(rt2x00dev,
"NIC: 0x%04x\n", word);
2449 rt2x00_eeprom_read(rt2x00dev,
EEPROM_LED, &word);
2450 if (word == 0xffff) {
2453 rt2x00_eeprom_write(rt2x00dev,
EEPROM_LED, word);
2454 EEPROM(rt2x00dev,
"Led: 0x%04x\n", word);
2457 rt2x00_eeprom_read(rt2x00dev,
EEPROM_FREQ, &word);
2458 if (word == 0xffff) {
2461 rt2x00_eeprom_write(rt2x00dev,
EEPROM_FREQ, word);
2462 EEPROM(rt2x00dev,
"Freq: 0x%04x\n", word);
2466 if (word == 0xffff) {
2470 EEPROM(rt2x00dev,
"RSSI OFFSET BG: 0x%04x\n", word);
2473 if (value < -10 || value > 10)
2476 if (value < -10 || value > 10)
2482 if (word == 0xffff) {
2486 EEPROM(rt2x00dev,
"RSSI OFFSET A: 0x%04x\n", word);
2489 if (value < -10 || value > 10)
2492 if (value < -10 || value > 10)
2500 static int rt61pci_init_eeprom(
struct rt2x00_dev *rt2x00dev)
2515 rt2x00pci_register_read(rt2x00dev,
MAC_CSR0, ®);
2519 if (!rt2x00_rf(rt2x00dev,
RF5225) &&
2520 !rt2x00_rf(rt2x00dev,
RF5325) &&
2521 !rt2x00_rf(rt2x00dev,
RF2527) &&
2522 !rt2x00_rf(rt2x00dev,
RF2529)) {
2523 ERROR(rt2x00dev,
"Invalid RF chipset detected.\n");
2556 rt2x00_eeprom_read(rt2x00dev,
EEPROM_FREQ, &eeprom);
2565 rt2x00_eeprom_read(rt2x00dev,
EEPROM_NIC, &eeprom);
2577 if (rt2x00_rf(rt2x00dev,
RF2529) &&
2595 #ifdef CONFIG_RT2X00_LIB_LEDS
2596 rt2x00_eeprom_read(rt2x00dev,
EEPROM_LED, &eeprom);
2599 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio,
LED_TYPE_RADIO);
2600 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc,
LED_TYPE_ASSOC);
2602 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2638 static const struct rf_channel rf_vals_noseq[] = {
2639 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2640 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2641 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2642 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2643 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2644 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2645 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2646 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2647 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2648 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2649 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2650 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2651 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2652 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2655 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2656 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2657 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2658 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2659 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2660 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2661 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2662 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2665 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2666 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2667 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2668 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2669 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2670 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2671 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2672 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2673 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2674 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2677 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2678 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2679 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2680 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2681 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2682 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2685 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2686 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2687 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2688 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2695 static const struct rf_channel rf_vals_seq[] = {
2696 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2697 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2698 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2699 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2700 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2701 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2702 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2703 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2704 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2705 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2706 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2707 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2708 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2709 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2712 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2713 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2714 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2715 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2716 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2717 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2718 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2719 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2722 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2723 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2724 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2725 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2726 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2727 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2728 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2729 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2730 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2731 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2734 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2735 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2736 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2737 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2738 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2739 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2742 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2743 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2744 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2745 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2748 static int rt61pci_probe_hw_mode(
struct rt2x00_dev *rt2x00dev)
2763 rt2x00dev->
hw->flags =
2769 SET_IEEE80211_DEV(rt2x00dev->
hw, rt2x00dev->
dev);
2770 SET_IEEE80211_PERM_ADDR(rt2x00dev->
hw,
2771 rt2x00_eeprom_addr(rt2x00dev,
2783 rt2x00dev->
hw->max_rates = 1;
2784 rt2x00dev->
hw->max_report_rates = 7;
2785 rt2x00dev->
hw->max_rate_tries = 1;
2801 if (rt2x00_rf(rt2x00dev,
RF5225) || rt2x00_rf(rt2x00dev,
RF5325)) {
2816 for (i = 0; i < 14; i++) {
2832 static int rt61pci_probe_hw(
struct rt2x00_dev *rt2x00dev)
2845 retval = rt61pci_validate_eeprom(rt2x00dev);
2849 retval = rt61pci_init_eeprom(rt2x00dev);
2857 rt2x00pci_register_read(rt2x00dev,
MAC_CSR13, ®);
2859 rt2x00pci_register_write(rt2x00dev,
MAC_CSR13, reg);
2864 retval = rt61pci_probe_hw_mode(rt2x00dev);
2879 if (!modparam_nohwcrypt)
2922 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2926 field.bit_offset = (queue_idx & 1) * 16;
2929 rt2x00pci_register_read(rt2x00dev, offset, ®);
2931 rt2x00pci_register_write(rt2x00dev, offset, reg);
2934 field.bit_offset = queue_idx * 4;
2937 rt2x00pci_register_read(rt2x00dev,
AIFSN_CSR, ®);
2939 rt2x00pci_register_write(rt2x00dev,
AIFSN_CSR, reg);
2941 rt2x00pci_register_read(rt2x00dev,
CWMIN_CSR, ®);
2943 rt2x00pci_register_write(rt2x00dev,
CWMIN_CSR, reg);
2945 rt2x00pci_register_read(rt2x00dev,
CWMAX_CSR, ®);
2947 rt2x00pci_register_write(rt2x00dev,
CWMAX_CSR, reg);
2958 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR13, ®);
2960 rt2x00pci_register_read(rt2x00dev,
TXRX_CSR12, ®);
2979 .conf_tx = rt61pci_conf_tx,
2980 .get_tsf = rt61pci_get_tsf,
2990 .irq_handler = rt61pci_interrupt,
2991 .txstatus_tasklet = rt61pci_txstatus_tasklet,
2992 .tbtt_tasklet = rt61pci_tbtt_tasklet,
2993 .rxdone_tasklet = rt61pci_rxdone_tasklet,
2994 .autowake_tasklet = rt61pci_autowake_tasklet,
2995 .probe_hw = rt61pci_probe_hw,
2996 .get_firmware_name = rt61pci_get_firmware_name,
2997 .check_firmware = rt61pci_check_firmware,
2998 .load_firmware = rt61pci_load_firmware,
3001 .get_entry_state = rt61pci_get_entry_state,
3002 .clear_entry = rt61pci_clear_entry,
3003 .set_device_state = rt61pci_set_device_state,
3004 .rfkill_poll = rt61pci_rfkill_poll,
3005 .link_stats = rt61pci_link_stats,
3006 .reset_tuner = rt61pci_reset_tuner,
3007 .link_tuner = rt61pci_link_tuner,
3008 .start_queue = rt61pci_start_queue,
3009 .kick_queue = rt61pci_kick_queue,
3010 .stop_queue = rt61pci_stop_queue,
3012 .write_tx_desc = rt61pci_write_tx_desc,
3013 .write_beacon = rt61pci_write_beacon,
3014 .clear_beacon = rt61pci_clear_beacon,
3015 .fill_rxdone = rt61pci_fill_rxdone,
3016 .config_shared_key = rt61pci_config_shared_key,
3017 .config_pairwise_key = rt61pci_config_pairwise_key,
3018 .config_filter = rt61pci_config_filter,
3019 .config_intf = rt61pci_config_intf,
3020 .config_erp = rt61pci_config_erp,
3021 .config_ant = rt61pci_config_ant,
3022 .config = rt61pci_config,
3046 static const struct rt2x00_ops rt61pci_ops = {
3047 .name = KBUILD_MODNAME,
3052 .extra_tx_headroom = 0,
3053 .rx = &rt61pci_queue_rx,
3054 .tx = &rt61pci_queue_tx,
3055 .bcn = &rt61pci_queue_bcn,
3056 .lib = &rt61pci_rt2x00_ops,
3057 .hw = &rt61pci_mac80211_ops,
3058 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
3059 .debugfs = &rt61pci_rt2x00debug,
3080 "PCI & PCMCIA chipset based cards");
3094 .name = KBUILD_MODNAME,
3095 .id_table = rt61pci_device_table,
3096 .probe = rt61pci_probe,