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smsc-ircc2.c
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1 /*********************************************************************
2  *
3  * Description: Driver for the SMC Infrared Communications Controller
4  * Author: Daniele Peri ([email protected])
5  * Created at:
6  * Modified at:
7  * Modified by:
8  *
9  * Copyright (c) 2002 Daniele Peri
10  * All Rights Reserved.
11  * Copyright (c) 2002 Jean Tourrilhes
12  * Copyright (c) 2006 Linus Walleij
13  *
14  *
15  * Based on smc-ircc.c:
16  *
17  * Copyright (c) 2001 Stefani Seibold
18  * Copyright (c) 1999-2001 Dag Brattli
19  * Copyright (c) 1998-1999 Thomas Davis,
20  *
21  * and irport.c:
22  *
23  * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
24  *
25  *
26  * This program is free software; you can redistribute it and/or
27  * modify it under the terms of the GNU General Public License as
28  * published by the Free Software Foundation; either version 2 of
29  * the License, or (at your option) any later version.
30  *
31  * This program is distributed in the hope that it will be useful,
32  * but WITHOUT ANY WARRANTY; without even the implied warranty of
33  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34  * GNU General Public License for more details.
35  *
36  * You should have received a copy of the GNU General Public License
37  * along with this program; if not, write to the Free Software
38  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39  * MA 02111-1307 USA
40  *
41  ********************************************************************/
42 
43 #include <linux/module.h>
44 #include <linux/kernel.h>
45 #include <linux/types.h>
46 #include <linux/skbuff.h>
47 #include <linux/netdevice.h>
48 #include <linux/ioport.h>
49 #include <linux/delay.h>
50 #include <linux/init.h>
51 #include <linux/interrupt.h>
52 #include <linux/rtnetlink.h>
53 #include <linux/serial_reg.h>
54 #include <linux/dma-mapping.h>
55 #include <linux/pnp.h>
56 #include <linux/platform_device.h>
57 #include <linux/gfp.h>
58 
59 #include <asm/io.h>
60 #include <asm/dma.h>
61 #include <asm/byteorder.h>
62 
63 #include <linux/spinlock.h>
64 #include <linux/pm.h>
65 #ifdef CONFIG_PCI
66 #include <linux/pci.h>
67 #endif
68 
69 #include <net/irda/wrapper.h>
70 #include <net/irda/irda.h>
71 #include <net/irda/irda_device.h>
72 
73 #include "smsc-ircc2.h"
74 #include "smsc-sio.h"
75 
76 
77 MODULE_AUTHOR("Daniele Peri <[email protected]>");
78 MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
79 MODULE_LICENSE("GPL");
80 
81 static bool smsc_nopnp = true;
82 module_param_named(nopnp, smsc_nopnp, bool, 0);
83 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings, defaults to true");
84 
85 #define DMA_INVAL 255
86 static int ircc_dma = DMA_INVAL;
87 module_param(ircc_dma, int, 0);
88 MODULE_PARM_DESC(ircc_dma, "DMA channel");
89 
90 #define IRQ_INVAL 255
91 static int ircc_irq = IRQ_INVAL;
92 module_param(ircc_irq, int, 0);
93 MODULE_PARM_DESC(ircc_irq, "IRQ line");
94 
95 static int ircc_fir;
96 module_param(ircc_fir, int, 0);
97 MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
98 
99 static int ircc_sir;
100 module_param(ircc_sir, int, 0);
101 MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
102 
103 static int ircc_cfg;
104 module_param(ircc_cfg, int, 0);
105 MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
106 
107 static int ircc_transceiver;
108 module_param(ircc_transceiver, int, 0);
109 MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
110 
111 /* Types */
112 
113 #ifdef CONFIG_PCI
114 struct smsc_ircc_subsystem_configuration {
115  unsigned short vendor; /* PCI vendor ID */
116  unsigned short device; /* PCI vendor ID */
117  unsigned short subvendor; /* PCI subsystem vendor ID */
118  unsigned short subdevice; /* PCI subsystem device ID */
119  unsigned short sir_io; /* I/O port for SIR */
120  unsigned short fir_io; /* I/O port for FIR */
121  unsigned char fir_irq; /* FIR IRQ */
122  unsigned char fir_dma; /* FIR DMA */
123  unsigned short cfg_base; /* I/O port for chip configuration */
124  int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
125  const char *name; /* name shown as info */
126 };
127 #endif
128 
129 struct smsc_transceiver {
130  char *name;
131  void (*set_for_speed)(int fir_base, u32 speed);
132  int (*probe)(int fir_base);
133 };
134 
135 struct smsc_chip {
136  char *name;
137  #if 0
138  u8 type;
139  #endif
140  u16 flags;
141  u8 devid;
142  u8 rev;
143 };
144 
145 struct smsc_chip_address {
146  unsigned int cfg_base;
147  unsigned int type;
148 };
149 
150 /* Private data for each instance */
151 struct smsc_ircc_cb {
152  struct net_device *netdev; /* Yes! we are some kind of netdevice */
153  struct irlap_cb *irlap; /* The link layer we are binded to */
154 
155  chipio_t io; /* IrDA controller information */
156  iobuff_t tx_buff; /* Transmit buffer */
157  iobuff_t rx_buff; /* Receive buffer */
158  dma_addr_t tx_buff_dma;
159  dma_addr_t rx_buff_dma;
160 
161  struct qos_info qos; /* QoS capabilities for this device */
162 
163  spinlock_t lock; /* For serializing operations */
164 
165  __u32 new_speed;
166  __u32 flags; /* Interface flags */
167 
168  int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
169  int tx_len; /* Number of frames in tx_buff */
170 
171  int transceiver;
172  struct platform_device *pldev;
173 };
174 
175 /* Constants */
176 
177 #define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2"
178 
179 #define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
180 #define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
181 #define SMSC_IRCC2_C_NET_TIMEOUT 0
182 #define SMSC_IRCC2_C_SIR_STOP 0
183 
184 static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
185 
186 /* Prototypes */
187 
188 static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
189 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
190 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
191 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
192 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
193 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
194 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
195 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
196 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
197 static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb,
198  struct net_device *dev);
199 static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb,
200  struct net_device *dev);
201 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
202 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
203 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
204 static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
205 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id);
206 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
207 static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
208 #if SMSC_IRCC2_C_SIR_STOP
209 static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
210 #endif
211 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
212 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
213 static int smsc_ircc_net_open(struct net_device *dev);
214 static int smsc_ircc_net_close(struct net_device *dev);
215 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
216 #if SMSC_IRCC2_C_NET_TIMEOUT
217 static void smsc_ircc_timeout(struct net_device *dev);
218 #endif
219 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
220 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
221 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
222 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
223 
224 /* Probing */
225 static int __init smsc_ircc_look_for_chips(void);
226 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
227 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
228 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
229 static int __init smsc_superio_fdc(unsigned short cfg_base);
230 static int __init smsc_superio_lpc(unsigned short cfg_base);
231 #ifdef CONFIG_PCI
232 static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
233 static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
234 static void __init preconfigure_ali_port(struct pci_dev *dev,
235  unsigned short port);
236 static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
237 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
238  unsigned short ircc_fir,
239  unsigned short ircc_sir,
240  unsigned char ircc_dma,
241  unsigned char ircc_irq);
242 #endif
243 
244 /* Transceivers specific functions */
245 
246 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
247 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
248 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
249 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
250 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
251 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
252 
253 /* Power Management */
254 
255 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
256 static int smsc_ircc_resume(struct platform_device *dev);
257 
258 static struct platform_driver smsc_ircc_driver = {
259  .suspend = smsc_ircc_suspend,
260  .resume = smsc_ircc_resume,
261  .driver = {
262  .name = SMSC_IRCC2_DRIVER_NAME,
263  },
264 };
265 
266 /* Transceivers for SMSC-ircc */
267 
268 static struct smsc_transceiver smsc_transceivers[] =
269 {
270  { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
271  { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
272  { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
273  { NULL, NULL }
274 };
275 #define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
276 
277 /* SMC SuperIO chipsets definitions */
278 
279 #define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
280 #define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
281 #define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
282 #define SIR 0 /* SuperIO Chip has only slow IRDA */
283 #define FIR 4 /* SuperIO Chip has fast IRDA */
284 #define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
285 
286 static struct smsc_chip __initdata fdc_chips_flat[] =
287 {
288  /* Base address 0x3f0 or 0x370 */
289  { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
290  { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
291  { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
292  { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
293  { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
294  { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
295  { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
296  { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
297  { NULL }
298 };
299 
300 static struct smsc_chip __initdata fdc_chips_paged[] =
301 {
302  /* Base address 0x3f0 or 0x370 */
303  { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
304  { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
305  { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
306  { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
307  { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
308  { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
309  { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
310  { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
311  { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
312  { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
313  { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
314  { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
315  { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
316  { NULL }
317 };
318 
319 static struct smsc_chip __initdata lpc_chips_flat[] =
320 {
321  /* Base address 0x2E or 0x4E */
322  { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
323  { "47N227", KEY55_1|FIR|SERx4, 0x7a, 0x00 },
324  { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
325  { NULL }
326 };
327 
328 static struct smsc_chip __initdata lpc_chips_paged[] =
329 {
330  /* Base address 0x2E or 0x4E */
331  { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
332  { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
333  { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
334  { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
335  { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
336  { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
337  { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
338  { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
339  { NULL }
340 };
341 
342 #define SMSCSIO_TYPE_FDC 1
343 #define SMSCSIO_TYPE_LPC 2
344 #define SMSCSIO_TYPE_FLAT 4
345 #define SMSCSIO_TYPE_PAGED 8
346 
347 static struct smsc_chip_address __initdata possible_addresses[] =
348 {
349  { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
350  { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
351  { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
352  { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
353  { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
354  { 0, 0 }
355 };
356 
357 /* Globals */
358 
359 static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
360 static unsigned short dev_count;
361 
362 static inline void register_bank(int iobase, int bank)
363 {
364  outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
365  iobase + IRCC_MASTER);
366 }
367 
368 /* PNP hotplug support */
369 static const struct pnp_device_id smsc_ircc_pnp_table[] = {
370  { .id = "SMCf010", .driver_data = 0 },
371  /* and presumably others */
372  { }
373 };
374 MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table);
375 
376 static int pnp_driver_registered;
377 
378 #ifdef CONFIG_PNP
379 static int __devinit smsc_ircc_pnp_probe(struct pnp_dev *dev,
380  const struct pnp_device_id *dev_id)
381 {
382  unsigned int firbase, sirbase;
383  u8 dma, irq;
384 
385  if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) &&
386  pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0)))
387  return -EINVAL;
388 
389  sirbase = pnp_port_start(dev, 0);
390  firbase = pnp_port_start(dev, 1);
391  dma = pnp_dma(dev, 0);
392  irq = pnp_irq(dev, 0);
393 
394  if (smsc_ircc_open(firbase, sirbase, dma, irq))
395  return -ENODEV;
396 
397  return 0;
398 }
399 
400 static struct pnp_driver smsc_ircc_pnp_driver = {
401  .name = "smsc-ircc2",
402  .id_table = smsc_ircc_pnp_table,
403  .probe = smsc_ircc_pnp_probe,
404 };
405 #else /* CONFIG_PNP */
406 static struct pnp_driver smsc_ircc_pnp_driver;
407 #endif
408 
409 /*******************************************************************************
410  *
411  *
412  * SMSC-ircc stuff
413  *
414  *
415  *******************************************************************************/
416 
417 static int __init smsc_ircc_legacy_probe(void)
418 {
419  int ret = 0;
420 
421 #ifdef CONFIG_PCI
422  if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
423  /* Ignore errors from preconfiguration */
424  IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name);
425  }
426 #endif
427 
428  if (ircc_fir > 0 && ircc_sir > 0) {
429  IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
430  IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
431 
432  if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
433  ret = -ENODEV;
434  } else {
435  ret = -ENODEV;
436 
437  /* try user provided configuration register base address */
438  if (ircc_cfg > 0) {
439  IRDA_MESSAGE(" Overriding configuration address "
440  "0x%04x\n", ircc_cfg);
441  if (!smsc_superio_fdc(ircc_cfg))
442  ret = 0;
443  if (!smsc_superio_lpc(ircc_cfg))
444  ret = 0;
445  }
446 
447  if (smsc_ircc_look_for_chips() > 0)
448  ret = 0;
449  }
450  return ret;
451 }
452 
453 /*
454  * Function smsc_ircc_init ()
455  *
456  * Initialize chip. Just try to find out how many chips we are dealing with
457  * and where they are
458  */
459 static int __init smsc_ircc_init(void)
460 {
461  int ret;
462 
463  IRDA_DEBUG(1, "%s\n", __func__);
464 
465  ret = platform_driver_register(&smsc_ircc_driver);
466  if (ret) {
467  IRDA_ERROR("%s, Can't register driver!\n", driver_name);
468  return ret;
469  }
470 
471  dev_count = 0;
472 
473  if (smsc_nopnp || !pnp_platform_devices ||
474  ircc_cfg || ircc_fir || ircc_sir ||
475  ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) {
476  ret = smsc_ircc_legacy_probe();
477  } else {
478  if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0)
479  pnp_driver_registered = 1;
480  }
481 
482  if (ret) {
483  if (pnp_driver_registered)
484  pnp_unregister_driver(&smsc_ircc_pnp_driver);
485  platform_driver_unregister(&smsc_ircc_driver);
486  }
487 
488  return ret;
489 }
490 
491 static netdev_tx_t smsc_ircc_net_xmit(struct sk_buff *skb,
492  struct net_device *dev)
493 {
494  struct smsc_ircc_cb *self = netdev_priv(dev);
495 
496  if (self->io.speed > 115200)
497  return smsc_ircc_hard_xmit_fir(skb, dev);
498  else
499  return smsc_ircc_hard_xmit_sir(skb, dev);
500 }
501 
502 static const struct net_device_ops smsc_ircc_netdev_ops = {
503  .ndo_open = smsc_ircc_net_open,
504  .ndo_stop = smsc_ircc_net_close,
505  .ndo_do_ioctl = smsc_ircc_net_ioctl,
506  .ndo_start_xmit = smsc_ircc_net_xmit,
507 #if SMSC_IRCC2_C_NET_TIMEOUT
508  .ndo_tx_timeout = smsc_ircc_timeout,
509 #endif
510 };
511 
512 /*
513  * Function smsc_ircc_open (firbase, sirbase, dma, irq)
514  *
515  * Try to open driver instance
516  *
517  */
518 static int __devinit smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
519 {
520  struct smsc_ircc_cb *self;
521  struct net_device *dev;
522  int err;
523 
524  IRDA_DEBUG(1, "%s\n", __func__);
525 
526  err = smsc_ircc_present(fir_base, sir_base);
527  if (err)
528  goto err_out;
529 
530  err = -ENOMEM;
531  if (dev_count >= ARRAY_SIZE(dev_self)) {
532  IRDA_WARNING("%s(), too many devices!\n", __func__);
533  goto err_out1;
534  }
535 
536  /*
537  * Allocate new instance of the driver
538  */
539  dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
540  if (!dev) {
541  IRDA_WARNING("%s() can't allocate net device\n", __func__);
542  goto err_out1;
543  }
544 
545 #if SMSC_IRCC2_C_NET_TIMEOUT
546  dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
547 #endif
548  dev->netdev_ops = &smsc_ircc_netdev_ops;
549 
550  self = netdev_priv(dev);
551  self->netdev = dev;
552 
553  /* Make ifconfig display some details */
554  dev->base_addr = self->io.fir_base = fir_base;
555  dev->irq = self->io.irq = irq;
556 
557  /* Need to store self somewhere */
558  dev_self[dev_count] = self;
559  spin_lock_init(&self->lock);
560 
561  self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
562  self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
563 
564  self->rx_buff.head =
565  dma_alloc_coherent(NULL, self->rx_buff.truesize,
566  &self->rx_buff_dma, GFP_KERNEL);
567  if (self->rx_buff.head == NULL) {
568  IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
569  driver_name);
570  goto err_out2;
571  }
572 
573  self->tx_buff.head =
574  dma_alloc_coherent(NULL, self->tx_buff.truesize,
575  &self->tx_buff_dma, GFP_KERNEL);
576  if (self->tx_buff.head == NULL) {
577  IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
578  driver_name);
579  goto err_out3;
580  }
581 
582  memset(self->rx_buff.head, 0, self->rx_buff.truesize);
583  memset(self->tx_buff.head, 0, self->tx_buff.truesize);
584 
585  self->rx_buff.in_frame = FALSE;
586  self->rx_buff.state = OUTSIDE_FRAME;
587  self->tx_buff.data = self->tx_buff.head;
588  self->rx_buff.data = self->rx_buff.head;
589 
590  smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
591  smsc_ircc_setup_qos(self);
592  smsc_ircc_init_chip(self);
593 
594  if (ircc_transceiver > 0 &&
595  ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
596  self->transceiver = ircc_transceiver;
597  else
598  smsc_ircc_probe_transceiver(self);
599 
600  err = register_netdev(self->netdev);
601  if (err) {
602  IRDA_ERROR("%s, Network device registration failed!\n",
603  driver_name);
604  goto err_out4;
605  }
606 
607  self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
608  dev_count, NULL, 0);
609  if (IS_ERR(self->pldev)) {
610  err = PTR_ERR(self->pldev);
611  goto err_out5;
612  }
613  platform_set_drvdata(self->pldev, self);
614 
615  IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
616  dev_count++;
617 
618  return 0;
619 
620  err_out5:
621  unregister_netdev(self->netdev);
622 
623  err_out4:
624  dma_free_coherent(NULL, self->tx_buff.truesize,
625  self->tx_buff.head, self->tx_buff_dma);
626  err_out3:
627  dma_free_coherent(NULL, self->rx_buff.truesize,
628  self->rx_buff.head, self->rx_buff_dma);
629  err_out2:
630  free_netdev(self->netdev);
631  dev_self[dev_count] = NULL;
632  err_out1:
633  release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
634  release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
635  err_out:
636  return err;
637 }
638 
639 /*
640  * Function smsc_ircc_present(fir_base, sir_base)
641  *
642  * Check the smsc-ircc chip presence
643  *
644  */
645 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
646 {
647  unsigned char low, high, chip, config, dma, irq, version;
648 
649  if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
650  driver_name)) {
651  IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
652  __func__, fir_base);
653  goto out1;
654  }
655 
656  if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
657  driver_name)) {
658  IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
659  __func__, sir_base);
660  goto out2;
661  }
662 
663  register_bank(fir_base, 3);
664 
665  high = inb(fir_base + IRCC_ID_HIGH);
666  low = inb(fir_base + IRCC_ID_LOW);
667  chip = inb(fir_base + IRCC_CHIP_ID);
668  version = inb(fir_base + IRCC_VERSION);
669  config = inb(fir_base + IRCC_INTERFACE);
670  dma = config & IRCC_INTERFACE_DMA_MASK;
671  irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
672 
673  if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
674  IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
675  __func__, fir_base);
676  goto out3;
677  }
678  IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
679  "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
680  chip & 0x0f, version, fir_base, sir_base, dma, irq);
681 
682  return 0;
683 
684  out3:
685  release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
686  out2:
687  release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
688  out1:
689  return -ENODEV;
690 }
691 
692 /*
693  * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
694  *
695  * Setup I/O
696  *
697  */
698 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
699  unsigned int fir_base, unsigned int sir_base,
700  u8 dma, u8 irq)
701 {
702  unsigned char config, chip_dma, chip_irq;
703 
704  register_bank(fir_base, 3);
705  config = inb(fir_base + IRCC_INTERFACE);
706  chip_dma = config & IRCC_INTERFACE_DMA_MASK;
707  chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
708 
709  self->io.fir_base = fir_base;
710  self->io.sir_base = sir_base;
711  self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
712  self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
713  self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
714  self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
715 
716  if (irq != IRQ_INVAL) {
717  if (irq != chip_irq)
718  IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
719  driver_name, chip_irq, irq);
720  self->io.irq = irq;
721  } else
722  self->io.irq = chip_irq;
723 
724  if (dma != DMA_INVAL) {
725  if (dma != chip_dma)
726  IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
727  driver_name, chip_dma, dma);
728  self->io.dma = dma;
729  } else
730  self->io.dma = chip_dma;
731 
732 }
733 
734 /*
735  * Function smsc_ircc_setup_qos(self)
736  *
737  * Setup qos
738  *
739  */
740 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
741 {
742  /* Initialize QoS for this device */
743  irda_init_max_qos_capabilies(&self->qos);
744 
745  self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
746  IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
747 
748  self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
749  self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
750  irda_qos_bits_to_value(&self->qos);
751 }
752 
753 /*
754  * Function smsc_ircc_init_chip(self)
755  *
756  * Init chip
757  *
758  */
759 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
760 {
761  int iobase = self->io.fir_base;
762 
763  register_bank(iobase, 0);
764  outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
765  outb(0x00, iobase + IRCC_MASTER);
766 
767  register_bank(iobase, 1);
768  outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
769  iobase + IRCC_SCE_CFGA);
770 
771 #ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
772  outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
773  iobase + IRCC_SCE_CFGB);
774 #else
775  outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
776  iobase + IRCC_SCE_CFGB);
777 #endif
778  (void) inb(iobase + IRCC_FIFO_THRESHOLD);
779  outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
780 
781  register_bank(iobase, 4);
782  outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
783 
784  register_bank(iobase, 0);
785  outb(0, iobase + IRCC_LCR_A);
786 
787  smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
788 
789  /* Power on device */
790  outb(0x00, iobase + IRCC_MASTER);
791 }
792 
793 /*
794  * Function smsc_ircc_net_ioctl (dev, rq, cmd)
795  *
796  * Process IOCTL commands for this device
797  *
798  */
799 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
800 {
801  struct if_irda_req *irq = (struct if_irda_req *) rq;
802  struct smsc_ircc_cb *self;
803  unsigned long flags;
804  int ret = 0;
805 
806  IRDA_ASSERT(dev != NULL, return -1;);
807 
808  self = netdev_priv(dev);
809 
810  IRDA_ASSERT(self != NULL, return -1;);
811 
812  IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __func__, dev->name, cmd);
813 
814  switch (cmd) {
815  case SIOCSBANDWIDTH: /* Set bandwidth */
816  if (!capable(CAP_NET_ADMIN))
817  ret = -EPERM;
818  else {
819  /* Make sure we are the only one touching
820  * self->io.speed and the hardware - Jean II */
821  spin_lock_irqsave(&self->lock, flags);
822  smsc_ircc_change_speed(self, irq->ifr_baudrate);
823  spin_unlock_irqrestore(&self->lock, flags);
824  }
825  break;
826  case SIOCSMEDIABUSY: /* Set media busy */
827  if (!capable(CAP_NET_ADMIN)) {
828  ret = -EPERM;
829  break;
830  }
831 
832  irda_device_set_media_busy(self->netdev, TRUE);
833  break;
834  case SIOCGRECEIVING: /* Check if we are receiving right now */
835  irq->ifr_receiving = smsc_ircc_is_receiving(self);
836  break;
837  #if 0
838  case SIOCSDTRRTS:
839  if (!capable(CAP_NET_ADMIN)) {
840  ret = -EPERM;
841  break;
842  }
843  smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
844  break;
845  #endif
846  default:
847  ret = -EOPNOTSUPP;
848  }
849 
850  return ret;
851 }
852 
853 #if SMSC_IRCC2_C_NET_TIMEOUT
854 /*
855  * Function smsc_ircc_timeout (struct net_device *dev)
856  *
857  * The networking timeout management.
858  *
859  */
860 
861 static void smsc_ircc_timeout(struct net_device *dev)
862 {
863  struct smsc_ircc_cb *self = netdev_priv(dev);
864  unsigned long flags;
865 
866  IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
867  dev->name, self->io.speed);
868  spin_lock_irqsave(&self->lock, flags);
869  smsc_ircc_sir_start(self);
870  smsc_ircc_change_speed(self, self->io.speed);
871  dev->trans_start = jiffies; /* prevent tx timeout */
872  netif_wake_queue(dev);
873  spin_unlock_irqrestore(&self->lock, flags);
874 }
875 #endif
876 
877 /*
878  * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
879  *
880  * Transmits the current frame until FIFO is full, then
881  * waits until the next transmit interrupt, and continues until the
882  * frame is transmitted.
883  */
884 static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb,
885  struct net_device *dev)
886 {
887  struct smsc_ircc_cb *self;
888  unsigned long flags;
889  s32 speed;
890 
891  IRDA_DEBUG(1, "%s\n", __func__);
892 
893  IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
894 
895  self = netdev_priv(dev);
896  IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
897 
898  netif_stop_queue(dev);
899 
900  /* Make sure test of self->io.speed & speed change are atomic */
901  spin_lock_irqsave(&self->lock, flags);
902 
903  /* Check if we need to change the speed */
904  speed = irda_get_next_speed(skb);
905  if (speed != self->io.speed && speed != -1) {
906  /* Check for empty frame */
907  if (!skb->len) {
908  /*
909  * We send frames one by one in SIR mode (no
910  * pipelining), so at this point, if we were sending
911  * a previous frame, we just received the interrupt
912  * telling us it is finished (UART_IIR_THRI).
913  * Therefore, waiting for the transmitter to really
914  * finish draining the fifo won't take too long.
915  * And the interrupt handler is not expected to run.
916  * - Jean II */
917  smsc_ircc_sir_wait_hw_transmitter_finish(self);
918  smsc_ircc_change_speed(self, speed);
919  spin_unlock_irqrestore(&self->lock, flags);
920  dev_kfree_skb(skb);
921  return NETDEV_TX_OK;
922  }
923  self->new_speed = speed;
924  }
925 
926  /* Init tx buffer */
927  self->tx_buff.data = self->tx_buff.head;
928 
929  /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
930  self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
931  self->tx_buff.truesize);
932 
933  dev->stats.tx_bytes += self->tx_buff.len;
934 
935  /* Turn on transmit finished interrupt. Will fire immediately! */
936  outb(UART_IER_THRI, self->io.sir_base + UART_IER);
937 
938  spin_unlock_irqrestore(&self->lock, flags);
939 
940  dev_kfree_skb(skb);
941 
942  return NETDEV_TX_OK;
943 }
944 
945 /*
946  * Function smsc_ircc_set_fir_speed (self, baud)
947  *
948  * Change the speed of the device
949  *
950  */
951 static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
952 {
953  int fir_base, ir_mode, ctrl, fast;
954 
955  IRDA_ASSERT(self != NULL, return;);
956  fir_base = self->io.fir_base;
957 
958  self->io.speed = speed;
959 
960  switch (speed) {
961  default:
962  case 576000:
963  ir_mode = IRCC_CFGA_IRDA_HDLC;
964  ctrl = IRCC_CRC;
965  fast = 0;
966  IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __func__);
967  break;
968  case 1152000:
969  ir_mode = IRCC_CFGA_IRDA_HDLC;
970  ctrl = IRCC_1152 | IRCC_CRC;
971  fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
972  IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
973  __func__);
974  break;
975  case 4000000:
976  ir_mode = IRCC_CFGA_IRDA_4PPM;
977  ctrl = IRCC_CRC;
978  fast = IRCC_LCR_A_FAST;
979  IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
980  __func__);
981  break;
982  }
983  #if 0
984  Now in tranceiver!
985  /* This causes an interrupt */
986  register_bank(fir_base, 0);
987  outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
988  #endif
989 
990  register_bank(fir_base, 1);
991  outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
992 
993  register_bank(fir_base, 4);
994  outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
995 }
996 
997 /*
998  * Function smsc_ircc_fir_start(self)
999  *
1000  * Change the speed of the device
1001  *
1002  */
1003 static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
1004 {
1005  struct net_device *dev;
1006  int fir_base;
1007 
1008  IRDA_DEBUG(1, "%s\n", __func__);
1009 
1010  IRDA_ASSERT(self != NULL, return;);
1011  dev = self->netdev;
1012  IRDA_ASSERT(dev != NULL, return;);
1013 
1014  fir_base = self->io.fir_base;
1015 
1016  /* Reset everything */
1017 
1018  /* Clear FIFO */
1019  outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1020 
1021  /* Enable interrupt */
1022  /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1023 
1024  register_bank(fir_base, 1);
1025 
1026  /* Select the TX/RX interface */
1027 #ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
1028  outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
1029  fir_base + IRCC_SCE_CFGB);
1030 #else
1031  outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
1032  fir_base + IRCC_SCE_CFGB);
1033 #endif
1034  (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1035 
1036  /* Enable SCE interrupts */
1037  outb(0, fir_base + IRCC_MASTER);
1038  register_bank(fir_base, 0);
1039  outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
1040  outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1041 }
1042 
1043 /*
1044  * Function smsc_ircc_fir_stop(self, baud)
1045  *
1046  * Change the speed of the device
1047  *
1048  */
1049 static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
1050 {
1051  int fir_base;
1052 
1053  IRDA_DEBUG(1, "%s\n", __func__);
1054 
1055  IRDA_ASSERT(self != NULL, return;);
1056 
1057  fir_base = self->io.fir_base;
1058  register_bank(fir_base, 0);
1059  /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
1060  outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1061 }
1062 
1063 
1064 /*
1065  * Function smsc_ircc_change_speed(self, baud)
1066  *
1067  * Change the speed of the device
1068  *
1069  * This function *must* be called with spinlock held, because it may
1070  * be called from the irq handler. - Jean II
1071  */
1072 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1073 {
1074  struct net_device *dev;
1075  int last_speed_was_sir;
1076 
1077  IRDA_DEBUG(0, "%s() changing speed to: %d\n", __func__, speed);
1078 
1079  IRDA_ASSERT(self != NULL, return;);
1080  dev = self->netdev;
1081 
1082  last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
1083 
1084  #if 0
1085  /* Temp Hack */
1086  speed= 1152000;
1087  self->io.speed = speed;
1088  last_speed_was_sir = 0;
1089  smsc_ircc_fir_start(self);
1090  #endif
1091 
1092  if (self->io.speed == 0)
1093  smsc_ircc_sir_start(self);
1094 
1095  #if 0
1096  if (!last_speed_was_sir) speed = self->io.speed;
1097  #endif
1098 
1099  if (self->io.speed != speed)
1100  smsc_ircc_set_transceiver_for_speed(self, speed);
1101 
1102  self->io.speed = speed;
1103 
1104  if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1105  if (!last_speed_was_sir) {
1106  smsc_ircc_fir_stop(self);
1107  smsc_ircc_sir_start(self);
1108  }
1109  smsc_ircc_set_sir_speed(self, speed);
1110  } else {
1111  if (last_speed_was_sir) {
1112  #if SMSC_IRCC2_C_SIR_STOP
1113  smsc_ircc_sir_stop(self);
1114  #endif
1115  smsc_ircc_fir_start(self);
1116  }
1117  smsc_ircc_set_fir_speed(self, speed);
1118 
1119  #if 0
1120  self->tx_buff.len = 10;
1121  self->tx_buff.data = self->tx_buff.head;
1122 
1123  smsc_ircc_dma_xmit(self, 4000);
1124  #endif
1125  /* Be ready for incoming frames */
1126  smsc_ircc_dma_receive(self);
1127  }
1128 
1129  netif_wake_queue(dev);
1130 }
1131 
1132 /*
1133  * Function smsc_ircc_set_sir_speed (self, speed)
1134  *
1135  * Set speed of IrDA port to specified baudrate
1136  *
1137  */
1138 static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1139 {
1140  int iobase;
1141  int fcr; /* FIFO control reg */
1142  int lcr; /* Line control reg */
1143  int divisor;
1144 
1145  IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __func__, speed);
1146 
1147  IRDA_ASSERT(self != NULL, return;);
1148  iobase = self->io.sir_base;
1149 
1150  /* Update accounting for new speed */
1151  self->io.speed = speed;
1152 
1153  /* Turn off interrupts */
1154  outb(0, iobase + UART_IER);
1155 
1156  divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
1157 
1158  fcr = UART_FCR_ENABLE_FIFO;
1159 
1160  /*
1161  * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1162  * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1163  * about this timeout since it will always be fast enough.
1164  */
1165  fcr |= self->io.speed < 38400 ?
1166  UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1167 
1168  /* IrDA ports use 8N1 */
1169  lcr = UART_LCR_WLEN8;
1170 
1171  outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1172  outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1173  outb(divisor >> 8, iobase + UART_DLM);
1174  outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1175  outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1176 
1177  /* Turn on interrups */
1178  outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1179 
1180  IRDA_DEBUG(2, "%s() speed changed to: %d\n", __func__, speed);
1181 }
1182 
1183 
1184 /*
1185  * Function smsc_ircc_hard_xmit_fir (skb, dev)
1186  *
1187  * Transmit the frame!
1188  *
1189  */
1190 static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb,
1191  struct net_device *dev)
1192 {
1193  struct smsc_ircc_cb *self;
1194  unsigned long flags;
1195  s32 speed;
1196  int mtt;
1197 
1198  IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
1199  self = netdev_priv(dev);
1200  IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
1201 
1202  netif_stop_queue(dev);
1203 
1204  /* Make sure test of self->io.speed & speed change are atomic */
1205  spin_lock_irqsave(&self->lock, flags);
1206 
1207  /* Check if we need to change the speed after this frame */
1208  speed = irda_get_next_speed(skb);
1209  if (speed != self->io.speed && speed != -1) {
1210  /* Check for empty frame */
1211  if (!skb->len) {
1212  /* Note : you should make sure that speed changes
1213  * are not going to corrupt any outgoing frame.
1214  * Look at nsc-ircc for the gory details - Jean II */
1215  smsc_ircc_change_speed(self, speed);
1216  spin_unlock_irqrestore(&self->lock, flags);
1217  dev_kfree_skb(skb);
1218  return NETDEV_TX_OK;
1219  }
1220 
1221  self->new_speed = speed;
1222  }
1223 
1224  skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len);
1225 
1226  self->tx_buff.len = skb->len;
1227  self->tx_buff.data = self->tx_buff.head;
1228 
1229  mtt = irda_get_mtt(skb);
1230  if (mtt) {
1231  int bofs;
1232 
1233  /*
1234  * Compute how many BOFs (STA or PA's) we need to waste the
1235  * min turn time given the speed of the link.
1236  */
1237  bofs = mtt * (self->io.speed / 1000) / 8000;
1238  if (bofs > 4095)
1239  bofs = 4095;
1240 
1241  smsc_ircc_dma_xmit(self, bofs);
1242  } else {
1243  /* Transmit frame */
1244  smsc_ircc_dma_xmit(self, 0);
1245  }
1246 
1247  spin_unlock_irqrestore(&self->lock, flags);
1248  dev_kfree_skb(skb);
1249 
1250  return NETDEV_TX_OK;
1251 }
1252 
1253 /*
1254  * Function smsc_ircc_dma_xmit (self, bofs)
1255  *
1256  * Transmit data using DMA
1257  *
1258  */
1259 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1260 {
1261  int iobase = self->io.fir_base;
1262  u8 ctrl;
1263 
1264  IRDA_DEBUG(3, "%s\n", __func__);
1265 #if 1
1266  /* Disable Rx */
1267  register_bank(iobase, 0);
1268  outb(0x00, iobase + IRCC_LCR_B);
1269 #endif
1270  register_bank(iobase, 1);
1271  outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1272  iobase + IRCC_SCE_CFGB);
1273 
1274  self->io.direction = IO_XMIT;
1275 
1276  /* Set BOF additional count for generating the min turn time */
1277  register_bank(iobase, 4);
1278  outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1279  ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1280  outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1281 
1282  /* Set max Tx frame size */
1283  outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1284  outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1285 
1286  /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
1287 
1288  /* Enable burst mode chip Tx DMA */
1289  register_bank(iobase, 1);
1290  outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1291  IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1292 
1293  /* Setup DMA controller (must be done after enabling chip DMA) */
1294  irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1295  DMA_TX_MODE);
1296 
1297  /* Enable interrupt */
1298 
1299  register_bank(iobase, 0);
1300  outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1301  outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1302 
1303  /* Enable transmit */
1304  outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1305 }
1306 
1307 /*
1308  * Function smsc_ircc_dma_xmit_complete (self)
1309  *
1310  * The transfer of a frame in finished. This function will only be called
1311  * by the interrupt handler
1312  *
1313  */
1314 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1315 {
1316  int iobase = self->io.fir_base;
1317 
1318  IRDA_DEBUG(3, "%s\n", __func__);
1319 #if 0
1320  /* Disable Tx */
1321  register_bank(iobase, 0);
1322  outb(0x00, iobase + IRCC_LCR_B);
1323 #endif
1324  register_bank(iobase, 1);
1325  outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1326  iobase + IRCC_SCE_CFGB);
1327 
1328  /* Check for underrun! */
1329  register_bank(iobase, 0);
1330  if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1331  self->netdev->stats.tx_errors++;
1332  self->netdev->stats.tx_fifo_errors++;
1333 
1334  /* Reset error condition */
1335  register_bank(iobase, 0);
1336  outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1337  outb(0x00, iobase + IRCC_MASTER);
1338  } else {
1339  self->netdev->stats.tx_packets++;
1340  self->netdev->stats.tx_bytes += self->tx_buff.len;
1341  }
1342 
1343  /* Check if it's time to change the speed */
1344  if (self->new_speed) {
1345  smsc_ircc_change_speed(self, self->new_speed);
1346  self->new_speed = 0;
1347  }
1348 
1349  netif_wake_queue(self->netdev);
1350 }
1351 
1352 /*
1353  * Function smsc_ircc_dma_receive(self)
1354  *
1355  * Get ready for receiving a frame. The device will initiate a DMA
1356  * if it starts to receive a frame.
1357  *
1358  */
1359 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1360 {
1361  int iobase = self->io.fir_base;
1362 #if 0
1363  /* Turn off chip DMA */
1364  register_bank(iobase, 1);
1365  outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1366  iobase + IRCC_SCE_CFGB);
1367 #endif
1368 
1369  /* Disable Tx */
1370  register_bank(iobase, 0);
1371  outb(0x00, iobase + IRCC_LCR_B);
1372 
1373  /* Turn off chip DMA */
1374  register_bank(iobase, 1);
1375  outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1376  iobase + IRCC_SCE_CFGB);
1377 
1378  self->io.direction = IO_RECV;
1379  self->rx_buff.data = self->rx_buff.head;
1380 
1381  /* Set max Rx frame size */
1382  register_bank(iobase, 4);
1383  outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1384  outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1385 
1386  /* Setup DMA controller */
1387  irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1388  DMA_RX_MODE);
1389 
1390  /* Enable burst mode chip Rx DMA */
1391  register_bank(iobase, 1);
1392  outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1393  IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1394 
1395  /* Enable interrupt */
1396  register_bank(iobase, 0);
1397  outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1398  outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1399 
1400  /* Enable receiver */
1401  register_bank(iobase, 0);
1402  outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
1403  iobase + IRCC_LCR_B);
1404 
1405  return 0;
1406 }
1407 
1408 /*
1409  * Function smsc_ircc_dma_receive_complete(self)
1410  *
1411  * Finished with receiving frames
1412  *
1413  */
1414 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1415 {
1416  struct sk_buff *skb;
1417  int len, msgcnt, lsr;
1418  int iobase = self->io.fir_base;
1419 
1420  register_bank(iobase, 0);
1421 
1422  IRDA_DEBUG(3, "%s\n", __func__);
1423 #if 0
1424  /* Disable Rx */
1425  register_bank(iobase, 0);
1426  outb(0x00, iobase + IRCC_LCR_B);
1427 #endif
1428  register_bank(iobase, 0);
1429  outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1430  lsr= inb(iobase + IRCC_LSR);
1431  msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1432 
1433  IRDA_DEBUG(2, "%s: dma count = %d\n", __func__,
1434  get_dma_residue(self->io.dma));
1435 
1436  len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1437 
1438  /* Look for errors */
1439  if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1440  self->netdev->stats.rx_errors++;
1441  if (lsr & IRCC_LSR_FRAME_ERROR)
1442  self->netdev->stats.rx_frame_errors++;
1443  if (lsr & IRCC_LSR_CRC_ERROR)
1444  self->netdev->stats.rx_crc_errors++;
1445  if (lsr & IRCC_LSR_SIZE_ERROR)
1446  self->netdev->stats.rx_length_errors++;
1447  if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1448  self->netdev->stats.rx_length_errors++;
1449  return;
1450  }
1451 
1452  /* Remove CRC */
1453  len -= self->io.speed < 4000000 ? 2 : 4;
1454 
1455  if (len < 2 || len > 2050) {
1456  IRDA_WARNING("%s(), bogus len=%d\n", __func__, len);
1457  return;
1458  }
1459  IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __func__, msgcnt, len);
1460 
1461  skb = dev_alloc_skb(len + 1);
1462  if (!skb) {
1463  IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1464  __func__);
1465  return;
1466  }
1467  /* Make sure IP header gets aligned */
1468  skb_reserve(skb, 1);
1469 
1470  memcpy(skb_put(skb, len), self->rx_buff.data, len);
1471  self->netdev->stats.rx_packets++;
1472  self->netdev->stats.rx_bytes += len;
1473 
1474  skb->dev = self->netdev;
1475  skb_reset_mac_header(skb);
1476  skb->protocol = htons(ETH_P_IRDA);
1477  netif_rx(skb);
1478 }
1479 
1480 /*
1481  * Function smsc_ircc_sir_receive (self)
1482  *
1483  * Receive one frame from the infrared port
1484  *
1485  */
1486 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1487 {
1488  int boguscount = 0;
1489  int iobase;
1490 
1491  IRDA_ASSERT(self != NULL, return;);
1492 
1493  iobase = self->io.sir_base;
1494 
1495  /*
1496  * Receive all characters in Rx FIFO, unwrap and unstuff them.
1497  * async_unwrap_char will deliver all found frames
1498  */
1499  do {
1500  async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff,
1501  inb(iobase + UART_RX));
1502 
1503  /* Make sure we don't stay here to long */
1504  if (boguscount++ > 32) {
1505  IRDA_DEBUG(2, "%s(), breaking!\n", __func__);
1506  break;
1507  }
1508  } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1509 }
1510 
1511 
1512 /*
1513  * Function smsc_ircc_interrupt (irq, dev_id, regs)
1514  *
1515  * An interrupt from the chip has arrived. Time to do some work
1516  *
1517  */
1518 static irqreturn_t smsc_ircc_interrupt(int dummy, void *dev_id)
1519 {
1520  struct net_device *dev = dev_id;
1521  struct smsc_ircc_cb *self = netdev_priv(dev);
1522  int iobase, iir, lcra, lsr;
1523  irqreturn_t ret = IRQ_NONE;
1524 
1525  /* Serialise the interrupt handler in various CPUs, stop Tx path */
1526  spin_lock(&self->lock);
1527 
1528  /* Check if we should use the SIR interrupt handler */
1529  if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1530  ret = smsc_ircc_interrupt_sir(dev);
1531  goto irq_ret_unlock;
1532  }
1533 
1534  iobase = self->io.fir_base;
1535 
1536  register_bank(iobase, 0);
1537  iir = inb(iobase + IRCC_IIR);
1538  if (iir == 0)
1539  goto irq_ret_unlock;
1540  ret = IRQ_HANDLED;
1541 
1542  /* Disable interrupts */
1543  outb(0, iobase + IRCC_IER);
1544  lcra = inb(iobase + IRCC_LCR_A);
1545  lsr = inb(iobase + IRCC_LSR);
1546 
1547  IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __func__, iir);
1548 
1549  if (iir & IRCC_IIR_EOM) {
1550  if (self->io.direction == IO_RECV)
1551  smsc_ircc_dma_receive_complete(self);
1552  else
1553  smsc_ircc_dma_xmit_complete(self);
1554 
1555  smsc_ircc_dma_receive(self);
1556  }
1557 
1558  if (iir & IRCC_IIR_ACTIVE_FRAME) {
1559  /*printk(KERN_WARNING "%s(): Active Frame\n", __func__);*/
1560  }
1561 
1562  /* Enable interrupts again */
1563 
1564  register_bank(iobase, 0);
1565  outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1566 
1567  irq_ret_unlock:
1568  spin_unlock(&self->lock);
1569 
1570  return ret;
1571 }
1572 
1573 /*
1574  * Function irport_interrupt_sir (irq, dev_id)
1575  *
1576  * Interrupt handler for SIR modes
1577  */
1578 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1579 {
1580  struct smsc_ircc_cb *self = netdev_priv(dev);
1581  int boguscount = 0;
1582  int iobase;
1583  int iir, lsr;
1584 
1585  /* Already locked coming here in smsc_ircc_interrupt() */
1586  /*spin_lock(&self->lock);*/
1587 
1588  iobase = self->io.sir_base;
1589 
1590  iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1591  if (iir == 0)
1592  return IRQ_NONE;
1593  while (iir) {
1594  /* Clear interrupt */
1595  lsr = inb(iobase + UART_LSR);
1596 
1597  IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1598  __func__, iir, lsr, iobase);
1599 
1600  switch (iir) {
1601  case UART_IIR_RLSI:
1602  IRDA_DEBUG(2, "%s(), RLSI\n", __func__);
1603  break;
1604  case UART_IIR_RDI:
1605  /* Receive interrupt */
1606  smsc_ircc_sir_receive(self);
1607  break;
1608  case UART_IIR_THRI:
1609  if (lsr & UART_LSR_THRE)
1610  /* Transmitter ready for data */
1611  smsc_ircc_sir_write_wakeup(self);
1612  break;
1613  default:
1614  IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1615  __func__, iir);
1616  break;
1617  }
1618 
1619  /* Make sure we don't stay here to long */
1620  if (boguscount++ > 100)
1621  break;
1622 
1623  iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1624  }
1625  /*spin_unlock(&self->lock);*/
1626  return IRQ_HANDLED;
1627 }
1628 
1629 
1630 #if 0 /* unused */
1631 /*
1632  * Function ircc_is_receiving (self)
1633  *
1634  * Return TRUE is we are currently receiving a frame
1635  *
1636  */
1637 static int ircc_is_receiving(struct smsc_ircc_cb *self)
1638 {
1639  int status = FALSE;
1640  /* int iobase; */
1641 
1642  IRDA_DEBUG(1, "%s\n", __func__);
1643 
1644  IRDA_ASSERT(self != NULL, return FALSE;);
1645 
1646  IRDA_DEBUG(0, "%s: dma count = %d\n", __func__,
1647  get_dma_residue(self->io.dma));
1648 
1649  status = (self->rx_buff.state != OUTSIDE_FRAME);
1650 
1651  return status;
1652 }
1653 #endif /* unused */
1654 
1655 static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
1656 {
1657  int error;
1658 
1659  error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
1660  self->netdev->name, self->netdev);
1661  if (error)
1662  IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n",
1663  __func__, self->io.irq, error);
1664 
1665  return error;
1666 }
1667 
1668 static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
1669 {
1670  unsigned long flags;
1671 
1672  spin_lock_irqsave(&self->lock, flags);
1673 
1674  self->io.speed = 0;
1675  smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1676 
1677  spin_unlock_irqrestore(&self->lock, flags);
1678 }
1679 
1680 static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
1681 {
1682  int iobase = self->io.fir_base;
1683  unsigned long flags;
1684 
1685  spin_lock_irqsave(&self->lock, flags);
1686 
1687  register_bank(iobase, 0);
1688  outb(0, iobase + IRCC_IER);
1689  outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1690  outb(0x00, iobase + IRCC_MASTER);
1691 
1692  spin_unlock_irqrestore(&self->lock, flags);
1693 }
1694 
1695 
1696 /*
1697  * Function smsc_ircc_net_open (dev)
1698  *
1699  * Start the device
1700  *
1701  */
1702 static int smsc_ircc_net_open(struct net_device *dev)
1703 {
1704  struct smsc_ircc_cb *self;
1705  char hwname[16];
1706 
1707  IRDA_DEBUG(1, "%s\n", __func__);
1708 
1709  IRDA_ASSERT(dev != NULL, return -1;);
1710  self = netdev_priv(dev);
1711  IRDA_ASSERT(self != NULL, return 0;);
1712 
1713  if (self->io.suspended) {
1714  IRDA_DEBUG(0, "%s(), device is suspended\n", __func__);
1715  return -EAGAIN;
1716  }
1717 
1718  if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1719  (void *) dev)) {
1720  IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1721  __func__, self->io.irq);
1722  return -EAGAIN;
1723  }
1724 
1725  smsc_ircc_start_interrupts(self);
1726 
1727  /* Give self a hardware name */
1728  /* It would be cool to offer the chip revision here - Jean II */
1729  sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1730 
1731  /*
1732  * Open new IrLAP layer instance, now that everything should be
1733  * initialized properly
1734  */
1735  self->irlap = irlap_open(dev, &self->qos, hwname);
1736 
1737  /*
1738  * Always allocate the DMA channel after the IRQ,
1739  * and clean up on failure.
1740  */
1741  if (request_dma(self->io.dma, dev->name)) {
1742  smsc_ircc_net_close(dev);
1743 
1744  IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1745  __func__, self->io.dma);
1746  return -EAGAIN;
1747  }
1748 
1749  netif_start_queue(dev);
1750 
1751  return 0;
1752 }
1753 
1754 /*
1755  * Function smsc_ircc_net_close (dev)
1756  *
1757  * Stop the device
1758  *
1759  */
1760 static int smsc_ircc_net_close(struct net_device *dev)
1761 {
1762  struct smsc_ircc_cb *self;
1763 
1764  IRDA_DEBUG(1, "%s\n", __func__);
1765 
1766  IRDA_ASSERT(dev != NULL, return -1;);
1767  self = netdev_priv(dev);
1768  IRDA_ASSERT(self != NULL, return 0;);
1769 
1770  /* Stop device */
1771  netif_stop_queue(dev);
1772 
1773  /* Stop and remove instance of IrLAP */
1774  if (self->irlap)
1775  irlap_close(self->irlap);
1776  self->irlap = NULL;
1777 
1778  smsc_ircc_stop_interrupts(self);
1779 
1780  /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1781  if (!self->io.suspended)
1782  free_irq(self->io.irq, dev);
1783 
1784  disable_dma(self->io.dma);
1785  free_dma(self->io.dma);
1786 
1787  return 0;
1788 }
1789 
1790 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1791 {
1792  struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1793 
1794  if (!self->io.suspended) {
1795  IRDA_DEBUG(1, "%s, Suspending\n", driver_name);
1796 
1797  rtnl_lock();
1798  if (netif_running(self->netdev)) {
1799  netif_device_detach(self->netdev);
1800  smsc_ircc_stop_interrupts(self);
1801  free_irq(self->io.irq, self->netdev);
1802  disable_dma(self->io.dma);
1803  }
1804  self->io.suspended = 1;
1805  rtnl_unlock();
1806  }
1807 
1808  return 0;
1809 }
1810 
1811 static int smsc_ircc_resume(struct platform_device *dev)
1812 {
1813  struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1814 
1815  if (self->io.suspended) {
1816  IRDA_DEBUG(1, "%s, Waking up\n", driver_name);
1817 
1818  rtnl_lock();
1819  smsc_ircc_init_chip(self);
1820  if (netif_running(self->netdev)) {
1821  if (smsc_ircc_request_irq(self)) {
1822  /*
1823  * Don't fail resume process, just kill this
1824  * network interface
1825  */
1826  unregister_netdevice(self->netdev);
1827  } else {
1828  enable_dma(self->io.dma);
1829  smsc_ircc_start_interrupts(self);
1830  netif_device_attach(self->netdev);
1831  }
1832  }
1833  self->io.suspended = 0;
1834  rtnl_unlock();
1835  }
1836  return 0;
1837 }
1838 
1839 /*
1840  * Function smsc_ircc_close (self)
1841  *
1842  * Close driver instance
1843  *
1844  */
1845 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1846 {
1847  IRDA_DEBUG(1, "%s\n", __func__);
1848 
1849  IRDA_ASSERT(self != NULL, return -1;);
1850 
1851  platform_device_unregister(self->pldev);
1852 
1853  /* Remove netdevice */
1854  unregister_netdev(self->netdev);
1855 
1856  smsc_ircc_stop_interrupts(self);
1857 
1858  /* Release the PORTS that this driver is using */
1859  IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__,
1860  self->io.fir_base);
1861 
1862  release_region(self->io.fir_base, self->io.fir_ext);
1863 
1864  IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__,
1865  self->io.sir_base);
1866 
1867  release_region(self->io.sir_base, self->io.sir_ext);
1868 
1869  if (self->tx_buff.head)
1870  dma_free_coherent(NULL, self->tx_buff.truesize,
1871  self->tx_buff.head, self->tx_buff_dma);
1872 
1873  if (self->rx_buff.head)
1874  dma_free_coherent(NULL, self->rx_buff.truesize,
1875  self->rx_buff.head, self->rx_buff_dma);
1876 
1877  free_netdev(self->netdev);
1878 
1879  return 0;
1880 }
1881 
1882 static void __exit smsc_ircc_cleanup(void)
1883 {
1884  int i;
1885 
1886  IRDA_DEBUG(1, "%s\n", __func__);
1887 
1888  for (i = 0; i < 2; i++) {
1889  if (dev_self[i])
1890  smsc_ircc_close(dev_self[i]);
1891  }
1892 
1893  if (pnp_driver_registered)
1894  pnp_unregister_driver(&smsc_ircc_pnp_driver);
1895 
1896  platform_driver_unregister(&smsc_ircc_driver);
1897 }
1898 
1899 /*
1900  * Start SIR operations
1901  *
1902  * This function *must* be called with spinlock held, because it may
1903  * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1904  */
1905 static void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1906 {
1907  struct net_device *dev;
1908  int fir_base, sir_base;
1909 
1910  IRDA_DEBUG(3, "%s\n", __func__);
1911 
1912  IRDA_ASSERT(self != NULL, return;);
1913  dev = self->netdev;
1914  IRDA_ASSERT(dev != NULL, return;);
1915 
1916  fir_base = self->io.fir_base;
1917  sir_base = self->io.sir_base;
1918 
1919  /* Reset everything */
1920  outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1921 
1922  #if SMSC_IRCC2_C_SIR_STOP
1923  /*smsc_ircc_sir_stop(self);*/
1924  #endif
1925 
1926  register_bank(fir_base, 1);
1927  outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1928 
1929  /* Initialize UART */
1930  outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1931  outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
1932 
1933  /* Turn on interrups */
1934  outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1935 
1936  IRDA_DEBUG(3, "%s() - exit\n", __func__);
1937 
1938  outb(0x00, fir_base + IRCC_MASTER);
1939 }
1940 
1941 #if SMSC_IRCC2_C_SIR_STOP
1942 void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1943 {
1944  int iobase;
1945 
1946  IRDA_DEBUG(3, "%s\n", __func__);
1947  iobase = self->io.sir_base;
1948 
1949  /* Reset UART */
1950  outb(0, iobase + UART_MCR);
1951 
1952  /* Turn off interrupts */
1953  outb(0, iobase + UART_IER);
1954 }
1955 #endif
1956 
1957 /*
1958  * Function smsc_sir_write_wakeup (self)
1959  *
1960  * Called by the SIR interrupt handler when there's room for more data.
1961  * If we have more packets to send, we send them here.
1962  *
1963  */
1964 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1965 {
1966  int actual = 0;
1967  int iobase;
1968  int fcr;
1969 
1970  IRDA_ASSERT(self != NULL, return;);
1971 
1972  IRDA_DEBUG(4, "%s\n", __func__);
1973 
1974  iobase = self->io.sir_base;
1975 
1976  /* Finished with frame? */
1977  if (self->tx_buff.len > 0) {
1978  /* Write data left in transmit buffer */
1979  actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1980  self->tx_buff.data, self->tx_buff.len);
1981  self->tx_buff.data += actual;
1982  self->tx_buff.len -= actual;
1983  } else {
1984 
1985  /*if (self->tx_buff.len ==0) {*/
1986 
1987  /*
1988  * Now serial buffer is almost free & we can start
1989  * transmission of another packet. But first we must check
1990  * if we need to change the speed of the hardware
1991  */
1992  if (self->new_speed) {
1993  IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1994  __func__, self->new_speed);
1995  smsc_ircc_sir_wait_hw_transmitter_finish(self);
1996  smsc_ircc_change_speed(self, self->new_speed);
1997  self->new_speed = 0;
1998  } else {
1999  /* Tell network layer that we want more frames */
2000  netif_wake_queue(self->netdev);
2001  }
2002  self->netdev->stats.tx_packets++;
2003 
2004  if (self->io.speed <= 115200) {
2005  /*
2006  * Reset Rx FIFO to make sure that all reflected transmit data
2007  * is discarded. This is needed for half duplex operation
2008  */
2009  fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
2010  fcr |= self->io.speed < 38400 ?
2011  UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
2012 
2013  outb(fcr, iobase + UART_FCR);
2014 
2015  /* Turn on receive interrupts */
2016  outb(UART_IER_RDI, iobase + UART_IER);
2017  }
2018  }
2019 }
2020 
2021 /*
2022  * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
2023  *
2024  * Fill Tx FIFO with transmit data
2025  *
2026  */
2027 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
2028 {
2029  int actual = 0;
2030 
2031  /* Tx FIFO should be empty! */
2032  if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
2033  IRDA_WARNING("%s(), failed, fifo not empty!\n", __func__);
2034  return 0;
2035  }
2036 
2037  /* Fill FIFO with current frame */
2038  while (fifo_size-- > 0 && actual < len) {
2039  /* Transmit next byte */
2040  outb(buf[actual], iobase + UART_TX);
2041  actual++;
2042  }
2043  return actual;
2044 }
2045 
2046 /*
2047  * Function smsc_ircc_is_receiving (self)
2048  *
2049  * Returns true is we are currently receiving data
2050  *
2051  */
2052 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
2053 {
2054  return self->rx_buff.state != OUTSIDE_FRAME;
2055 }
2056 
2057 
2058 /*
2059  * Function smsc_ircc_probe_transceiver(self)
2060  *
2061  * Tries to find the used Transceiver
2062  *
2063  */
2064 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
2065 {
2066  unsigned int i;
2067 
2068  IRDA_ASSERT(self != NULL, return;);
2069 
2070  for (i = 0; smsc_transceivers[i].name != NULL; i++)
2071  if (smsc_transceivers[i].probe(self->io.fir_base)) {
2072  IRDA_MESSAGE(" %s transceiver found\n",
2073  smsc_transceivers[i].name);
2074  self->transceiver= i + 1;
2075  return;
2076  }
2077 
2078  IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
2079  smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
2080 
2081  self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
2082 }
2083 
2084 
2085 /*
2086  * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2087  *
2088  * Set the transceiver according to the speed
2089  *
2090  */
2091 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
2092 {
2093  unsigned int trx;
2094 
2095  trx = self->transceiver;
2096  if (trx > 0)
2097  smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
2098 }
2099 
2100 /*
2101  * Function smsc_ircc_wait_hw_transmitter_finish ()
2102  *
2103  * Wait for the real end of HW transmission
2104  *
2105  * The UART is a strict FIFO, and we get called only when we have finished
2106  * pushing data to the FIFO, so the maximum amount of time we must wait
2107  * is only for the FIFO to drain out.
2108  *
2109  * We use a simple calibrated loop. We may need to adjust the loop
2110  * delay (udelay) to balance I/O traffic and latency. And we also need to
2111  * adjust the maximum timeout.
2112  * It would probably be better to wait for the proper interrupt,
2113  * but it doesn't seem to be available.
2114  *
2115  * We can't use jiffies or kernel timers because :
2116  * 1) We are called from the interrupt handler, which disable softirqs,
2117  * so jiffies won't be increased
2118  * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2119  * want to wait that long to detect stuck hardware.
2120  * Jean II
2121  */
2122 
2123 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
2124 {
2125  int iobase = self->io.sir_base;
2126  int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
2127 
2128  /* Calibrated busy loop */
2129  while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
2130  udelay(1);
2131 
2132  if (count < 0)
2133  IRDA_DEBUG(0, "%s(): stuck transmitter\n", __func__);
2134 }
2135 
2136 
2137 /* PROBING
2138  *
2139  * REVISIT we can be told about the device by PNP, and should use that info
2140  * instead of probing hardware and creating a platform_device ...
2141  */
2142 
2143 static int __init smsc_ircc_look_for_chips(void)
2144 {
2145  struct smsc_chip_address *address;
2146  char *type;
2147  unsigned int cfg_base, found;
2148 
2149  found = 0;
2150  address = possible_addresses;
2151 
2152  while (address->cfg_base) {
2153  cfg_base = address->cfg_base;
2154 
2155  /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __func__, cfg_base, address->type);*/
2156 
2157  if (address->type & SMSCSIO_TYPE_FDC) {
2158  type = "FDC";
2159  if (address->type & SMSCSIO_TYPE_FLAT)
2160  if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2161  found++;
2162 
2163  if (address->type & SMSCSIO_TYPE_PAGED)
2164  if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2165  found++;
2166  }
2167  if (address->type & SMSCSIO_TYPE_LPC) {
2168  type = "LPC";
2169  if (address->type & SMSCSIO_TYPE_FLAT)
2170  if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2171  found++;
2172 
2173  if (address->type & SMSCSIO_TYPE_PAGED)
2174  if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2175  found++;
2176  }
2177  address++;
2178  }
2179  return found;
2180 }
2181 
2182 /*
2183  * Function smsc_superio_flat (chip, base, type)
2184  *
2185  * Try to get configuration of a smc SuperIO chip with flat register model
2186  *
2187  */
2188 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
2189 {
2190  unsigned short firbase, sirbase;
2191  u8 mode, dma, irq;
2192  int ret = -ENODEV;
2193 
2194  IRDA_DEBUG(1, "%s\n", __func__);
2195 
2196  if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
2197  return ret;
2198 
2199  outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
2200  mode = inb(cfgbase + 1);
2201 
2202  /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __func__, mode);*/
2203 
2204  if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
2205  IRDA_WARNING("%s(): IrDA not enabled\n", __func__);
2206 
2207  outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
2208  sirbase = inb(cfgbase + 1) << 2;
2209 
2210  /* FIR iobase */
2211  outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
2212  firbase = inb(cfgbase + 1) << 3;
2213 
2214  /* DMA */
2215  outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
2216  dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
2217 
2218  /* IRQ */
2219  outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
2220  irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2221 
2222  IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __func__, firbase, sirbase, dma, irq, mode);
2223 
2224  if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2225  ret = 0;
2226 
2227  /* Exit configuration */
2228  outb(SMSCSIO_CFGEXITKEY, cfgbase);
2229 
2230  return ret;
2231 }
2232 
2233 /*
2234  * Function smsc_superio_paged (chip, base, type)
2235  *
2236  * Try to get configuration of a smc SuperIO chip with paged register model
2237  *
2238  */
2239 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
2240 {
2241  unsigned short fir_io, sir_io;
2242  int ret = -ENODEV;
2243 
2244  IRDA_DEBUG(1, "%s\n", __func__);
2245 
2246  if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
2247  return ret;
2248 
2249  /* Select logical device (UART2) */
2250  outb(0x07, cfg_base);
2251  outb(0x05, cfg_base + 1);
2252 
2253  /* SIR iobase */
2254  outb(0x60, cfg_base);
2255  sir_io = inb(cfg_base + 1) << 8;
2256  outb(0x61, cfg_base);
2257  sir_io |= inb(cfg_base + 1);
2258 
2259  /* Read FIR base */
2260  outb(0x62, cfg_base);
2261  fir_io = inb(cfg_base + 1) << 8;
2262  outb(0x63, cfg_base);
2263  fir_io |= inb(cfg_base + 1);
2264  outb(0x2b, cfg_base); /* ??? */
2265 
2266  if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2267  ret = 0;
2268 
2269  /* Exit configuration */
2270  outb(SMSCSIO_CFGEXITKEY, cfg_base);
2271 
2272  return ret;
2273 }
2274 
2275 
2276 static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
2277 {
2278  IRDA_DEBUG(1, "%s\n", __func__);
2279 
2280  outb(reg, cfg_base);
2281  return inb(cfg_base) != reg ? -1 : 0;
2282 }
2283 
2284 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
2285 {
2286  u8 devid, xdevid, rev;
2287 
2288  IRDA_DEBUG(1, "%s\n", __func__);
2289 
2290  /* Leave configuration */
2291 
2292  outb(SMSCSIO_CFGEXITKEY, cfg_base);
2293 
2294  if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2295  return NULL;
2296 
2297  outb(reg, cfg_base);
2298 
2299  xdevid = inb(cfg_base + 1);
2300 
2301  /* Enter configuration */
2302 
2303  outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2304 
2305  #if 0
2306  if (smsc_access(cfg_base,0x55)) /* send second key and check */
2307  return NULL;
2308  #endif
2309 
2310  /* probe device ID */
2311 
2312  if (smsc_access(cfg_base, reg))
2313  return NULL;
2314 
2315  devid = inb(cfg_base + 1);
2316 
2317  if (devid == 0 || devid == 0xff) /* typical values for unused port */
2318  return NULL;
2319 
2320  /* probe revision ID */
2321 
2322  if (smsc_access(cfg_base, reg + 1))
2323  return NULL;
2324 
2325  rev = inb(cfg_base + 1);
2326 
2327  if (rev >= 128) /* i think this will make no sense */
2328  return NULL;
2329 
2330  if (devid == xdevid) /* protection against false positives */
2331  return NULL;
2332 
2333  /* Check for expected device ID; are there others? */
2334 
2335  while (chip->devid != devid) {
2336 
2337  chip++;
2338 
2339  if (chip->name == NULL)
2340  return NULL;
2341  }
2342 
2343  IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2344  devid, rev, cfg_base, type, chip->name);
2345 
2346  if (chip->rev > rev) {
2347  IRDA_MESSAGE("Revision higher than expected\n");
2348  return NULL;
2349  }
2350 
2351  if (chip->flags & NoIRDA)
2352  IRDA_MESSAGE("chipset does not support IRDA\n");
2353 
2354  return chip;
2355 }
2356 
2357 static int __init smsc_superio_fdc(unsigned short cfg_base)
2358 {
2359  int ret = -1;
2360 
2361  if (!request_region(cfg_base, 2, driver_name)) {
2362  IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2363  __func__, cfg_base);
2364  } else {
2365  if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2366  !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
2367  ret = 0;
2368 
2369  release_region(cfg_base, 2);
2370  }
2371 
2372  return ret;
2373 }
2374 
2375 static int __init smsc_superio_lpc(unsigned short cfg_base)
2376 {
2377  int ret = -1;
2378 
2379  if (!request_region(cfg_base, 2, driver_name)) {
2380  IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2381  __func__, cfg_base);
2382  } else {
2383  if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2384  !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
2385  ret = 0;
2386 
2387  release_region(cfg_base, 2);
2388  }
2389  return ret;
2390 }
2391 
2392 /*
2393  * Look for some specific subsystem setups that need
2394  * pre-configuration not properly done by the BIOS (especially laptops)
2395  * This code is based in part on smcinit.c, tosh1800-smcinit.c
2396  * and tosh2450-smcinit.c. The table lists the device entries
2397  * for ISA bridges with an LPC (Low Pin Count) controller which
2398  * handles the communication with the SMSC device. After the LPC
2399  * controller is initialized through PCI, the SMSC device is initialized
2400  * through a dedicated port in the ISA port-mapped I/O area, this latter
2401  * area is used to configure the SMSC device with default
2402  * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
2403  * used different sets of parameters and different control port
2404  * addresses making a subsystem device table necessary.
2405  */
2406 #ifdef CONFIG_PCI
2407 static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = {
2408  /*
2409  * Subsystems needing entries:
2410  * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family
2411  * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family
2412  * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family
2413  */
2414  {
2415  /* Guessed entry */
2416  .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2417  .device = 0x24cc,
2418  .subvendor = 0x103c,
2419  .subdevice = 0x08bc,
2420  .sir_io = 0x02f8,
2421  .fir_io = 0x0130,
2422  .fir_irq = 0x05,
2423  .fir_dma = 0x03,
2424  .cfg_base = 0x004e,
2425  .preconfigure = preconfigure_through_82801,
2426  .name = "HP nx5000 family",
2427  },
2428  {
2429  .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2430  .device = 0x24cc,
2431  .subvendor = 0x103c,
2432  .subdevice = 0x088c,
2433  /* Quite certain these are the same for nc8000 as for nc6000 */
2434  .sir_io = 0x02f8,
2435  .fir_io = 0x0130,
2436  .fir_irq = 0x05,
2437  .fir_dma = 0x03,
2438  .cfg_base = 0x004e,
2439  .preconfigure = preconfigure_through_82801,
2440  .name = "HP nc8000 family",
2441  },
2442  {
2443  .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2444  .device = 0x24cc,
2445  .subvendor = 0x103c,
2446  .subdevice = 0x0890,
2447  .sir_io = 0x02f8,
2448  .fir_io = 0x0130,
2449  .fir_irq = 0x05,
2450  .fir_dma = 0x03,
2451  .cfg_base = 0x004e,
2452  .preconfigure = preconfigure_through_82801,
2453  .name = "HP nc6000 family",
2454  },
2455  {
2456  .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2457  .device = 0x24cc,
2458  .subvendor = 0x0e11,
2459  .subdevice = 0x0860,
2460  /* I assume these are the same for x1000 as for the others */
2461  .sir_io = 0x02e8,
2462  .fir_io = 0x02f8,
2463  .fir_irq = 0x07,
2464  .fir_dma = 0x03,
2465  .cfg_base = 0x002e,
2466  .preconfigure = preconfigure_through_82801,
2467  .name = "Compaq x1000 family",
2468  },
2469  {
2470  /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
2471  .vendor = PCI_VENDOR_ID_INTEL,
2472  .device = 0x24c0,
2473  .subvendor = 0x1179,
2474  .subdevice = 0xffff, /* 0xffff is "any" */
2475  .sir_io = 0x03f8,
2476  .fir_io = 0x0130,
2477  .fir_irq = 0x07,
2478  .fir_dma = 0x01,
2479  .cfg_base = 0x002e,
2480  .preconfigure = preconfigure_through_82801,
2481  .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
2482  },
2483  {
2484  .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801CAM ISA bridge */
2485  .device = 0x248c,
2486  .subvendor = 0x1179,
2487  .subdevice = 0xffff, /* 0xffff is "any" */
2488  .sir_io = 0x03f8,
2489  .fir_io = 0x0130,
2490  .fir_irq = 0x03,
2491  .fir_dma = 0x03,
2492  .cfg_base = 0x002e,
2493  .preconfigure = preconfigure_through_82801,
2494  .name = "Toshiba laptop with Intel 82801CAM ISA bridge",
2495  },
2496  {
2497  /* 82801DBM (ICH4-M) LPC Interface Bridge */
2498  .vendor = PCI_VENDOR_ID_INTEL,
2499  .device = 0x24cc,
2500  .subvendor = 0x1179,
2501  .subdevice = 0xffff, /* 0xffff is "any" */
2502  .sir_io = 0x03f8,
2503  .fir_io = 0x0130,
2504  .fir_irq = 0x03,
2505  .fir_dma = 0x03,
2506  .cfg_base = 0x002e,
2507  .preconfigure = preconfigure_through_82801,
2508  .name = "Toshiba laptop with Intel 8281DBM LPC bridge",
2509  },
2510  {
2511  /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
2512  .vendor = PCI_VENDOR_ID_AL,
2513  .device = 0x1533,
2514  .subvendor = 0x1179,
2515  .subdevice = 0xffff, /* 0xffff is "any" */
2516  .sir_io = 0x02e8,
2517  .fir_io = 0x02f8,
2518  .fir_irq = 0x07,
2519  .fir_dma = 0x03,
2520  .cfg_base = 0x002e,
2521  .preconfigure = preconfigure_through_ali,
2522  .name = "Toshiba laptop with ALi ISA bridge",
2523  },
2524  { } // Terminator
2525 };
2526 
2527 
2528 /*
2529  * This sets up the basic SMSC parameters
2530  * (FIR port, SIR port, FIR DMA, FIR IRQ)
2531  * through the chip configuration port.
2532  */
2533 static int __init preconfigure_smsc_chip(struct
2534  smsc_ircc_subsystem_configuration
2535  *conf)
2536 {
2537  unsigned short iobase = conf->cfg_base;
2538  unsigned char tmpbyte;
2539 
2540  outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2541  outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2542  tmpbyte = inb(iobase +1); // Read device ID
2543  IRDA_DEBUG(0,
2544  "Detected Chip id: 0x%02x, setting up registers...\n",
2545  tmpbyte);
2546 
2547  /* Disable UART1 and set up SIR I/O port */
2548  outb(0x24, iobase); // select CR24 - UART1 base addr
2549  outb(0x00, iobase + 1); // disable UART1
2550  outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr
2551  outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2552  tmpbyte = inb(iobase + 1);
2553  if (tmpbyte != (conf->sir_io >> 2) ) {
2554  IRDA_WARNING("ERROR: could not configure SIR ioport.\n");
2555  IRDA_WARNING("Try to supply ircc_cfg argument.\n");
2556  return -ENXIO;
2557  }
2558 
2559  /* Set up FIR IRQ channel for UART2 */
2560  outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2561  tmpbyte = inb(iobase + 1);
2562  tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
2563  tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
2564  outb(tmpbyte, iobase + 1);
2565  tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2566  if (tmpbyte != conf->fir_irq) {
2567  IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n");
2568  return -ENXIO;
2569  }
2570 
2571  /* Set up FIR I/O port */
2572  outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr
2573  outb((conf->fir_io >> 3), iobase + 1);
2574  tmpbyte = inb(iobase + 1);
2575  if (tmpbyte != (conf->fir_io >> 3) ) {
2576  IRDA_WARNING("ERROR: could not configure FIR I/O port.\n");
2577  return -ENXIO;
2578  }
2579 
2580  /* Set up FIR DMA channel */
2581  outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select
2582  outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2583  tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2584  if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
2585  IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n");
2586  return -ENXIO;
2587  }
2588 
2589  outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode
2590  tmpbyte = inb(iobase + 1);
2591  tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK |
2592  SMSCSIOFLAT_UART2MODE_VAL_IRDA;
2593  outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2594 
2595  outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel
2596  tmpbyte = inb(iobase + 1);
2597  outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2598 
2599  /* This one was not part of tosh1800 */
2600  outb(0x0a, iobase); // CR0a - ecp fifo / ir mux
2601  tmpbyte = inb(iobase + 1);
2602  outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2603 
2604  outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power
2605  tmpbyte = inb(iobase + 1);
2606  outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2607 
2608  outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle
2609  tmpbyte = inb(iobase + 1);
2610  outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2611 
2612  outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration
2613 
2614  return 0;
2615 }
2616 
2617 /* 82801CAM generic registers */
2618 #define VID 0x00
2619 #define DID 0x02
2620 #define PIRQ_A_D_ROUT 0x60
2621 #define SIRQ_CNTL 0x64
2622 #define PIRQ_E_H_ROUT 0x68
2623 #define PCI_DMA_C 0x90
2624 /* LPC-specific registers */
2625 #define COM_DEC 0xe0
2626 #define GEN1_DEC 0xe4
2627 #define LPC_EN 0xe6
2628 #define GEN2_DEC 0xec
2629 /*
2630  * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2631  * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2632  * They all work the same way!
2633  */
2634 static int __init preconfigure_through_82801(struct pci_dev *dev,
2635  struct
2636  smsc_ircc_subsystem_configuration
2637  *conf)
2638 {
2639  unsigned short tmpword;
2640  unsigned char tmpbyte;
2641 
2642  IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n");
2643  /*
2644  * Select the range for the COMA COM port (SIR)
2645  * Register COM_DEC:
2646  * Bit 7: reserved
2647  * Bit 6-4, COMB decode range
2648  * Bit 3: reserved
2649  * Bit 2-0, COMA decode range
2650  *
2651  * Decode ranges:
2652  * 000 = 0x3f8-0x3ff (COM1)
2653  * 001 = 0x2f8-0x2ff (COM2)
2654  * 010 = 0x220-0x227
2655  * 011 = 0x228-0x22f
2656  * 100 = 0x238-0x23f
2657  * 101 = 0x2e8-0x2ef (COM4)
2658  * 110 = 0x338-0x33f
2659  * 111 = 0x3e8-0x3ef (COM3)
2660  */
2661  pci_read_config_byte(dev, COM_DEC, &tmpbyte);
2662  tmpbyte &= 0xf8; /* mask COMA bits */
2663  switch(conf->sir_io) {
2664  case 0x3f8:
2665  tmpbyte |= 0x00;
2666  break;
2667  case 0x2f8:
2668  tmpbyte |= 0x01;
2669  break;
2670  case 0x220:
2671  tmpbyte |= 0x02;
2672  break;
2673  case 0x228:
2674  tmpbyte |= 0x03;
2675  break;
2676  case 0x238:
2677  tmpbyte |= 0x04;
2678  break;
2679  case 0x2e8:
2680  tmpbyte |= 0x05;
2681  break;
2682  case 0x338:
2683  tmpbyte |= 0x06;
2684  break;
2685  case 0x3e8:
2686  tmpbyte |= 0x07;
2687  break;
2688  default:
2689  tmpbyte |= 0x01; /* COM2 default */
2690  }
2691  IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte);
2692  pci_write_config_byte(dev, COM_DEC, tmpbyte);
2693 
2694  /* Enable Low Pin Count interface */
2695  pci_read_config_word(dev, LPC_EN, &tmpword);
2696  /* These seem to be set up at all times,
2697  * just make sure it is properly set.
2698  */
2699  switch(conf->cfg_base) {
2700  case 0x04e:
2701  tmpword |= 0x2000;
2702  break;
2703  case 0x02e:
2704  tmpword |= 0x1000;
2705  break;
2706  case 0x062:
2707  tmpword |= 0x0800;
2708  break;
2709  case 0x060:
2710  tmpword |= 0x0400;
2711  break;
2712  default:
2713  IRDA_WARNING("Uncommon I/O base address: 0x%04x\n",
2714  conf->cfg_base);
2715  break;
2716  }
2717  tmpword &= 0xfffd; /* disable LPC COMB */
2718  tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
2719  IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword);
2720  pci_write_config_word(dev, LPC_EN, tmpword);
2721 
2722  /*
2723  * Configure LPC DMA channel
2724  * PCI_DMA_C bits:
2725  * Bit 15-14: DMA channel 7 select
2726  * Bit 13-12: DMA channel 6 select
2727  * Bit 11-10: DMA channel 5 select
2728  * Bit 9-8: Reserved
2729  * Bit 7-6: DMA channel 3 select
2730  * Bit 5-4: DMA channel 2 select
2731  * Bit 3-2: DMA channel 1 select
2732  * Bit 1-0: DMA channel 0 select
2733  * 00 = Reserved value
2734  * 01 = PC/PCI DMA
2735  * 10 = Reserved value
2736  * 11 = LPC I/F DMA
2737  */
2738  pci_read_config_word(dev, PCI_DMA_C, &tmpword);
2739  switch(conf->fir_dma) {
2740  case 0x07:
2741  tmpword |= 0xc000;
2742  break;
2743  case 0x06:
2744  tmpword |= 0x3000;
2745  break;
2746  case 0x05:
2747  tmpword |= 0x0c00;
2748  break;
2749  case 0x03:
2750  tmpword |= 0x00c0;
2751  break;
2752  case 0x02:
2753  tmpword |= 0x0030;
2754  break;
2755  case 0x01:
2756  tmpword |= 0x000c;
2757  break;
2758  case 0x00:
2759  tmpword |= 0x0003;
2760  break;
2761  default:
2762  break; /* do not change settings */
2763  }
2764  IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword);
2765  pci_write_config_word(dev, PCI_DMA_C, tmpword);
2766 
2767  /*
2768  * GEN2_DEC bits:
2769  * Bit 15-4: Generic I/O range
2770  * Bit 3-1: reserved (read as 0)
2771  * Bit 0: enable GEN2 range on LPC I/F
2772  */
2773  tmpword = conf->fir_io & 0xfff8;
2774  tmpword |= 0x0001;
2775  IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword);
2776  pci_write_config_word(dev, GEN2_DEC, tmpword);
2777 
2778  /* Pre-configure chip */
2779  return preconfigure_smsc_chip(conf);
2780 }
2781 
2782 /*
2783  * Pre-configure a certain port on the ALi 1533 bridge.
2784  * This is based on reverse-engineering since ALi does not
2785  * provide any data sheet for the 1533 chip.
2786  */
2787 static void __init preconfigure_ali_port(struct pci_dev *dev,
2788  unsigned short port)
2789 {
2790  unsigned char reg;
2791  /* These bits obviously control the different ports */
2792  unsigned char mask;
2793  unsigned char tmpbyte;
2794 
2795  switch(port) {
2796  case 0x0130:
2797  case 0x0178:
2798  reg = 0xb0;
2799  mask = 0x80;
2800  break;
2801  case 0x03f8:
2802  reg = 0xb4;
2803  mask = 0x80;
2804  break;
2805  case 0x02f8:
2806  reg = 0xb4;
2807  mask = 0x30;
2808  break;
2809  case 0x02e8:
2810  reg = 0xb4;
2811  mask = 0x08;
2812  break;
2813  default:
2814  IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port);
2815  return;
2816  }
2817 
2818  pci_read_config_byte(dev, reg, &tmpbyte);
2819  /* Turn on the right bits */
2820  tmpbyte |= mask;
2821  pci_write_config_byte(dev, reg, tmpbyte);
2822  IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port);
2823 }
2824 
2825 static int __init preconfigure_through_ali(struct pci_dev *dev,
2826  struct
2827  smsc_ircc_subsystem_configuration
2828  *conf)
2829 {
2830  /* Configure the two ports on the ALi 1533 */
2831  preconfigure_ali_port(dev, conf->sir_io);
2832  preconfigure_ali_port(dev, conf->fir_io);
2833 
2834  /* Pre-configure chip */
2835  return preconfigure_smsc_chip(conf);
2836 }
2837 
2838 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
2839  unsigned short ircc_fir,
2840  unsigned short ircc_sir,
2841  unsigned char ircc_dma,
2842  unsigned char ircc_irq)
2843 {
2844  struct pci_dev *dev = NULL;
2845  unsigned short ss_vendor = 0x0000;
2846  unsigned short ss_device = 0x0000;
2847  int ret = 0;
2848 
2849  for_each_pci_dev(dev) {
2850  struct smsc_ircc_subsystem_configuration *conf;
2851 
2852  /*
2853  * Cache the subsystem vendor/device:
2854  * some manufacturers fail to set this for all components,
2855  * so we save it in case there is just 0x0000 0x0000 on the
2856  * device we want to check.
2857  */
2858  if (dev->subsystem_vendor != 0x0000U) {
2859  ss_vendor = dev->subsystem_vendor;
2860  ss_device = dev->subsystem_device;
2861  }
2862  conf = subsystem_configurations;
2863  for( ; conf->subvendor; conf++) {
2864  if(conf->vendor == dev->vendor &&
2865  conf->device == dev->device &&
2866  conf->subvendor == ss_vendor &&
2867  /* Sometimes these are cached values */
2868  (conf->subdevice == ss_device ||
2869  conf->subdevice == 0xffff)) {
2870  struct smsc_ircc_subsystem_configuration
2871  tmpconf;
2872 
2873  memcpy(&tmpconf, conf,
2874  sizeof(struct smsc_ircc_subsystem_configuration));
2875 
2876  /*
2877  * Override the default values with anything
2878  * passed in as parameter
2879  */
2880  if (ircc_cfg != 0)
2881  tmpconf.cfg_base = ircc_cfg;
2882  if (ircc_fir != 0)
2883  tmpconf.fir_io = ircc_fir;
2884  if (ircc_sir != 0)
2885  tmpconf.sir_io = ircc_sir;
2886  if (ircc_dma != DMA_INVAL)
2887  tmpconf.fir_dma = ircc_dma;
2888  if (ircc_irq != IRQ_INVAL)
2889  tmpconf.fir_irq = ircc_irq;
2890 
2891  IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name);
2892  if (conf->preconfigure)
2893  ret = conf->preconfigure(dev, &tmpconf);
2894  else
2895  ret = -ENODEV;
2896  }
2897  }
2898  }
2899 
2900  return ret;
2901 }
2902 #endif // CONFIG_PCI
2903 
2904 /************************************************
2905  *
2906  * Transceivers specific functions
2907  *
2908  ************************************************/
2909 
2910 
2911 /*
2912  * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2913  *
2914  * Program transceiver through smsc-ircc ATC circuitry
2915  *
2916  */
2917 
2918 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2919 {
2920  unsigned long jiffies_now, jiffies_timeout;
2921  u8 val;
2922 
2923  jiffies_now = jiffies;
2924  jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
2925 
2926  /* ATC */
2927  register_bank(fir_base, 4);
2928  outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2929  fir_base + IRCC_ATC);
2930 
2931  while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2932  !time_after(jiffies, jiffies_timeout))
2933  /* empty */;
2934 
2935  if (val)
2936  IRDA_WARNING("%s(): ATC: 0x%02x\n", __func__,
2937  inb(fir_base + IRCC_ATC));
2938 }
2939 
2940 /*
2941  * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2942  *
2943  * Probe transceiver smsc-ircc ATC circuitry
2944  *
2945  */
2946 
2947 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2948 {
2949  return 0;
2950 }
2951 
2952 /*
2953  * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2954  *
2955  * Set transceiver
2956  *
2957  */
2958 
2959 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2960 {
2961  u8 fast_mode;
2962 
2963  switch (speed) {
2964  default:
2965  case 576000 :
2966  fast_mode = 0;
2967  break;
2968  case 1152000 :
2969  case 4000000 :
2970  fast_mode = IRCC_LCR_A_FAST;
2971  break;
2972  }
2973  register_bank(fir_base, 0);
2974  outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
2975 }
2976 
2977 /*
2978  * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2979  *
2980  * Probe transceiver
2981  *
2982  */
2983 
2984 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2985 {
2986  return 0;
2987 }
2988 
2989 /*
2990  * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2991  *
2992  * Set transceiver
2993  *
2994  */
2995 
2996 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2997 {
2998  u8 fast_mode;
2999 
3000  switch (speed) {
3001  default:
3002  case 576000 :
3003  fast_mode = 0;
3004  break;
3005  case 1152000 :
3006  case 4000000 :
3007  fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
3008  break;
3009 
3010  }
3011  /* This causes an interrupt */
3012  register_bank(fir_base, 0);
3013  outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
3014 }
3015 
3016 /*
3017  * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
3018  *
3019  * Probe transceiver
3020  *
3021  */
3022 
3023 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
3024 {
3025  return 0;
3026 }
3027 
3028 
3029 module_init(smsc_ircc_init);
3030 module_exit(smsc_ircc_cleanup);
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