#include <R600InstrInfo.h>
Detailed Description
Definition at line 32 of file R600InstrInfo.h.
Member Enumeration Documentation
- Enumerator:
ALU_VEC_012_SCL_210 ALU_VEC_021_SCL_122 ALU_VEC_120_SCL_212 ALU_VEC_102_SCL_221 ALU_VEC_201 ALU_VEC_210
Definition at line 52 of file R600InstrInfo.h.
Constructor & Destructor Documentation
| R600InstrInfo::R600InstrInfo | ( | const AMDGPUSubtarget & | st | ) | [explicit] |
Definition at line 31 of file R600InstrInfo.cpp.
Member Function Documentation
| void R600InstrInfo::addFlag | ( | MachineInstr * | MI, |
| unsigned | Operand, | ||
| unsigned | Flag | ||
| ) | const |
Add one of the MO_FLAG* flags to the specified Operand.
Definition at line 1408 of file R600InstrInfo.cpp.
References clearFlag(), getFlagOp(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), HAS_NATIVE_OPERANDS, MO_FLAG_LAST, MO_FLAG_MASK, MO_FLAG_NOT_LAST, NUM_MO_FLAGS, and llvm::MachineOperand::setImm().
Referenced by llvm::R600TargetLowering::EmitInstrWithCustomInserter(), and InsertBranch().
| bool R600InstrInfo::AnalyzeBranch | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock *& | TBB, | ||
| MachineBasicBlock *& | FBB, | ||
| SmallVectorImpl< MachineOperand > & | Cond, | ||
| bool | AllowModify | ||
| ) | const [override] |
Definition at line 698 of file R600InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineOperand::CreateReg(), llvm::MachineBasicBlock::end(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, isBranch(), isJump(), isPredicateSetter(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
| MachineInstrBuilder R600InstrInfo::buildDefaultInstruction | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| unsigned | Opcode, | ||
| unsigned | DstReg, | ||
| unsigned | Src0Reg, | ||
| unsigned | Src1Reg = 0 |
||
| ) | const |
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers initialized to their default values. You can use this function to avoid manually specifying each instruction modifier operand when building a new instruction.
- Returns:
- a MachineInstr with all the instruction modifiers initialized to their default values.
Definition at line 1186 of file R600InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), and llvm::MachineBasicBlock::findDebugLoc().
Referenced by buildMovImm(), buildMovInstr(), buildSlotOfVectorInstruction(), copyPhysReg(), and llvm::R600TargetLowering::EmitInstrWithCustomInserter().
| MachineInstrBuilder R600InstrInfo::buildIndirectRead | ( | MachineBasicBlock * | MBB, |
| MachineBasicBlock::iterator | I, | ||
| unsigned | ValueReg, | ||
| unsigned | Address, | ||
| unsigned | OffsetReg | ||
| ) | const [override, virtual] |
Build instruction(s) for an indirect register read.
- Returns:
- The instruction that performs the indirect register read
Implements llvm::AMDGPUInstrInfo.
Definition at line 1148 of file R600InstrInfo.cpp.
| MachineInstrBuilder R600InstrInfo::buildIndirectWrite | ( | MachineBasicBlock * | MBB, |
| MachineBasicBlock::iterator | I, | ||
| unsigned | ValueReg, | ||
| unsigned | Address, | ||
| unsigned | OffsetReg | ||
| ) | const [override, virtual] |
Build instruction(s) for an indirect register write.
- Returns:
- The instruction that performs the indirect register write
Implements llvm::AMDGPUInstrInfo.
Definition at line 1116 of file R600InstrInfo.cpp.
| MachineInstr * R600InstrInfo::buildMovImm | ( | MachineBasicBlock & | BB, |
| MachineBasicBlock::iterator | I, | ||
| unsigned | DstReg, | ||
| uint64_t | Imm | ||
| ) | const |
Definition at line 1313 of file R600InstrInfo.cpp.
References buildDefaultInstruction(), and setImmOperand().
Referenced by llvm::R600TargetLowering::EmitInstrWithCustomInserter().
| MachineInstr * R600InstrInfo::buildMovInstr | ( | MachineBasicBlock * | MBB, |
| MachineBasicBlock::iterator | I, | ||
| unsigned | DstReg, | ||
| unsigned | SrcReg | ||
| ) | const [override, virtual] |
Build a MOV instruction.
Implements llvm::AMDGPUInstrInfo.
Definition at line 1323 of file R600InstrInfo.cpp.
References buildDefaultInstruction().
| MachineInstr * R600InstrInfo::buildSlotOfVectorInstruction | ( | MachineBasicBlock & | MBB, |
| MachineInstr * | MI, | ||
| unsigned | Slot, | ||
| unsigned | DstReg | ||
| ) | const |
Definition at line 1265 of file R600InstrInfo.cpp.
References buildDefaultInstruction(), llvm::AMDGPUSubtarget::getGeneration(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::MachineOperand::getReg(), getSlotedOps(), llvm::MachineOperand::isImm(), llvm::AArch64CC::MI, llvm::AMDGPUSubtarget::R700, llvm::MachineOperand::setImm(), setImmOperand(), llvm::MachineOperand::setReg(), llvm::AMDGPUInstrInfo::ST, and llvm::LibFunc::write.
| unsigned R600InstrInfo::calculateIndirectAddress | ( | unsigned | RegIndex, |
| unsigned | Channel | ||
| ) | const [override, virtual] |
Calculate the "Indirect Address" for the given RegIndex and Channel.
We model indirect addressing using a virtual address space that can be accesed with loads and stores. The "Indirect Address" is the memory address in this virtual address space that maps to the given RegIndex and Channel.
Implements llvm::AMDGPUInstrInfo.
Definition at line 1105 of file R600InstrInfo.cpp.
| bool R600InstrInfo::canBeConsideredALU | ( | const MachineInstr * | MI | ) | const |
- Returns:
- true if this
Opcoderepresents an ALU instruction or an instruction that will be lowered in ExpandSpecialInstrs Pass.
Definition at line 163 of file R600InstrInfo.cpp.
References llvm::TargetOpcode::COPY, llvm::MachineInstr::getOpcode(), isALUInstr(), isCubeOp(), and isVector().
| void R600InstrInfo::clearFlag | ( | MachineInstr * | MI, |
| unsigned | Operand, | ||
| unsigned | Flag | ||
| ) | const |
Clear the specified flag on the instruction.
Definition at line 1429 of file R600InstrInfo.cpp.
References getFlagOp(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), HAS_NATIVE_OPERANDS, NUM_MO_FLAGS, and llvm::MachineOperand::setImm().
Referenced by addFlag(), and RemoveBranch().
| void R600InstrInfo::copyPhysReg | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | MI, | ||
| DebugLoc | DL, | ||
| unsigned | DestReg, | ||
| unsigned | SrcReg, | ||
| bool | KillSrc | ||
| ) | const [override] |
Definition at line 49 of file R600InstrInfo.cpp.
References buildDefaultInstruction(), contains(), llvm::RegState::Define, llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::AMDGPURegisterInfo::getSubRegFromChannel(), I, llvm::RegState::Implicit, and llvm::MachineOperand::setIsKill().
| DFAPacketizer * R600InstrInfo::CreateTargetScheduleState | ( | const TargetMachine * | TM, |
| const ScheduleDAG * | DAG | ||
| ) | const [override] |
Definition at line 657 of file R600InstrInfo.cpp.
References llvm::TargetSubtargetInfo::getInstrItineraryData(), llvm::TargetMachine::getSubtarget(), and llvm::TargetMachine::getSubtargetImpl().
| bool R600InstrInfo::definesAddressRegister | ( | MachineInstr * | MI | ) | const |
Definition at line 240 of file R600InstrInfo.cpp.
References llvm::MachineInstr::findRegisterDefOperandIdx().
| bool R600InstrInfo::DefinesPredicate | ( | MachineInstr * | MI, |
| std::vector< MachineOperand > & | Pred | ||
| ) | const [override] |
Reimplemented from llvm::AMDGPUInstrInfo.
Definition at line 1001 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and isPredicateSetter().
| bool R600InstrInfo::expandPostRAPseudo | ( | MachineBasicBlock::iterator | MI | ) | const [override] |
Reimplemented from llvm::AMDGPUInstrInfo.
Definition at line 1061 of file R600InstrInfo.cpp.
References llvm::R600RegisterInfo::getHWRegChan(), llvm::R600RegisterInfo::getHWRegIndex(), and llvm::AArch64CC::MI.
| bool R600InstrInfo::FindSwizzleForVectorSlot | ( | const std::vector< std::vector< std::pair< int, unsigned > > > & | IGSrcs, |
| std::vector< R600InstrInfo::BankSwizzle > & | SwzCandidate, | ||
| const std::vector< std::pair< int, unsigned > > & | TransSrcs, | ||
| R600InstrInfo::BankSwizzle | TransSwz | ||
| ) | const |
Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.
Definition at line 515 of file R600InstrInfo.cpp.
References isLegalUpTo(), and NextPossibleSolution().
Referenced by fitsReadPortLimitations().
| bool R600InstrInfo::fitsConstReadLimitations | ( | const std::vector< MachineInstr * > & | MIs | ) | const |
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+. This function check if MI set in input meet this limitations
Definition at line 626 of file R600InstrInfo.cpp.
References contains(), llvm::R600RegisterInfo::getHWRegChan(), llvm::MachineInstr::getOpcode(), getSrcs(), llvm::SmallSet< T, N, C >::insert(), isALUInstr(), llvm::SmallSet< T, N, C >::size(), and llvm::SmallVectorTemplateCommon< T >::size().
Referenced by FoldOperand().
| bool R600InstrInfo::fitsConstReadLimitations | ( | const std::vector< unsigned > & | Consts | ) | const |
Same but using const index set instead of MI set.
Definition at line 601 of file R600InstrInfo.cpp.
| bool R600InstrInfo::fitsReadPortLimitations | ( | const std::vector< MachineInstr * > & | MIs, |
| const DenseMap< unsigned, unsigned > & | PV, | ||
| std::vector< BankSwizzle > & | BS, | ||
| bool | isLastAluTrans | ||
| ) | const |
Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first (in lexical order) BankSwizzle affectation starting from the one already provided in the Instruction Group MIs that fits Read Port limitations in BS if available. Otherwise returns false and undefined content in BS. isLastAluTrans should be set if the last Alu of MIs will be executed on Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to apply to the last instruction. PV holds GPR to PV registers in the Instruction Group MIs.
Definition at line 552 of file R600InstrInfo.cpp.
References ALU_VEC_012_SCL_210, ALU_VEC_021_SCL_122, ALU_VEC_102_SCL_221, ALU_VEC_120_SCL_212, FindSwizzleForVectorSlot(), getOperandIdx(), and isConstCompatible().
| MachineOperand & R600InstrInfo::getFlagOp | ( | MachineInstr * | MI, |
| unsigned | SrcIdx = 0, |
||
| unsigned | Flag = 0 |
||
| ) | const |
- Parameters:
-
SrcIdx The register source to set the flag on (e.g src0, src1, src2) Flag The flag being set.
- Returns:
- the operand containing the flags for this instruction.
Definition at line 1353 of file R600InstrInfo.cpp.
References GET_FLAG_OPERAND_IDX, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOperandIdx(), HAS_NATIVE_OPERANDS, llvm::MachineOperand::isImm(), MO_FLAG_ABS, MO_FLAG_CLAMP, MO_FLAG_LAST, MO_FLAG_MASK, MO_FLAG_NEG, MO_FLAG_NOT_LAST, R600_InstFlag::OP3, and llvm::LibFunc::write.
Referenced by addFlag(), and clearFlag().
| const TargetRegisterClass * R600InstrInfo::getIndirectAddrRegClass | ( | ) | const [override, virtual] |
- Returns:
- The register class to be used for loading and storing values from an "Indirect Address" .
Implements llvm::AMDGPUInstrInfo.
Definition at line 1112 of file R600InstrInfo.cpp.
| unsigned int R600InstrInfo::getInstrLatency | ( | const InstrItineraryData * | ItinData, |
| const MachineInstr * | MI, | ||
| unsigned * | PredCost = nullptr |
||
| ) | const [override] |
Definition at line 1053 of file R600InstrInfo.cpp.
| int llvm::R600InstrInfo::getInstrLatency | ( | const InstrItineraryData * | ItinData, |
| SDNode * | Node | ||
| ) | const [inline, override] |
Definition at line 206 of file R600InstrInfo.h.
| unsigned R600InstrInfo::getMaxAlusPerClause | ( | ) | const |
Definition at line 1182 of file R600InstrInfo.cpp.
Referenced by llvm::R600SchedStrategy::initialize().
| int R600InstrInfo::getOperandIdx | ( | const MachineInstr & | MI, |
| unsigned | Op | ||
| ) | const |
Get the index of Op in the MachineInstr.
- Returns:
- -1 if the Instruction does not contain the specified
Op.
Definition at line 1329 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by buildSlotOfVectorInstruction(), copyPhysReg(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), fitsReadPortLimitations(), FoldOperand(), getFlagOp(), getSelIdx(), getSrcIdx(), getSrcs(), isLDSNoRetInstr(), isLDSRetInstr(), PredicateInstruction(), and setImmOperand().
| int R600InstrInfo::getOperandIdx | ( | unsigned | Opcode, |
| unsigned | Op | ||
| ) | const |
Get the index of Op for the given Opcode.
- Returns:
- -1 if the Instruction does not contain the specified
Op.
Definition at line 1333 of file R600InstrInfo.cpp.
References llvm::AMDGPU::getNamedOperandIdx().
| unsigned int R600InstrInfo::getPredicationCost | ( | const MachineInstr * | ) | const [override] |
Definition at line 1049 of file R600InstrInfo.cpp.
| const R600RegisterInfo & R600InstrInfo::getRegisterInfo | ( | ) | const [override, virtual] |
Implements llvm::AMDGPUInstrInfo.
Definition at line 36 of file R600InstrInfo.cpp.
Referenced by llvm::R600TargetLowering::LowerOperation().
| int R600InstrInfo::getSelIdx | ( | unsigned | Opcode, |
| unsigned | SrcIdx | ||
| ) | const |
- Returns:
- The operand Index for the Sel operand given an index to one of the instruction's src operands.
Definition at line 272 of file R600InstrInfo.cpp.
References getOperandIdx(), and SRC_SEL_ROWS.
Referenced by FoldOperand().
| int R600InstrInfo::getSrcIdx | ( | unsigned | Opcode, |
| unsigned | SrcNum | ||
| ) | const |
- Returns:
- The operand index for the given source number. Legal values for SrcNum are 0, 1, and 2.
Definition at line 260 of file R600InstrInfo.cpp.
References getOperandIdx().
| SmallVector< std::pair< MachineOperand *, int64_t >, 3 > R600InstrInfo::getSrcs | ( | MachineInstr * | MI | ) | const |
- Returns:
- a pair for each src of an ALU instructions. The first member of a pair is the register id. If register is ALU_CONST, second member is SEL. If register is ALU_LITERAL, second member is IMM. Otherwise, second member value is undefined.
Definition at line 297 of file R600InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::MachineOperand::getReg(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by fitsConstReadLimitations().
| bool R600InstrInfo::hasFlagOperand | ( | const MachineInstr & | MI | ) | const |
- Returns:
- true if this instruction has an operand for storing target flags.
Definition at line 1349 of file R600InstrInfo.cpp.
References GET_FLAG_OPERAND_IDX, and llvm::MachineInstr::getOpcode().
| bool R600InstrInfo::hasInstrModifiers | ( | unsigned | Opcode | ) | const |
Definition at line 139 of file R600InstrInfo.cpp.
References R600_InstFlag::OP1, R600_InstFlag::OP2, and R600_InstFlag::OP3.
| unsigned R600InstrInfo::InsertBranch | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock * | TBB, | ||
| MachineBasicBlock * | FBB, | ||
| const SmallVectorImpl< MachineOperand > & | Cond, | ||
| DebugLoc | DL | ||
| ) | const [override] |
Definition at line 787 of file R600InstrInfo.cpp.
References addFlag(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::SmallVectorBase::empty(), llvm::MachineBasicBlock::end(), findFirstPredicateSetterFrom(), FindLastAluClause(), llvm::MachineInstr::getOperand(), llvm::RegState::Kill, MO_FLAG_PUSH, and llvm::MachineOperand::setImm().
| bool R600InstrInfo::isALUInstr | ( | unsigned | Opcode | ) | const |
- Returns:
- true if this
Opcoderepresents an ALU instruction.
Definition at line 133 of file R600InstrInfo.cpp.
References R600_InstFlag::ALU_INST.
Referenced by canBeConsideredALU(), fitsConstReadLimitations(), and readsLDSSrcReg().
| bool R600InstrInfo::isCubeOp | ( | unsigned | opcode | ) | const |
Definition at line 122 of file R600InstrInfo.cpp.
Referenced by canBeConsideredALU().
| bool R600InstrInfo::isExport | ( | unsigned | Opcode | ) | const |
Definition at line 199 of file R600InstrInfo.cpp.
References R600_InstFlag::IS_EXPORT.
| bool llvm::R600InstrInfo::isFlagSet | ( | const MachineInstr & | MI, |
| unsigned | Operand, | ||
| unsigned | Flag | ||
| ) | const |
Determine if the specified Flag is set on this Operand.
| bool R600InstrInfo::isLDSInstr | ( | unsigned | Opcode | ) | const |
Definition at line 147 of file R600InstrInfo.cpp.
References R600_InstFlag::LDS_1A, R600_InstFlag::LDS_1A1D, and R600_InstFlag::LDS_1A2D.
Referenced by isLDSNoRetInstr(), and isLDSRetInstr().
| bool R600InstrInfo::isLDSNoRetInstr | ( | unsigned | Opcode | ) | const |
Definition at line 155 of file R600InstrInfo.cpp.
References getOperandIdx(), and isLDSInstr().
| bool R600InstrInfo::isLDSRetInstr | ( | unsigned | Opcode | ) | const |
Definition at line 159 of file R600InstrInfo.cpp.
References getOperandIdx(), and isLDSInstr().
Referenced by llvm::R600TargetLowering::EmitInstrWithCustomInserter().
| bool R600InstrInfo::isLegalToSplitMBBAt | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | MBBI | ||
| ) | const [override] |
- Returns:
- true if
MBBIcan be moved into a new basic.
Definition at line 84 of file R600InstrInfo.cpp.
References I, llvm::R600RegisterInfo::isPhysRegLiveAcrossClauses(), and llvm::TargetRegisterInfo::isVirtualRegister().
| unsigned R600InstrInfo::isLegalUpTo | ( | const std::vector< std::vector< std::pair< int, unsigned > > > & | IGSrcs, |
| const std::vector< R600InstrInfo::BankSwizzle > & | Swz, | ||
| const std::vector< std::pair< int, unsigned > > & | TransSrcs, | ||
| R600InstrInfo::BankSwizzle | TransSwz | ||
| ) | const |
returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction Group while meeting read port limitations given a Swz swizzle sequence.
Definition at line 446 of file R600InstrInfo.cpp.
References ALU_VEC_012_SCL_210, ALU_VEC_021_SCL_122, GET_REG_INDEX, getTransSwizzle(), llvm::LibFunc::memset, and Swizzle().
Referenced by FindSwizzleForVectorSlot().
| bool R600InstrInfo::isMov | ( | unsigned | Opcode | ) | const [override, virtual] |
Implements llvm::AMDGPUInstrInfo.
Definition at line 95 of file R600InstrInfo.cpp.
| bool R600InstrInfo::isPlaceHolderOpcode | ( | unsigned | opcode | ) | const |
Definition at line 110 of file R600InstrInfo.cpp.
References llvm::NVPTXISD::RETURN.
| bool R600InstrInfo::isPredicable | ( | MachineInstr * | MI | ) | const [override] |
Reimplemented from llvm::AMDGPUInstrInfo.
Definition at line 907 of file R600InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), and isVector().
| bool R600InstrInfo::isPredicated | ( | const MachineInstr * | MI | ) | const [override] |
Reimplemented from llvm::AMDGPUInstrInfo.
Definition at line 891 of file R600InstrInfo.cpp.
References llvm::MachineInstr::findFirstPredOperandIdx(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
| bool R600InstrInfo::isProfitableToDupForIfCvt | ( | MachineBasicBlock & | MBB, |
| unsigned | NumCyles, | ||
| const BranchProbability & | Probability | ||
| ) | const [override] |
Definition at line 952 of file R600InstrInfo.cpp.
| bool R600InstrInfo::isProfitableToIfCvt | ( | MachineBasicBlock & | MBB, |
| unsigned | NumCyles, | ||
| unsigned | ExtraPredCycles, | ||
| const BranchProbability & | Probability | ||
| ) | const [override] |
Definition at line 933 of file R600InstrInfo.cpp.
| bool R600InstrInfo::isProfitableToIfCvt | ( | MachineBasicBlock & | TMBB, |
| unsigned | NumTCycles, | ||
| unsigned | ExtraTCycles, | ||
| MachineBasicBlock & | FMBB, | ||
| unsigned | NumFCycles, | ||
| unsigned | ExtraFCycles, | ||
| const BranchProbability & | Probability | ||
| ) | const [override] |
Definition at line 941 of file R600InstrInfo.cpp.
| bool R600InstrInfo::isProfitableToUnpredicate | ( | MachineBasicBlock & | TMBB, |
| MachineBasicBlock & | FMBB | ||
| ) | const [override] |
Definition at line 960 of file R600InstrInfo.cpp.
| bool R600InstrInfo::isReductionOp | ( | unsigned | opcode | ) | const |
Definition at line 118 of file R600InstrInfo.cpp.
| bool R600InstrInfo::isTransOnly | ( | unsigned | Opcode | ) | const |
Definition at line 181 of file R600InstrInfo.cpp.
References llvm::AMDGPUSubtarget::hasCaymanISA(), and llvm::AMDGPUInstrInfo::ST.
Referenced by isTransOnly().
| bool R600InstrInfo::isTransOnly | ( | const MachineInstr * | MI | ) | const |
Definition at line 187 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and isTransOnly().
| bool R600InstrInfo::isTrig | ( | const MachineInstr & | MI | ) | const |
Definition at line 40 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and R600_InstFlag::TRIG.
| bool R600InstrInfo::isVector | ( | const MachineInstr & | MI | ) | const |
Vector instructions are instructions that must fill all instruction slots within an instruction group.
Definition at line 44 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and R600_InstFlag::VECTOR.
Referenced by canBeConsideredALU(), and isPredicable().
| bool R600InstrInfo::isVectorOnly | ( | unsigned | Opcode | ) | const |
Definition at line 191 of file R600InstrInfo.cpp.
Referenced by isVectorOnly().
| bool R600InstrInfo::isVectorOnly | ( | const MachineInstr * | MI | ) | const |
Definition at line 195 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and isVectorOnly().
| bool R600InstrInfo::mustBeLastInClause | ( | unsigned | Opcode | ) | const |
Definition at line 226 of file R600InstrInfo.cpp.
| bool R600InstrInfo::PredicateInstruction | ( | MachineInstr * | MI, |
| const SmallVectorImpl< MachineOperand > & | Pred | ||
| ) | const [override] |
Definition at line 1015 of file R600InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::findFirstPredOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), getReg(), llvm::RegState::Implicit, llvm::AArch64CC::MI, llvm::MachineOperand::setImm(), and llvm::MachineOperand::setReg().
| bool R600InstrInfo::readsLDSSrcReg | ( | const MachineInstr * | MI | ) | const |
Definition at line 244 of file R600InstrInfo.cpp.
References contains(), llvm::MachineInstr::getOpcode(), I, isALUInstr(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineInstr::operands_begin(), and llvm::MachineInstr::operands_end().
| unsigned R600InstrInfo::RemoveBranch | ( | MachineBasicBlock & | MBB | ) | const [override] |
Definition at line 833 of file R600InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), clearFlag(), llvm::MachineBasicBlock::end(), findFirstPredicateSetterFrom(), FindLastAluClause(), I, and MO_FLAG_PUSH.
| void R600InstrInfo::reserveIndirectRegisters | ( | BitVector & | Reserved, |
| const MachineFunction & | MF | ||
| ) | const |
Reserve the registers that may be accesed using indirect addressing.
Definition at line 1084 of file R600InstrInfo.cpp.
References llvm::TargetSubtargetInfo::getFrameLowering(), llvm::AMDGPUInstrInfo::getIndirectIndexBegin(), llvm::AMDGPUInstrInfo::getIndirectIndexEnd(), llvm::AMDGPUFrameLowering::getStackWidth(), llvm::MachineFunction::getSubtarget(), and llvm::BitVector::set().
Referenced by llvm::R600RegisterInfo::getReservedRegs().
| bool R600InstrInfo::ReverseBranchCondition | ( | SmallVectorImpl< MachineOperand > & | Cond | ) | const [override] |
Reimplemented from llvm::AMDGPUInstrInfo.
Definition at line 967 of file R600InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), OPCODE_IS_NOT_ZERO, OPCODE_IS_NOT_ZERO_INT, OPCODE_IS_ZERO, OPCODE_IS_ZERO_INT, llvm::MachineOperand::setImm(), and llvm::MachineOperand::setReg().
| void R600InstrInfo::setImmOperand | ( | MachineInstr * | MI, |
| unsigned | Op, | ||
| int64_t | Imm | ||
| ) | const |
Helper function for setting instruction flag values.
Definition at line 1337 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::setImm().
Referenced by buildMovImm(), buildSlotOfVectorInstruction(), and llvm::R600TargetLowering::EmitInstrWithCustomInserter().
| bool R600InstrInfo::SubsumesPredicate | ( | const SmallVectorImpl< MachineOperand > & | Pred1, |
| const SmallVectorImpl< MachineOperand > & | Pred2 | ||
| ) | const [override] |
Reimplemented from llvm::AMDGPUInstrInfo.
Definition at line 1008 of file R600InstrInfo.cpp.
| bool R600InstrInfo::usesAddressRegister | ( | MachineInstr * | MI | ) | const |
Definition at line 236 of file R600InstrInfo.cpp.
References llvm::MachineInstr::findRegisterUseOperandIdx().
| bool R600InstrInfo::usesTextureCache | ( | unsigned | Opcode | ) | const |
Definition at line 214 of file R600InstrInfo.cpp.
References llvm::AMDGPUSubtarget::hasVertexCache(), IS_TEX, IS_VTX, and llvm::AMDGPUInstrInfo::ST.
Referenced by usesTextureCache().
| bool R600InstrInfo::usesTextureCache | ( | const MachineInstr * | MI | ) | const |
Definition at line 218 of file R600InstrInfo.cpp.
References ShaderType::COMPUTE, llvm::MachineFunction::getInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::AMDGPUMachineFunction::getShaderType(), usesTextureCache(), and usesVertexCache().
| bool R600InstrInfo::usesVertexCache | ( | unsigned | Opcode | ) | const |
Definition at line 203 of file R600InstrInfo.cpp.
References llvm::AMDGPUSubtarget::hasVertexCache(), IS_VTX, and llvm::AMDGPUInstrInfo::ST.
Referenced by usesTextureCache(), and usesVertexCache().
| bool R600InstrInfo::usesVertexCache | ( | const MachineInstr * | MI | ) | const |
Definition at line 207 of file R600InstrInfo.cpp.
References ShaderType::COMPUTE, llvm::MachineFunction::getInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::AMDGPUMachineFunction::getShaderType(), and usesVertexCache().
The documentation for this class was generated from the following files:
1.7.6.1