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bnx2x_main.c
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1 /* bnx2x_main.c: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2012 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Maintained by: Eilon Greenstein <[email protected]>
10  * Written by: Eliezer Tamir
11  * Based on code from Michael Chan's bnx2 driver
12  * UDP CSUM errata workaround by Arik Gendelman
13  * Slowpath and fastpath rework by Vladislav Zolotarov
14  * Statistics and Link management by Yitchak Gertner
15  *
16  */
17 
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <net/ip.h>
44 #include <net/ipv6.h>
45 #include <net/tcp.h>
46 #include <net/checksum.h>
47 #include <net/ip6_checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/crc32c.h>
51 #include <linux/prefetch.h>
52 #include <linux/zlib.h>
53 #include <linux/io.h>
54 #include <linux/semaphore.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
57 
58 #include "bnx2x.h"
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_dcb.h"
63 #include "bnx2x_sp.h"
64 
65 #include <linux/firmware.h>
66 #include "bnx2x_fw_file_hdr.h"
67 /* FW files */
68 #define FW_FILE_VERSION \
69  __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
70  __stringify(BCM_5710_FW_MINOR_VERSION) "." \
71  __stringify(BCM_5710_FW_REVISION_VERSION) "." \
72  __stringify(BCM_5710_FW_ENGINEERING_VERSION)
73 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
74 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
76 
77 #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
78 
79 /* Time in jiffies before concluding the transmitter is hung */
80 #define TX_TIMEOUT (5*HZ)
81 
82 static char version[] __devinitdata =
83  "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
85 
86 MODULE_AUTHOR("Eliezer Tamir");
87 MODULE_DESCRIPTION("Broadcom NetXtreme II "
88  "BCM57710/57711/57711E/"
89  "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
90  "57840/57840_MF Driver");
91 MODULE_LICENSE("GPL");
96 
97 
99 module_param(num_queues, int, 0);
101  " Set number of queues (default is as a number of CPUs)");
102 
103 static int disable_tpa;
104 module_param(disable_tpa, int, 0);
105 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
106 
107 #define INT_MODE_INTx 1
108 #define INT_MODE_MSI 2
110 module_param(int_mode, int, 0);
111 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
112  "(1 INT#x; 2 MSI)");
113 
114 static int dropless_fc;
115 module_param(dropless_fc, int, 0);
116 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
117 
118 static int mrrs = -1;
119 module_param(mrrs, int, 0);
120 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
121 
122 static int debug;
123 module_param(debug, int, 0);
124 MODULE_PARM_DESC(debug, " Default debug msglevel");
125 
126 
127 
129 
131  BCM57710 = 0,
147 };
148 
149 /* indexed by board_type, above */
150 static struct {
151  char *name;
153  { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
154  { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
155  { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
156  { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
157  { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
158  { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
159  { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
160  { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
161  { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
162  { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
163  { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
164  { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
165  { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"},
166  { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"},
167  { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet"},
168  { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function"},
169 };
170 
171 #ifndef PCI_DEVICE_ID_NX2_57710
172 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
173 #endif
174 #ifndef PCI_DEVICE_ID_NX2_57711
175 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
176 #endif
177 #ifndef PCI_DEVICE_ID_NX2_57711E
178 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
179 #endif
180 #ifndef PCI_DEVICE_ID_NX2_57712
181 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
182 #endif
183 #ifndef PCI_DEVICE_ID_NX2_57712_MF
184 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
185 #endif
186 #ifndef PCI_DEVICE_ID_NX2_57800
187 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
188 #endif
189 #ifndef PCI_DEVICE_ID_NX2_57800_MF
190 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
191 #endif
192 #ifndef PCI_DEVICE_ID_NX2_57810
193 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
194 #endif
195 #ifndef PCI_DEVICE_ID_NX2_57810_MF
196 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
197 #endif
198 #ifndef PCI_DEVICE_ID_NX2_57840_O
199 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
200 #endif
201 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
202 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
203 #endif
204 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
205 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
206 #endif
207 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
208 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
209 #endif
210 #ifndef PCI_DEVICE_ID_NX2_57840_MF
211 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
212 #endif
213 #ifndef PCI_DEVICE_ID_NX2_57811
214 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
215 #endif
216 #ifndef PCI_DEVICE_ID_NX2_57811_MF
217 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
218 #endif
219 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
236  { 0 }
237 };
238 
239 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
240 
241 /* Global resources for unloading a previously loaded device */
242 #define BNX2X_PREV_WAIT_NEEDED 1
243 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
244 static LIST_HEAD(bnx2x_prev_list);
245 /****************************************************************************
246 * General service functions
247 ****************************************************************************/
248 
249 static void __storm_memset_dma_mapping(struct bnx2x *bp,
251 {
252  REG_WR(bp, addr, U64_LO(mapping));
253  REG_WR(bp, addr + 4, U64_HI(mapping));
254 }
255 
256 static void storm_memset_spq_addr(struct bnx2x *bp,
257  dma_addr_t mapping, u16 abs_fid)
258 {
259  u32 addr = XSEM_REG_FAST_MEMORY +
261 
262  __storm_memset_dma_mapping(bp, addr, mapping);
263 }
264 
265 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
266  u16 pf_id)
267 {
269  pf_id);
271  pf_id);
273  pf_id);
275  pf_id);
276 }
277 
278 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
279  u8 enable)
280 {
282  enable);
284  enable);
286  enable);
288  enable);
289 }
290 
291 static void storm_memset_eq_data(struct bnx2x *bp,
292  struct event_ring_data *eq_data,
293  u16 pfid)
294 {
295  size_t size = sizeof(struct event_ring_data);
296 
298 
299  __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
300 }
301 
302 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
303  u16 pfid)
304 {
306  REG_WR16(bp, addr, eq_prod);
307 }
308 
309 /* used only at init
310  * locking is done by mcp
311  */
312 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
313 {
314  pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
315  pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
316  pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
318 }
319 
320 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
321 {
322  u32 val;
323 
324  pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
325  pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
326  pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
328 
329  return val;
330 }
331 
332 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
333 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
334 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
335 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
336 #define DMAE_DP_DST_NONE "dst_addr [none]"
337 
338 
339 /* copy command into DMAE command memory and set DMAE command go */
340 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
341 {
342  u32 cmd_offset;
343  int i;
344 
345  cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
346  for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
347  REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
348  }
349  REG_WR(bp, dmae_reg_go_c[idx], 1);
350 }
351 
353 {
354  return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
356 }
357 
359 {
360  return opcode & ~DMAE_CMD_SRC_RESET;
361 }
362 
363 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
364  bool with_comp, u8 comp_type)
365 {
366  u32 opcode = 0;
367 
368  opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
369  (dst_type << DMAE_COMMAND_DST_SHIFT));
370 
372 
373  opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
374  opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
377 
378 #ifdef __BIG_ENDIAN
380 #else
381  opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
382 #endif
383  if (with_comp)
384  opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
385  return opcode;
386 }
387 
388 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
389  struct dmae_command *dmae,
390  u8 src_type, u8 dst_type)
391 {
392  memset(dmae, 0, sizeof(struct dmae_command));
393 
394  /* set the opcode */
395  dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
396  true, DMAE_COMP_PCI);
397 
398  /* fill in the completion parameters */
399  dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
400  dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
401  dmae->comp_val = DMAE_COMP_VAL;
402 }
403 
404 /* issue a dmae command over the init-channel and wailt for completion */
405 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
406  struct dmae_command *dmae)
407 {
408  u32 *wb_comp = bnx2x_sp(bp, wb_comp);
409  int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
410  int rc = 0;
411 
412  /*
413  * Lock the dmae channel. Disable BHs to prevent a dead-lock
414  * as long as this code is called both from syscall context and
415  * from ndo_set_rx_mode() flow that may be called from BH.
416  */
417  spin_lock_bh(&bp->dmae_lock);
418 
419  /* reset completion */
420  *wb_comp = 0;
421 
422  /* post the command on the channel used for initializations */
423  bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
424 
425  /* wait for completion */
426  udelay(5);
427  while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
428 
429  if (!cnt ||
432  BNX2X_ERR("DMAE timeout!\n");
433  rc = DMAE_TIMEOUT;
434  goto unlock;
435  }
436  cnt--;
437  udelay(50);
438  }
439  if (*wb_comp & DMAE_PCI_ERR_FLAG) {
440  BNX2X_ERR("DMAE PCI error!\n");
441  rc = DMAE_PCI_ERROR;
442  }
443 
444 unlock:
445  spin_unlock_bh(&bp->dmae_lock);
446  return rc;
447 }
448 
450  u32 len32)
451 {
452  struct dmae_command dmae;
453 
454  if (!bp->dmae_ready) {
455  u32 *data = bnx2x_sp(bp, wb_data[0]);
456 
457  if (CHIP_IS_E1(bp))
458  bnx2x_init_ind_wr(bp, dst_addr, data, len32);
459  else
460  bnx2x_init_str_wr(bp, dst_addr, data, len32);
461  return;
462  }
463 
464  /* set opcode and fixed command fields */
465  bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
466 
467  /* fill in addresses and len */
468  dmae.src_addr_lo = U64_LO(dma_addr);
469  dmae.src_addr_hi = U64_HI(dma_addr);
470  dmae.dst_addr_lo = dst_addr >> 2;
471  dmae.dst_addr_hi = 0;
472  dmae.len = len32;
473 
474  /* issue the command and wait for completion */
475  bnx2x_issue_dmae_with_comp(bp, &dmae);
476 }
477 
478 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
479 {
480  struct dmae_command dmae;
481 
482  if (!bp->dmae_ready) {
483  u32 *data = bnx2x_sp(bp, wb_data[0]);
484  int i;
485 
486  if (CHIP_IS_E1(bp))
487  for (i = 0; i < len32; i++)
488  data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
489  else
490  for (i = 0; i < len32; i++)
491  data[i] = REG_RD(bp, src_addr + i*4);
492 
493  return;
494  }
495 
496  /* set opcode and fixed command fields */
497  bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
498 
499  /* fill in addresses and len */
500  dmae.src_addr_lo = src_addr >> 2;
501  dmae.src_addr_hi = 0;
502  dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
503  dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
504  dmae.len = len32;
505 
506  /* issue the command and wait for completion */
507  bnx2x_issue_dmae_with_comp(bp, &dmae);
508 }
509 
510 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
511  u32 addr, u32 len)
512 {
513  int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
514  int offset = 0;
515 
516  while (len > dmae_wr_max) {
517  bnx2x_write_dmae(bp, phys_addr + offset,
518  addr + offset, dmae_wr_max);
519  offset += dmae_wr_max * 4;
520  len -= dmae_wr_max;
521  }
522 
523  bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
524 }
525 
526 static int bnx2x_mc_assert(struct bnx2x *bp)
527 {
528  char last_idx;
529  int i, rc = 0;
530  u32 row0, row1, row2, row3;
531 
532  /* XSTORM */
533  last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
535  if (last_idx)
536  BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
537 
538  /* print the asserts */
539  for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
540 
541  row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
543  row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
545  row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
547  row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
548  XSTORM_ASSERT_LIST_OFFSET(i) + 12);
549 
550  if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
551  BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
552  i, row3, row2, row1, row0);
553  rc++;
554  } else {
555  break;
556  }
557  }
558 
559  /* TSTORM */
560  last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
562  if (last_idx)
563  BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
564 
565  /* print the asserts */
566  for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
567 
568  row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
570  row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
572  row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
574  row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
575  TSTORM_ASSERT_LIST_OFFSET(i) + 12);
576 
577  if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
578  BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
579  i, row3, row2, row1, row0);
580  rc++;
581  } else {
582  break;
583  }
584  }
585 
586  /* CSTORM */
587  last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
589  if (last_idx)
590  BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
591 
592  /* print the asserts */
593  for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
594 
595  row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
597  row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
599  row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
601  row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
602  CSTORM_ASSERT_LIST_OFFSET(i) + 12);
603 
604  if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
605  BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
606  i, row3, row2, row1, row0);
607  rc++;
608  } else {
609  break;
610  }
611  }
612 
613  /* USTORM */
614  last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
616  if (last_idx)
617  BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
618 
619  /* print the asserts */
620  for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
621 
622  row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
624  row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
626  row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
628  row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
629  USTORM_ASSERT_LIST_OFFSET(i) + 12);
630 
631  if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
632  BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
633  i, row3, row2, row1, row0);
634  rc++;
635  } else {
636  break;
637  }
638  }
639 
640  return rc;
641 }
642 
643 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
644 {
645  u32 addr, val;
646  u32 mark, offset;
647  __be32 data[9];
648  int word;
649  u32 trace_shmem_base;
650  if (BP_NOMCP(bp)) {
651  BNX2X_ERR("NO MCP - can not dump\n");
652  return;
653  }
654  netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
655  (bp->common.bc_ver & 0xff0000) >> 16,
656  (bp->common.bc_ver & 0xff00) >> 8,
657  (bp->common.bc_ver & 0xff));
658 
661  BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
662 
663  if (BP_PATH(bp) == 0)
664  trace_shmem_base = bp->common.shmem_base;
665  else
666  trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
667  addr = trace_shmem_base - 0x800;
668 
669  /* validate TRCB signature */
670  mark = REG_RD(bp, addr);
671  if (mark != MFW_TRACE_SIGNATURE) {
672  BNX2X_ERR("Trace buffer signature is missing.");
673  return ;
674  }
675 
676  /* read cyclic buffer pointer */
677  addr += 4;
678  mark = REG_RD(bp, addr);
680  + ((mark + 0x3) & ~0x3) - 0x08000000;
681  printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
682 
683  printk("%s", lvl);
684  for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
685  for (word = 0; word < 8; word++)
686  data[word] = htonl(REG_RD(bp, offset + 4*word));
687  data[8] = 0x0;
688  pr_cont("%s", (char *)data);
689  }
690  for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
691  for (word = 0; word < 8; word++)
692  data[word] = htonl(REG_RD(bp, offset + 4*word));
693  data[8] = 0x0;
694  pr_cont("%s", (char *)data);
695  }
696  printk("%s" "end of fw dump\n", lvl);
697 }
698 
699 static void bnx2x_fw_dump(struct bnx2x *bp)
700 {
702 }
703 
704 void bnx2x_panic_dump(struct bnx2x *bp)
705 {
706  int i;
707  u16 j;
708  struct hc_sp_status_block_data sp_sb_data;
709  int func = BP_FUNC(bp);
710 #ifdef BNX2X_STOP_ON_ERROR
711  u16 start = 0, end = 0;
712  u8 cos;
713 #endif
714 
716  bp->eth_stats.unrecoverable_error++;
717  DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
718 
719  BNX2X_ERR("begin crash dump -----------------\n");
720 
721  /* Indices */
722  /* Common */
723  BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
724  bp->def_idx, bp->def_att_idx, bp->attn_state,
725  bp->spq_prod_idx, bp->stats_counter);
726  BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
727  bp->def_status_blk->atten_status_block.attn_bits,
728  bp->def_status_blk->atten_status_block.attn_bits_ack,
729  bp->def_status_blk->atten_status_block.status_block_id,
730  bp->def_status_blk->atten_status_block.attn_bits_index);
731  BNX2X_ERR(" def (");
732  for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
733  pr_cont("0x%x%s",
734  bp->def_status_blk->sp_sb.index_values[i],
735  (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
736 
737  for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
738  *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
740  i*sizeof(u32));
741 
742  pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
743  sp_sb_data.igu_sb_id,
744  sp_sb_data.igu_seg_id,
745  sp_sb_data.p_func.pf_id,
746  sp_sb_data.p_func.vnic_id,
747  sp_sb_data.p_func.vf_id,
748  sp_sb_data.p_func.vf_valid,
749  sp_sb_data.state);
750 
751 
752  for_each_eth_queue(bp, i) {
753  struct bnx2x_fastpath *fp = &bp->fp[i];
754  int loop;
755  struct hc_status_block_data_e2 sb_data_e2;
756  struct hc_status_block_data_e1x sb_data_e1x;
757  struct hc_status_block_sm *hc_sm_p =
758  CHIP_IS_E1x(bp) ?
759  sb_data_e1x.common.state_machine :
760  sb_data_e2.common.state_machine;
761  struct hc_index_data *hc_index_p =
762  CHIP_IS_E1x(bp) ?
763  sb_data_e1x.index_data :
764  sb_data_e2.index_data;
765  u8 data_size, cos;
766  u32 *sb_data_p;
767  struct bnx2x_fp_txdata txdata;
768 
769  /* Rx */
770  BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
771  i, fp->rx_bd_prod, fp->rx_bd_cons,
772  fp->rx_comp_prod,
773  fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
774  BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
775  fp->rx_sge_prod, fp->last_max_sge,
776  le16_to_cpu(fp->fp_hc_idx));
777 
778  /* Tx */
779  for_each_cos_in_tx_queue(fp, cos)
780  {
781  txdata = *fp->txdata_ptr[cos];
782  BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
783  i, txdata.tx_pkt_prod,
784  txdata.tx_pkt_cons, txdata.tx_bd_prod,
785  txdata.tx_bd_cons,
786  le16_to_cpu(*txdata.tx_cons_sb));
787  }
788 
789  loop = CHIP_IS_E1x(bp) ?
791 
792  /* host sb data */
793 
794 #ifdef BCM_CNIC
795  if (IS_FCOE_FP(fp))
796  continue;
797 #endif
798  BNX2X_ERR(" run indexes (");
799  for (j = 0; j < HC_SB_MAX_SM; j++)
800  pr_cont("0x%x%s",
801  fp->sb_running_index[j],
802  (j == HC_SB_MAX_SM - 1) ? ")" : " ");
803 
804  BNX2X_ERR(" indexes (");
805  for (j = 0; j < loop; j++)
806  pr_cont("0x%x%s",
807  fp->sb_index_values[j],
808  (j == loop - 1) ? ")" : " ");
809  /* fw sb data */
810  data_size = CHIP_IS_E1x(bp) ?
811  sizeof(struct hc_status_block_data_e1x) :
812  sizeof(struct hc_status_block_data_e2);
813  data_size /= sizeof(u32);
814  sb_data_p = CHIP_IS_E1x(bp) ?
815  (u32 *)&sb_data_e1x :
816  (u32 *)&sb_data_e2;
817  /* copy sb data in here */
818  for (j = 0; j < data_size; j++)
819  *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
820  CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
821  j * sizeof(u32));
822 
823  if (!CHIP_IS_E1x(bp)) {
824  pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
825  sb_data_e2.common.p_func.pf_id,
826  sb_data_e2.common.p_func.vf_id,
827  sb_data_e2.common.p_func.vf_valid,
828  sb_data_e2.common.p_func.vnic_id,
829  sb_data_e2.common.same_igu_sb_1b,
830  sb_data_e2.common.state);
831  } else {
832  pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
833  sb_data_e1x.common.p_func.pf_id,
834  sb_data_e1x.common.p_func.vf_id,
835  sb_data_e1x.common.p_func.vf_valid,
836  sb_data_e1x.common.p_func.vnic_id,
837  sb_data_e1x.common.same_igu_sb_1b,
838  sb_data_e1x.common.state);
839  }
840 
841  /* SB_SMs data */
842  for (j = 0; j < HC_SB_MAX_SM; j++) {
843  pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
844  j, hc_sm_p[j].__flags,
845  hc_sm_p[j].igu_sb_id,
846  hc_sm_p[j].igu_seg_id,
847  hc_sm_p[j].time_to_expire,
848  hc_sm_p[j].timer_value);
849  }
850 
851  /* Indecies data */
852  for (j = 0; j < loop; j++) {
853  pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
854  hc_index_p[j].flags,
855  hc_index_p[j].timeout);
856  }
857  }
858 
859 #ifdef BNX2X_STOP_ON_ERROR
860  /* Rings */
861  /* Rx */
862  for_each_rx_queue(bp, i) {
863  struct bnx2x_fastpath *fp = &bp->fp[i];
864 
865  start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
866  end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
867  for (j = start; j != end; j = RX_BD(j + 1)) {
868  u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
869  struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
870 
871  BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
872  i, j, rx_bd[1], rx_bd[0], sw_bd->data);
873  }
874 
875  start = RX_SGE(fp->rx_sge_prod);
876  end = RX_SGE(fp->last_max_sge);
877  for (j = start; j != end; j = RX_SGE(j + 1)) {
878  u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
879  struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
880 
881  BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
882  i, j, rx_sge[1], rx_sge[0], sw_page->page);
883  }
884 
885  start = RCQ_BD(fp->rx_comp_cons - 10);
886  end = RCQ_BD(fp->rx_comp_cons + 503);
887  for (j = start; j != end; j = RCQ_BD(j + 1)) {
888  u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
889 
890  BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
891  i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
892  }
893  }
894 
895  /* Tx */
896  for_each_tx_queue(bp, i) {
897  struct bnx2x_fastpath *fp = &bp->fp[i];
898  for_each_cos_in_tx_queue(fp, cos) {
899  struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
900 
901  start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
902  end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
903  for (j = start; j != end; j = TX_BD(j + 1)) {
904  struct sw_tx_bd *sw_bd =
905  &txdata->tx_buf_ring[j];
906 
907  BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
908  i, cos, j, sw_bd->skb,
909  sw_bd->first_bd);
910  }
911 
912  start = TX_BD(txdata->tx_bd_cons - 10);
913  end = TX_BD(txdata->tx_bd_cons + 254);
914  for (j = start; j != end; j = TX_BD(j + 1)) {
915  u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
916 
917  BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
918  i, cos, j, tx_bd[0], tx_bd[1],
919  tx_bd[2], tx_bd[3]);
920  }
921  }
922  }
923 #endif
924  bnx2x_fw_dump(bp);
925  bnx2x_mc_assert(bp);
926  BNX2X_ERR("end crash dump -----------------\n");
927 }
928 
929 /*
930  * FLR Support for E2
931  *
932  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
933  * initialization.
934  */
935 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
936 #define FLR_WAIT_INTERVAL 50 /* usec */
937 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
938 
940  int pN;
944 };
945 
947  int pN;
950 };
951 
952 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
953  struct pbf_pN_buf_regs *regs,
954  u32 poll_count)
955 {
956  u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
957  u32 cur_cnt = poll_count;
958 
959  crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
960  crd = crd_start = REG_RD(bp, regs->crd);
961  init_crd = REG_RD(bp, regs->init_crd);
962 
963  DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
964  DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
965  DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
966 
967  while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
968  (init_crd - crd_start))) {
969  if (cur_cnt--) {
971  crd = REG_RD(bp, regs->crd);
972  crd_freed = REG_RD(bp, regs->crd_freed);
973  } else {
974  DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
975  regs->pN);
976  DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
977  regs->pN, crd);
978  DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
979  regs->pN, crd_freed);
980  break;
981  }
982  }
983  DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
984  poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
985 }
986 
987 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
988  struct pbf_pN_cmd_regs *regs,
989  u32 poll_count)
990 {
991  u32 occup, to_free, freed, freed_start;
992  u32 cur_cnt = poll_count;
993 
994  occup = to_free = REG_RD(bp, regs->lines_occup);
995  freed = freed_start = REG_RD(bp, regs->lines_freed);
996 
997  DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
998  DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
999 
1000  while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1001  if (cur_cnt--) {
1003  occup = REG_RD(bp, regs->lines_occup);
1004  freed = REG_RD(bp, regs->lines_freed);
1005  } else {
1006  DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1007  regs->pN);
1008  DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1009  regs->pN, occup);
1010  DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1011  regs->pN, freed);
1012  break;
1013  }
1014  }
1015  DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1016  poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1017 }
1018 
1019 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1020  u32 expected, u32 poll_count)
1021 {
1022  u32 cur_cnt = poll_count;
1023  u32 val;
1024 
1025  while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1027 
1028  return val;
1029 }
1030 
1031 static int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1032  char *msg, u32 poll_cnt)
1033 {
1034  u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1035  if (val != 0) {
1036  BNX2X_ERR("%s usage count=%d\n", msg, val);
1037  return 1;
1038  }
1039  return 0;
1040 }
1041 
1042 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1043 {
1044  /* adjust polling timeout */
1045  if (CHIP_REV_IS_EMUL(bp))
1046  return FLR_POLL_CNT * 2000;
1047 
1048  if (CHIP_REV_IS_FPGA(bp))
1049  return FLR_POLL_CNT * 120;
1050 
1051  return FLR_POLL_CNT;
1052 }
1053 
1054 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1055 {
1056  struct pbf_pN_cmd_regs cmd_regs[] = {
1057  {0, (CHIP_IS_E3B0(bp)) ?
1060  (CHIP_IS_E3B0(bp)) ?
1063  {1, (CHIP_IS_E3B0(bp)) ?
1066  (CHIP_IS_E3B0(bp)) ?
1069  {4, (CHIP_IS_E3B0(bp)) ?
1072  (CHIP_IS_E3B0(bp)) ?
1075  };
1076 
1077  struct pbf_pN_buf_regs buf_regs[] = {
1078  {0, (CHIP_IS_E3B0(bp)) ?
1081  (CHIP_IS_E3B0(bp)) ?
1084  (CHIP_IS_E3B0(bp)) ?
1087  {1, (CHIP_IS_E3B0(bp)) ?
1090  (CHIP_IS_E3B0(bp)) ?
1093  (CHIP_IS_E3B0(bp)) ?
1096  {4, (CHIP_IS_E3B0(bp)) ?
1099  (CHIP_IS_E3B0(bp)) ?
1102  (CHIP_IS_E3B0(bp)) ?
1105  };
1106 
1107  int i;
1108 
1109  /* Verify the command queues are flushed P0, P1, P4 */
1110  for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1111  bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1112 
1113 
1114  /* Verify the transmission buffers are flushed P0, P1, P4 */
1115  for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1116  bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1117 }
1118 
1119 #define OP_GEN_PARAM(param) \
1120  (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1121 
1122 #define OP_GEN_TYPE(type) \
1123  (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1124 
1125 #define OP_GEN_AGG_VECT(index) \
1126  (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1127 
1128 
1129 static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1130  u32 poll_cnt)
1131 {
1132  struct sdm_op_gen op_gen = {0};
1133 
1134  u32 comp_addr = BAR_CSTRORM_INTMEM +
1136  int ret = 0;
1137 
1138  if (REG_RD(bp, comp_addr)) {
1139  BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1140  return 1;
1141  }
1142 
1145  op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1147 
1148  DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1149  REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1150 
1151  if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1152  BNX2X_ERR("FW final cleanup did not succeed\n");
1153  DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1154  (REG_RD(bp, comp_addr)));
1155  ret = 1;
1156  }
1157  /* Zero completion for nxt FLR */
1158  REG_WR(bp, comp_addr, 0);
1159 
1160  return ret;
1161 }
1162 
1163 static u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1164 {
1165  u16 status;
1166 
1168  return status & PCI_EXP_DEVSTA_TRPND;
1169 }
1170 
1171 /* PF FLR specific routines
1172 */
1173 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1174 {
1175 
1176  /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1177  if (bnx2x_flr_clnup_poll_hw_counter(bp,
1179  "CFC PF usage counter timed out",
1180  poll_cnt))
1181  return 1;
1182 
1183 
1184  /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1185  if (bnx2x_flr_clnup_poll_hw_counter(bp,
1187  "DQ PF usage counter timed out",
1188  poll_cnt))
1189  return 1;
1190 
1191  /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1192  if (bnx2x_flr_clnup_poll_hw_counter(bp,
1193  QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1194  "QM PF usage counter timed out",
1195  poll_cnt))
1196  return 1;
1197 
1198  /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1199  if (bnx2x_flr_clnup_poll_hw_counter(bp,
1200  TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1201  "Timers VNIC usage counter timed out",
1202  poll_cnt))
1203  return 1;
1204  if (bnx2x_flr_clnup_poll_hw_counter(bp,
1206  "Timers NUM_SCANS usage counter timed out",
1207  poll_cnt))
1208  return 1;
1209 
1210  /* Wait DMAE PF usage counter to zero */
1211  if (bnx2x_flr_clnup_poll_hw_counter(bp,
1212  dmae_reg_go_c[INIT_DMAE_C(bp)],
1213  "DMAE dommand register timed out",
1214  poll_cnt))
1215  return 1;
1216 
1217  return 0;
1218 }
1219 
1220 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1221 {
1222  u32 val;
1223 
1224  val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1225  DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1226 
1227  val = REG_RD(bp, PBF_REG_DISABLE_PF);
1228  DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1229 
1230  val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1231  DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1232 
1233  val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1234  DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1235 
1237  DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1238 
1240  DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1241 
1243  DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1244 
1246  DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1247  val);
1248 }
1249 
1250 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1251 {
1252  u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1253 
1254  DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1255 
1256  /* Re-enable PF target read access */
1258 
1259  /* Poll HW usage counters */
1260  DP(BNX2X_MSG_SP, "Polling usage counters\n");
1261  if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1262  return -EBUSY;
1263 
1264  /* Zero the igu 'trailing edge' and 'leading edge' */
1265 
1266  /* Send the FW cleanup command */
1267  if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1268  return -EBUSY;
1269 
1270  /* ATC cleanup */
1271 
1272  /* Verify TX hw is flushed */
1273  bnx2x_tx_hw_flushed(bp, poll_cnt);
1274 
1275  /* Wait 100ms (not adjusted according to platform) */
1276  msleep(100);
1277 
1278  /* Verify no pending pci transactions */
1279  if (bnx2x_is_pcie_pending(bp->pdev))
1280  BNX2X_ERR("PCIE Transactions still pending\n");
1281 
1282  /* Debug */
1283  bnx2x_hw_enable_status(bp);
1284 
1285  /*
1286  * Master enable - Due to WB DMAE writes performed before this
1287  * register is re-initialized as part of the regular function init
1288  */
1290 
1291  return 0;
1292 }
1293 
1294 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1295 {
1296  int port = BP_PORT(bp);
1297  u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1298  u32 val = REG_RD(bp, addr);
1299  bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1300  bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1301  bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1302 
1303  if (msix) {
1308  if (single_msix)
1310  } else if (msi) {
1315  } else {
1320 
1321  if (!CHIP_IS_E1(bp)) {
1323  "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1324 
1325  REG_WR(bp, addr, val);
1326 
1328  }
1329  }
1330 
1331  if (CHIP_IS_E1(bp))
1332  REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1333 
1335  "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1336  (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1337 
1338  REG_WR(bp, addr, val);
1339  /*
1340  * Ensure that HC_CONFIG is written before leading/trailing edge config
1341  */
1342  mmiowb();
1343  barrier();
1344 
1345  if (!CHIP_IS_E1(bp)) {
1346  /* init leading/trailing edge */
1347  if (IS_MF(bp)) {
1348  val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1349  if (bp->port.pmf)
1350  /* enable nig and gpio3 attention */
1351  val |= 0x1100;
1352  } else
1353  val = 0xffff;
1354 
1355  REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1356  REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1357  }
1358 
1359  /* Make sure that interrupts are indeed enabled from here on */
1360  mmiowb();
1361 }
1362 
1363 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1364 {
1365  u32 val;
1366  bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1367  bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1368  bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1369 
1370  val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1371 
1372  if (msix) {
1373  val &= ~(IGU_PF_CONF_INT_LINE_EN |
1375  val |= (IGU_PF_CONF_FUNC_EN |
1378 
1379  if (single_msix)
1381  } else if (msi) {
1382  val &= ~IGU_PF_CONF_INT_LINE_EN;
1383  val |= (IGU_PF_CONF_FUNC_EN |
1387  } else {
1388  val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1389  val |= (IGU_PF_CONF_FUNC_EN |
1393  }
1394 
1395  DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1396  val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1397 
1398  REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1399 
1400  if (val & IGU_PF_CONF_INT_LINE_EN)
1401  pci_intx(bp->pdev, true);
1402 
1403  barrier();
1404 
1405  /* init leading/trailing edge */
1406  if (IS_MF(bp)) {
1407  val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1408  if (bp->port.pmf)
1409  /* enable nig and gpio3 attention */
1410  val |= 0x1100;
1411  } else
1412  val = 0xffff;
1413 
1416 
1417  /* Make sure that interrupts are indeed enabled from here on */
1418  mmiowb();
1419 }
1420 
1421 void bnx2x_int_enable(struct bnx2x *bp)
1422 {
1423  if (bp->common.int_block == INT_BLOCK_HC)
1424  bnx2x_hc_int_enable(bp);
1425  else
1426  bnx2x_igu_int_enable(bp);
1427 }
1428 
1429 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1430 {
1431  int port = BP_PORT(bp);
1432  u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1433  u32 val = REG_RD(bp, addr);
1434 
1435  /*
1436  * in E1 we must use only PCI configuration space to disable
1437  * MSI/MSIX capablility
1438  * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1439  */
1440  if (CHIP_IS_E1(bp)) {
1441  /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1442  * Use mask register to prevent from HC sending interrupts
1443  * after we exit the function
1444  */
1445  REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1446 
1450  } else
1455 
1457  "write %x to HC %d (addr 0x%x)\n",
1458  val, port, addr);
1459 
1460  /* flush all outstanding writes */
1461  mmiowb();
1462 
1463  REG_WR(bp, addr, val);
1464  if (REG_RD(bp, addr) != val)
1465  BNX2X_ERR("BUG! proper val not read from IGU!\n");
1466 }
1467 
1468 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1469 {
1470  u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1471 
1472  val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1473  IGU_PF_CONF_INT_LINE_EN |
1475 
1476  DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
1477 
1478  /* flush all outstanding writes */
1479  mmiowb();
1480 
1481  REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1482  if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1483  BNX2X_ERR("BUG! proper val not read from IGU!\n");
1484 }
1485 
1486 void bnx2x_int_disable(struct bnx2x *bp)
1487 {
1488  if (bp->common.int_block == INT_BLOCK_HC)
1489  bnx2x_hc_int_disable(bp);
1490  else
1491  bnx2x_igu_int_disable(bp);
1492 }
1493 
1494 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1495 {
1496  int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1497  int i, offset;
1498 
1499  if (disable_hw)
1500  /* prevent the HW from sending interrupts */
1501  bnx2x_int_disable(bp);
1502 
1503  /* make sure all ISRs are done */
1504  if (msix) {
1505  synchronize_irq(bp->msix_table[0].vector);
1506  offset = 1;
1507 #ifdef BCM_CNIC
1508  offset++;
1509 #endif
1510  for_each_eth_queue(bp, i)
1511  synchronize_irq(bp->msix_table[offset++].vector);
1512  } else
1513  synchronize_irq(bp->pdev->irq);
1514 
1515  /* make sure sp_task is not running */
1518  flush_workqueue(bnx2x_wq);
1519 }
1520 
1521 /* fast path */
1522 
1523 /*
1524  * General service functions
1525  */
1526 
1527 /* Return true if succeeded to acquire the lock */
1528 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1529 {
1530  u32 lock_status;
1531  u32 resource_bit = (1 << resource);
1532  int func = BP_FUNC(bp);
1533  u32 hw_lock_control_reg;
1534 
1536  "Trying to take a lock on resource %d\n", resource);
1537 
1538  /* Validating that the resource is within range */
1539  if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1541  "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1542  resource, HW_LOCK_MAX_RESOURCE_VALUE);
1543  return false;
1544  }
1545 
1546  if (func <= 5)
1547  hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1548  else
1549  hw_lock_control_reg =
1550  (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1551 
1552  /* Try to acquire the lock */
1553  REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1554  lock_status = REG_RD(bp, hw_lock_control_reg);
1555  if (lock_status & resource_bit)
1556  return true;
1557 
1559  "Failed to get a lock on resource %d\n", resource);
1560  return false;
1561 }
1562 
1571 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1572 {
1573  if (BP_PATH(bp))
1575  else
1577 }
1578 
1586 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1587 {
1588  return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1589 }
1590 
1591 #ifdef BCM_CNIC
1592 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1593 #endif
1594 
1595 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1596 {
1597  struct bnx2x *bp = fp->bp;
1598  int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1599  int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1601  struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1602 
1603  DP(BNX2X_MSG_SP,
1604  "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1605  fp->index, cid, command, bp->state,
1606  rr_cqe->ramrod_cqe.ramrod_type);
1607 
1608  switch (command) {
1610  DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1611  drv_cmd = BNX2X_Q_CMD_UPDATE;
1612  break;
1613 
1615  DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1616  drv_cmd = BNX2X_Q_CMD_SETUP;
1617  break;
1618 
1620  DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1621  drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1622  break;
1623 
1624  case (RAMROD_CMD_ID_ETH_HALT):
1625  DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1626  drv_cmd = BNX2X_Q_CMD_HALT;
1627  break;
1628 
1630  DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1631  drv_cmd = BNX2X_Q_CMD_TERMINATE;
1632  break;
1633 
1634  case (RAMROD_CMD_ID_ETH_EMPTY):
1635  DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1636  drv_cmd = BNX2X_Q_CMD_EMPTY;
1637  break;
1638 
1639  default:
1640  BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1641  command, fp->index);
1642  return;
1643  }
1644 
1645  if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1646  q_obj->complete_cmd(bp, q_obj, drv_cmd))
1647  /* q_obj->complete_cmd() failure means that this was
1648  * an unexpected completion.
1649  *
1650  * In this case we don't want to increase the bp->spq_left
1651  * because apparently we haven't sent this command the first
1652  * place.
1653  */
1654 #ifdef BNX2X_STOP_ON_ERROR
1655  bnx2x_panic();
1656 #else
1657  return;
1658 #endif
1659 
1661  atomic_inc(&bp->cq_spq_left);
1662  /* push the change in bp->spq_left and towards the memory */
1664 
1665  DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1666 
1667  if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1669  /* if Q update ramrod is completed for last Q in AFEX vif set
1670  * flow, then ACK MCP at the end
1671  *
1672  * mark pending ACK to MCP bit.
1673  * prevent case that both bits are cleared.
1674  * At the end of load/unload driver checks that
1675  * sp_state is cleaerd, and this order prevents
1676  * races
1677  */
1680  wmb();
1683 
1684  /* schedule workqueue to send ack to MCP */
1685  queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1686  }
1687 
1688  return;
1689 }
1690 
1691 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1692  u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1693 {
1695 
1696  bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1697  start);
1698 }
1699 
1700 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1701 {
1702  struct bnx2x *bp = netdev_priv(dev_instance);
1703  u16 status = bnx2x_ack_int(bp);
1704  u16 mask;
1705  int i;
1706  u8 cos;
1707 
1708  /* Return here if interrupt is shared and it's not for us */
1709  if (unlikely(status == 0)) {
1710  DP(NETIF_MSG_INTR, "not our interrupt!\n");
1711  return IRQ_NONE;
1712  }
1713  DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1714 
1715 #ifdef BNX2X_STOP_ON_ERROR
1716  if (unlikely(bp->panic))
1717  return IRQ_HANDLED;
1718 #endif
1719 
1720  for_each_eth_queue(bp, i) {
1721  struct bnx2x_fastpath *fp = &bp->fp[i];
1722 
1723  mask = 0x2 << (fp->index + CNIC_PRESENT);
1724  if (status & mask) {
1725  /* Handle Rx or Tx according to SB id */
1726  prefetch(fp->rx_cons_sb);
1727  for_each_cos_in_tx_queue(fp, cos)
1728  prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1730  napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1731  status &= ~mask;
1732  }
1733  }
1734 
1735 #ifdef BCM_CNIC
1736  mask = 0x2;
1737  if (status & (mask | 0x1)) {
1738  struct cnic_ops *c_ops = NULL;
1739 
1740  if (likely(bp->state == BNX2X_STATE_OPEN)) {
1741  rcu_read_lock();
1742  c_ops = rcu_dereference(bp->cnic_ops);
1743  if (c_ops)
1744  c_ops->cnic_handler(bp->cnic_data, NULL);
1745  rcu_read_unlock();
1746  }
1747 
1748  status &= ~mask;
1749  }
1750 #endif
1751 
1752  if (unlikely(status & 0x1)) {
1753  queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1754 
1755  status &= ~0x1;
1756  if (!status)
1757  return IRQ_HANDLED;
1758  }
1759 
1760  if (unlikely(status))
1761  DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1762  status);
1763 
1764  return IRQ_HANDLED;
1765 }
1766 
1767 /* Link */
1768 
1769 /*
1770  * General service functions
1771  */
1772 
1773 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1774 {
1775  u32 lock_status;
1776  u32 resource_bit = (1 << resource);
1777  int func = BP_FUNC(bp);
1778  u32 hw_lock_control_reg;
1779  int cnt;
1780 
1781  /* Validating that the resource is within range */
1782  if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1783  BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1784  resource, HW_LOCK_MAX_RESOURCE_VALUE);
1785  return -EINVAL;
1786  }
1787 
1788  if (func <= 5) {
1789  hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1790  } else {
1791  hw_lock_control_reg =
1792  (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1793  }
1794 
1795  /* Validating that the resource is not already taken */
1796  lock_status = REG_RD(bp, hw_lock_control_reg);
1797  if (lock_status & resource_bit) {
1798  BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1799  lock_status, resource_bit);
1800  return -EEXIST;
1801  }
1802 
1803  /* Try for 5 second every 5ms */
1804  for (cnt = 0; cnt < 1000; cnt++) {
1805  /* Try to acquire the lock */
1806  REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1807  lock_status = REG_RD(bp, hw_lock_control_reg);
1808  if (lock_status & resource_bit)
1809  return 0;
1810 
1811  msleep(5);
1812  }
1813  BNX2X_ERR("Timeout\n");
1814  return -EAGAIN;
1815 }
1816 
1818 {
1819  return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1820 }
1821 
1822 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1823 {
1824  u32 lock_status;
1825  u32 resource_bit = (1 << resource);
1826  int func = BP_FUNC(bp);
1827  u32 hw_lock_control_reg;
1828 
1829  /* Validating that the resource is within range */
1830  if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1831  BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1832  resource, HW_LOCK_MAX_RESOURCE_VALUE);
1833  return -EINVAL;
1834  }
1835 
1836  if (func <= 5) {
1837  hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1838  } else {
1839  hw_lock_control_reg =
1840  (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1841  }
1842 
1843  /* Validating that the resource is currently taken */
1844  lock_status = REG_RD(bp, hw_lock_control_reg);
1845  if (!(lock_status & resource_bit)) {
1846  BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1847  lock_status, resource_bit);
1848  return -EFAULT;
1849  }
1850 
1851  REG_WR(bp, hw_lock_control_reg, resource_bit);
1852  return 0;
1853 }
1854 
1855 
1856 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1857 {
1858  /* The GPIO should be swapped if swap register is set and active */
1859  int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1860  REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1861  int gpio_shift = gpio_num +
1862  (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1863  u32 gpio_mask = (1 << gpio_shift);
1864  u32 gpio_reg;
1865  int value;
1866 
1867  if (gpio_num > MISC_REGISTERS_GPIO_3) {
1868  BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1869  return -EINVAL;
1870  }
1871 
1872  /* read GPIO value */
1873  gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1874 
1875  /* get the requested pin value */
1876  if ((gpio_reg & gpio_mask) == gpio_mask)
1877  value = 1;
1878  else
1879  value = 0;
1880 
1881  DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1882 
1883  return value;
1884 }
1885 
1886 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1887 {
1888  /* The GPIO should be swapped if swap register is set and active */
1889  int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1890  REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1891  int gpio_shift = gpio_num +
1892  (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1893  u32 gpio_mask = (1 << gpio_shift);
1894  u32 gpio_reg;
1895 
1896  if (gpio_num > MISC_REGISTERS_GPIO_3) {
1897  BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1898  return -EINVAL;
1899  }
1900 
1902  /* read GPIO and mask except the float bits */
1903  gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1904 
1905  switch (mode) {
1908  "Set GPIO %d (shift %d) -> output low\n",
1909  gpio_num, gpio_shift);
1910  /* clear FLOAT and set CLR */
1911  gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1912  gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1913  break;
1914 
1917  "Set GPIO %d (shift %d) -> output high\n",
1918  gpio_num, gpio_shift);
1919  /* clear FLOAT and set SET */
1920  gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1921  gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1922  break;
1923 
1926  "Set GPIO %d (shift %d) -> input\n",
1927  gpio_num, gpio_shift);
1928  /* set FLOAT */
1929  gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1930  break;
1931 
1932  default:
1933  break;
1934  }
1935 
1936  REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1938 
1939  return 0;
1940 }
1941 
1943 {
1944  u32 gpio_reg = 0;
1945  int rc = 0;
1946 
1947  /* Any port swapping should be handled by caller. */
1948 
1950  /* read GPIO and mask except the float bits */
1951  gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1952  gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1953  gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1954  gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1955 
1956  switch (mode) {
1958  DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
1959  /* set CLR */
1960  gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
1961  break;
1962 
1964  DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
1965  /* set SET */
1966  gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
1967  break;
1968 
1970  DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
1971  /* set FLOAT */
1972  gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1973  break;
1974 
1975  default:
1976  BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
1977  rc = -EINVAL;
1978  break;
1979  }
1980 
1981  if (rc == 0)
1982  REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1983 
1985 
1986  return rc;
1987 }
1988 
1989 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1990 {
1991  /* The GPIO should be swapped if swap register is set and active */
1992  int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1993  REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1994  int gpio_shift = gpio_num +
1995  (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1996  u32 gpio_mask = (1 << gpio_shift);
1997  u32 gpio_reg;
1998 
1999  if (gpio_num > MISC_REGISTERS_GPIO_3) {
2000  BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2001  return -EINVAL;
2002  }
2003 
2005  /* read GPIO int */
2006  gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2007 
2008  switch (mode) {
2011  "Clear GPIO INT %d (shift %d) -> output low\n",
2012  gpio_num, gpio_shift);
2013  /* clear SET and set CLR */
2014  gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2015  gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2016  break;
2017 
2020  "Set GPIO INT %d (shift %d) -> output high\n",
2021  gpio_num, gpio_shift);
2022  /* clear CLR and set SET */
2023  gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2024  gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2025  break;
2026 
2027  default:
2028  break;
2029  }
2030 
2031  REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2033 
2034  return 0;
2035 }
2036 
2037 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2038 {
2039  u32 spio_mask = (1 << spio_num);
2040  u32 spio_reg;
2041 
2042  if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2043  (spio_num > MISC_REGISTERS_SPIO_7)) {
2044  BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2045  return -EINVAL;
2046  }
2047 
2049  /* read SPIO and mask except the float bits */
2050  spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2051 
2052  switch (mode) {
2054  DP(NETIF_MSG_HW, "Set SPIO %d -> output low\n", spio_num);
2055  /* clear FLOAT and set CLR */
2056  spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2057  spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2058  break;
2059 
2061  DP(NETIF_MSG_HW, "Set SPIO %d -> output high\n", spio_num);
2062  /* clear FLOAT and set SET */
2063  spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2064  spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2065  break;
2066 
2068  DP(NETIF_MSG_HW, "Set SPIO %d -> input\n", spio_num);
2069  /* set FLOAT */
2070  spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2071  break;
2072 
2073  default:
2074  break;
2075  }
2076 
2077  REG_WR(bp, MISC_REG_SPIO, spio_reg);
2079 
2080  return 0;
2081 }
2082 
2083 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2084 {
2085  u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2086  switch (bp->link_vars.ieee_fc &
2089  bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2091  break;
2092 
2094  bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2096  break;
2097 
2099  bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2100  break;
2101 
2102  default:
2103  bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2105  break;
2106  }
2107 }
2108 
2109 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2110 {
2111  if (!BP_NOMCP(bp)) {
2112  u8 rc;
2113  int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2114  u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2115  /*
2116  * Initialize link parameters structure variables
2117  * It is recommended to turn off RX FC for jumbo frames
2118  * for better performance
2119  */
2120  if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2121  bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2122  else
2123  bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2124 
2126 
2127  if (load_mode == LOAD_DIAG) {
2128  struct link_params *lp = &bp->link_params;
2130  /* do PHY loopback at 10G speed, if possible */
2131  if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2132  if (lp->speed_cap_mask[cfx_idx] &
2134  lp->req_line_speed[cfx_idx] =
2135  SPEED_10000;
2136  else
2137  lp->req_line_speed[cfx_idx] =
2138  SPEED_1000;
2139  }
2140  }
2141 
2142  if (load_mode == LOAD_LOOPBACK_EXT) {
2143  struct link_params *lp = &bp->link_params;
2145  }
2146 
2147  rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2148 
2150 
2151  bnx2x_calc_fc_adv(bp);
2152 
2153  if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2155  bnx2x_link_report(bp);
2156  } else
2157  queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2158  bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2159  return rc;
2160  }
2161  BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2162  return -EINVAL;
2163 }
2164 
2165 void bnx2x_link_set(struct bnx2x *bp)
2166 {
2167  if (!BP_NOMCP(bp)) {
2169  bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2171 
2172  bnx2x_calc_fc_adv(bp);
2173  } else
2174  BNX2X_ERR("Bootcode is missing - can not set link\n");
2175 }
2176 
2177 static void bnx2x__link_reset(struct bnx2x *bp)
2178 {
2179  if (!BP_NOMCP(bp)) {
2183  } else
2184  BNX2X_ERR("Bootcode is missing - can not reset link\n");
2185 }
2186 
2188 {
2190  bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2192 }
2193 
2194 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2195 {
2196  u8 rc = 0;
2197 
2198  if (!BP_NOMCP(bp)) {
2200  rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2201  is_serdes);
2203  } else
2204  BNX2X_ERR("Bootcode is missing - can not test link\n");
2205 
2206  return rc;
2207 }
2208 
2209 
2210 /* Calculates the sum of vn_min_rates.
2211  It's needed for further normalizing of the min_rates.
2212  Returns:
2213  sum of vn_min_rates.
2214  or
2215  0 - if all the min_rates are 0.
2216  In the later case fainess algorithm should be deactivated.
2217  If not all min_rates are zero then those that are zeroes will be set to 1.
2218  */
2219 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2220  struct cmng_init_input *input)
2221 {
2222  int all_zero = 1;
2223  int vn;
2224 
2225  for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2226  u32 vn_cfg = bp->mf_config[vn];
2227  u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2228  FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2229 
2230  /* Skip hidden vns */
2231  if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2232  vn_min_rate = 0;
2233  /* If min rate is zero - set it to 1 */
2234  else if (!vn_min_rate)
2235  vn_min_rate = DEF_MIN_RATE;
2236  else
2237  all_zero = 0;
2238 
2239  input->vnic_min_rate[vn] = vn_min_rate;
2240  }
2241 
2242  /* if ETS or all min rates are zeros - disable fairness */
2243  if (BNX2X_IS_ETS_ENABLED(bp)) {
2244  input->flags.cmng_enables &=
2246  DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2247  } else if (all_zero) {
2248  input->flags.cmng_enables &=
2251  "All MIN values are zeroes fairness will be disabled\n");
2252  } else
2253  input->flags.cmng_enables |=
2255 }
2256 
2257 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2258  struct cmng_init_input *input)
2259 {
2260  u16 vn_max_rate;
2261  u32 vn_cfg = bp->mf_config[vn];
2262 
2263  if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2264  vn_max_rate = 0;
2265  else {
2266  u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2267 
2268  if (IS_MF_SI(bp)) {
2269  /* maxCfg in percents of linkspeed */
2270  vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2271  } else /* SD modes */
2272  /* maxCfg is absolute in 100Mb units */
2273  vn_max_rate = maxCfg * 100;
2274  }
2275 
2276  DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2277 
2278  input->vnic_max_rate[vn] = vn_max_rate;
2279 }
2280 
2281 
2282 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2283 {
2284  if (CHIP_REV_IS_SLOW(bp))
2285  return CMNG_FNS_NONE;
2286  if (IS_MF(bp))
2287  return CMNG_FNS_MINMAX;
2288 
2289  return CMNG_FNS_NONE;
2290 }
2291 
2292 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2293 {
2294  int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2295 
2296  if (BP_NOMCP(bp))
2297  return; /* what should be the default bvalue in this case */
2298 
2299  /* For 2 port configuration the absolute function number formula
2300  * is:
2301  * abs_func = 2 * vn + BP_PORT + BP_PATH
2302  *
2303  * and there are 4 functions per port
2304  *
2305  * For 4 port configuration it is
2306  * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2307  *
2308  * and there are 2 functions per port
2309  */
2310  for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2311  int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2312 
2313  if (func >= E1H_FUNC_MAX)
2314  break;
2315 
2316  bp->mf_config[vn] =
2317  MF_CFG_RD(bp, func_mf_config[func].config);
2318  }
2319  if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2320  DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2321  bp->flags |= MF_FUNC_DIS;
2322  } else {
2323  DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2324  bp->flags &= ~MF_FUNC_DIS;
2325  }
2326 }
2327 
2328 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2329 {
2330  struct cmng_init_input input;
2331  memset(&input, 0, sizeof(struct cmng_init_input));
2332 
2333  input.port_rate = bp->link_vars.line_speed;
2334 
2335  if (cmng_type == CMNG_FNS_MINMAX) {
2336  int vn;
2337 
2338  /* read mf conf from shmem */
2339  if (read_cfg)
2340  bnx2x_read_mf_cfg(bp);
2341 
2342  /* vn_weight_sum and enable fairness if not 0 */
2343  bnx2x_calc_vn_min(bp, &input);
2344 
2345  /* calculate and set min-max rate for each vn */
2346  if (bp->port.pmf)
2347  for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2348  bnx2x_calc_vn_max(bp, vn, &input);
2349 
2350  /* always enable rate shaping and fairness */
2351  input.flags.cmng_enables |=
2353 
2354  bnx2x_init_cmng(&input, &bp->cmng);
2355  return;
2356  }
2357 
2358  /* rate shaping and fairness are disabled */
2360  "rate shaping and fairness are disabled\n");
2361 }
2362 
2363 static void storm_memset_cmng(struct bnx2x *bp,
2364  struct cmng_init *cmng,
2365  u8 port)
2366 {
2367  int vn;
2368  size_t size = sizeof(struct cmng_struct_per_port);
2369 
2370  u32 addr = BAR_XSTRORM_INTMEM +
2372 
2373  __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2374 
2375  for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2376  int func = func_by_vn(bp, vn);
2377 
2378  addr = BAR_XSTRORM_INTMEM +
2380  size = sizeof(struct rate_shaping_vars_per_vn);
2381  __storm_memset_struct(bp, addr, size,
2382  (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2383 
2384  addr = BAR_XSTRORM_INTMEM +
2386  size = sizeof(struct fairness_vars_per_vn);
2387  __storm_memset_struct(bp, addr, size,
2388  (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2389  }
2390 }
2391 
2392 /* This function is called upon link interrupt */
2393 static void bnx2x_link_attn(struct bnx2x *bp)
2394 {
2395  /* Make sure that we are synced with the current statistics */
2397 
2399 
2400  if (bp->link_vars.link_up) {
2401 
2402  /* dropless flow control */
2403  if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2404  int port = BP_PORT(bp);
2405  u32 pause_enabled = 0;
2406 
2407  if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2408  pause_enabled = 1;
2409 
2412  pause_enabled);
2413  }
2414 
2415  if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2416  struct host_port_stats *pstats;
2417 
2418  pstats = bnx2x_sp(bp, port_stats);
2419  /* reset old mac stats */
2420  memset(&(pstats->mac_stx[0]), 0,
2421  sizeof(struct mac_stx));
2422  }
2423  if (bp->state == BNX2X_STATE_OPEN)
2425  }
2426 
2427  if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2428  int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2429 
2430  if (cmng_fns != CMNG_FNS_NONE) {
2431  bnx2x_cmng_fns_init(bp, false, cmng_fns);
2432  storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2433  } else
2434  /* rate shaping and fairness are disabled */
2436  "single function mode without fairness\n");
2437  }
2438 
2439  __bnx2x_link_report(bp);
2440 
2441  if (IS_MF(bp))
2442  bnx2x_link_sync_notify(bp);
2443 }
2444 
2446 {
2447  if (bp->state != BNX2X_STATE_OPEN)
2448  return;
2449 
2450  /* read updated dcb configuration */
2452 
2454 
2455  if (bp->link_vars.link_up)
2457  else
2459 
2460  /* indicate link status */
2461  bnx2x_link_report(bp);
2462 }
2463 
2464 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2465  u16 vlan_val, u8 allowed_prio)
2466 {
2467  struct bnx2x_func_state_params func_params = {0};
2468  struct bnx2x_func_afex_update_params *f_update_params =
2469  &func_params.params.afex_update;
2470 
2471  func_params.f_obj = &bp->func_obj;
2472  func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2473 
2474  /* no need to wait for RAMROD completion, so don't
2475  * set RAMROD_COMP_WAIT flag
2476  */
2477 
2478  f_update_params->vif_id = vifid;
2479  f_update_params->afex_default_vlan = vlan_val;
2480  f_update_params->allowed_priorities = allowed_prio;
2481 
2482  /* if ramrod can not be sent, response to MCP immediately */
2483  if (bnx2x_func_state_change(bp, &func_params) < 0)
2485 
2486  return 0;
2487 }
2488 
2489 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2490  u16 vif_index, u8 func_bit_map)
2491 {
2492  struct bnx2x_func_state_params func_params = {0};
2493  struct bnx2x_func_afex_viflists_params *update_params =
2494  &func_params.params.afex_viflists;
2495  int rc;
2496  u32 drv_msg_code;
2497 
2498  /* validate only LIST_SET and LIST_GET are received from switch */
2499  if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2500  BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2501  cmd_type);
2502 
2503  func_params.f_obj = &bp->func_obj;
2504  func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2505 
2506  /* set parameters according to cmd_type */
2507  update_params->afex_vif_list_command = cmd_type;
2508  update_params->vif_list_index = cpu_to_le16(vif_index);
2509  update_params->func_bit_map =
2510  (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2511  update_params->func_to_clear = 0;
2512  drv_msg_code =
2513  (cmd_type == VIF_LIST_RULE_GET) ?
2516 
2517  /* if ramrod can not be sent, respond to MCP immediately for
2518  * SET and GET requests (other are not triggered from MCP)
2519  */
2520  rc = bnx2x_func_state_change(bp, &func_params);
2521  if (rc < 0)
2522  bnx2x_fw_command(bp, drv_msg_code, 0);
2523 
2524  return 0;
2525 }
2526 
2527 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2528 {
2529  struct afex_stats afex_stats;
2530  u32 func = BP_ABS_FUNC(bp);
2531  u32 mf_config;
2532  u16 vlan_val;
2533  u32 vlan_prio;
2534  u16 vif_id;
2535  u8 allowed_prio;
2536  u8 vlan_mode;
2537  u32 addr_to_write, vifid, addrs, stats_type, i;
2538 
2539  if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2540  vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2541  DP(BNX2X_MSG_MCP,
2542  "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2543  bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2544  }
2545 
2546  if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2547  vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2548  addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2549  DP(BNX2X_MSG_MCP,
2550  "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2551  vifid, addrs);
2552  bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2553  addrs);
2554  }
2555 
2556  if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2557  addr_to_write = SHMEM2_RD(bp,
2558  afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2559  stats_type = SHMEM2_RD(bp,
2560  afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2561 
2562  DP(BNX2X_MSG_MCP,
2563  "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2564  addr_to_write);
2565 
2566  bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2567 
2568  /* write response to scratchpad, for MCP */
2569  for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2570  REG_WR(bp, addr_to_write + i*sizeof(u32),
2571  *(((u32 *)(&afex_stats))+i));
2572 
2573  /* send ack message to MCP */
2575  }
2576 
2577  if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2578  mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2579  bp->mf_config[BP_VN(bp)] = mf_config;
2580  DP(BNX2X_MSG_MCP,
2581  "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2582  mf_config);
2583 
2584  /* if VIF_SET is "enabled" */
2585  if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2586  /* set rate limit directly to internal RAM */
2587  struct cmng_init_input cmng_input;
2588  struct rate_shaping_vars_per_vn m_rs_vn;
2589  size_t size = sizeof(struct rate_shaping_vars_per_vn);
2590  u32 addr = BAR_XSTRORM_INTMEM +
2592 
2593  bp->mf_config[BP_VN(bp)] = mf_config;
2594 
2595  bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2596  m_rs_vn.vn_counter.rate =
2597  cmng_input.vnic_max_rate[BP_VN(bp)];
2598  m_rs_vn.vn_counter.quota =
2599  (m_rs_vn.vn_counter.rate *
2601 
2602  __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2603 
2604  /* read relevant values from mf_cfg struct in shmem */
2605  vif_id =
2606  (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2609  vlan_val =
2610  (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2613  vlan_prio = (mf_config &
2616  vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2617  vlan_mode =
2618  (MF_CFG_RD(bp,
2619  func_mf_config[func].afex_config) &
2622  allowed_prio =
2623  (MF_CFG_RD(bp,
2624  func_mf_config[func].afex_config) &
2627 
2628  /* send ramrod to FW, return in case of failure */
2629  if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2630  allowed_prio))
2631  return;
2632 
2633  bp->afex_def_vlan_tag = vlan_val;
2634  bp->afex_vlan_mode = vlan_mode;
2635  } else {
2636  /* notify link down because BP->flags is disabled */
2637  bnx2x_link_report(bp);
2638 
2639  /* send INVALID VIF ramrod to FW */
2640  bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2641 
2642  /* Reset the default afex VLAN */
2643  bp->afex_def_vlan_tag = -1;
2644  }
2645  }
2646 }
2647 
2648 static void bnx2x_pmf_update(struct bnx2x *bp)
2649 {
2650  int port = BP_PORT(bp);
2651  u32 val;
2652 
2653  bp->port.pmf = 1;
2654  DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2655 
2656  /*
2657  * We need the mb() to ensure the ordering between the writing to
2658  * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2659  */
2660  smp_mb();
2661 
2662  /* queue a periodic task */
2663  queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2664 
2666 
2667  /* enable nig attention */
2668  val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2669  if (bp->common.int_block == INT_BLOCK_HC) {
2670  REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2671  REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2672  } else if (!CHIP_IS_E1x(bp)) {
2675  }
2676 
2678 }
2679 
2680 /* end of Link */
2681 
2682 /* slow path */
2683 
2684 /*
2685  * General service functions
2686  */
2687 
2688 /* send the MCP a request, block until there is a reply */
2690 {
2691  int mb_idx = BP_FW_MB_IDX(bp);
2692  u32 seq;
2693  u32 rc = 0;
2694  u32 cnt = 1;
2695  u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2696 
2697  mutex_lock(&bp->fw_mb_mutex);
2698  seq = ++bp->fw_seq;
2699  SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2700  SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2701 
2702  DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2703  (command | seq), param);
2704 
2705  do {
2706  /* let the FW do it's magic ... */
2707  msleep(delay);
2708 
2709  rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2710 
2711  /* Give the FW up to 5 second (500*10ms) */
2712  } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2713 
2714  DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2715  cnt*delay, rc, seq);
2716 
2717  /* is this a reply to our command? */
2718  if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2719  rc &= FW_MSG_CODE_MASK;
2720  else {
2721  /* FW BUG! */
2722  BNX2X_ERR("FW failed to respond!\n");
2723  bnx2x_fw_dump(bp);
2724  rc = 0;
2725  }
2726  mutex_unlock(&bp->fw_mb_mutex);
2727 
2728  return rc;
2729 }
2730 
2731 
2732 static void storm_memset_func_cfg(struct bnx2x *bp,
2733  struct tstorm_eth_function_common_config *tcfg,
2734  u16 abs_fid)
2735 {
2736  size_t size = sizeof(struct tstorm_eth_function_common_config);
2737 
2738  u32 addr = BAR_TSTRORM_INTMEM +
2740 
2741  __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2742 }
2743 
2745 {
2746  if (CHIP_IS_E1x(bp)) {
2747  struct tstorm_eth_function_common_config tcfg = {0};
2748 
2749  storm_memset_func_cfg(bp, &tcfg, p->func_id);
2750  }
2751 
2752  /* Enable the function in the FW */
2753  storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2754  storm_memset_func_en(bp, p->func_id, 1);
2755 
2756  /* spq */
2757  if (p->func_flgs & FUNC_FLG_SPQ) {
2758  storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2761  }
2762 }
2763 
2773 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2774  struct bnx2x_fastpath *fp,
2775  bool zero_stats)
2776 {
2777  unsigned long flags = 0;
2778 
2779  /* PF driver will always initialize the Queue to an ACTIVE state */
2780  __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2781 
2782  /* tx only connections collect statistics (on the same index as the
2783  * parent connection). The statistics are zeroed when the parent
2784  * connection is initialized.
2785  */
2786 
2787  __set_bit(BNX2X_Q_FLG_STATS, &flags);
2788  if (zero_stats)
2790 
2791 
2792  return flags;
2793 }
2794 
2795 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2796  struct bnx2x_fastpath *fp,
2797  bool leading)
2798 {
2799  unsigned long flags = 0;
2800 
2801  /* calculate other queue flags */
2802  if (IS_MF_SD(bp))
2803  __set_bit(BNX2X_Q_FLG_OV, &flags);
2804 
2805  if (IS_FCOE_FP(fp)) {
2806  __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2807  /* For FCoE - force usage of default priority (for afex) */
2809  }
2810 
2811  if (!fp->disable_tpa) {
2812  __set_bit(BNX2X_Q_FLG_TPA, &flags);
2814  if (fp->mode == TPA_MODE_GRO)
2815  __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2816  }
2817 
2818  if (leading) {
2820  __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2821  }
2822 
2823  /* Always set HW VLAN stripping */
2824  __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2825 
2826  /* configure silent vlan removal */
2827  if (IS_MF_AFEX(bp))
2829 
2830 
2831  return flags | bnx2x_get_common_flags(bp, fp, true);
2832 }
2833 
2834 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2835  struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2836  u8 cos)
2837 {
2838  gen_init->stat_id = bnx2x_stats_id(fp);
2839  gen_init->spcl_id = fp->cl_id;
2840 
2841  /* Always use mini-jumbo MTU for FCoE L2 ring */
2842  if (IS_FCOE_FP(fp))
2843  gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2844  else
2845  gen_init->mtu = bp->dev->mtu;
2846 
2847  gen_init->cos = cos;
2848 }
2849 
2850 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2851  struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2852  struct bnx2x_rxq_setup_params *rxq_init)
2853 {
2854  u8 max_sge = 0;
2855  u16 sge_sz = 0;
2856  u16 tpa_agg_size = 0;
2857 
2858  if (!fp->disable_tpa) {
2859  pause->sge_th_lo = SGE_TH_LO(bp);
2860  pause->sge_th_hi = SGE_TH_HI(bp);
2861 
2862  /* validate SGE ring has enough to cross high threshold */
2863  WARN_ON(bp->dropless_fc &&
2864  pause->sge_th_hi + FW_PREFETCH_CNT >
2866 
2867  tpa_agg_size = min_t(u32,
2868  (min_t(u32, 8, MAX_SKB_FRAGS) *
2869  SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2870  max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2872  max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2874  sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2875  0xffff);
2876  }
2877 
2878  /* pause - not for e1 */
2879  if (!CHIP_IS_E1(bp)) {
2880  pause->bd_th_lo = BD_TH_LO(bp);
2881  pause->bd_th_hi = BD_TH_HI(bp);
2882 
2883  pause->rcq_th_lo = RCQ_TH_LO(bp);
2884  pause->rcq_th_hi = RCQ_TH_HI(bp);
2885  /*
2886  * validate that rings have enough entries to cross
2887  * high thresholds
2888  */
2889  WARN_ON(bp->dropless_fc &&
2890  pause->bd_th_hi + FW_PREFETCH_CNT >
2891  bp->rx_ring_size);
2892  WARN_ON(bp->dropless_fc &&
2893  pause->rcq_th_hi + FW_PREFETCH_CNT >
2895 
2896  pause->pri_map = 1;
2897  }
2898 
2899  /* rxq setup */
2900  rxq_init->dscr_map = fp->rx_desc_mapping;
2901  rxq_init->sge_map = fp->rx_sge_mapping;
2902  rxq_init->rcq_map = fp->rx_comp_mapping;
2903  rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2904 
2905  /* This should be a maximum number of data bytes that may be
2906  * placed on the BD (not including paddings).
2907  */
2908  rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
2910 
2911  rxq_init->cl_qzone_id = fp->cl_qzone_id;
2912  rxq_init->tpa_agg_sz = tpa_agg_size;
2913  rxq_init->sge_buf_sz = sge_sz;
2914  rxq_init->max_sges_pkt = max_sge;
2915  rxq_init->rss_engine_id = BP_FUNC(bp);
2916  rxq_init->mcast_engine_id = BP_FUNC(bp);
2917 
2918  /* Maximum number or simultaneous TPA aggregation for this Queue.
2919  *
2920  * For PF Clients it should be the maximum avaliable number.
2921  * VF driver(s) may want to define it to a smaller value.
2922  */
2923  rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
2924 
2926  rxq_init->fw_sb_id = fp->fw_sb_id;
2927 
2928  if (IS_FCOE_FP(fp))
2930  else
2932  /* configure silent vlan removal
2933  * if multi function mode is afex, then mask default vlan
2934  */
2935  if (IS_MF_AFEX(bp)) {
2936  rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
2937  rxq_init->silent_removal_mask = VLAN_VID_MASK;
2938  }
2939 }
2940 
2941 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2942  struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2943  u8 cos)
2944 {
2945  txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
2946  txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2947  txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2948  txq_init->fw_sb_id = fp->fw_sb_id;
2949 
2950  /*
2951  * set the tss leading client id for TX classfication ==
2952  * leading RSS client id
2953  */
2954  txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2955 
2956  if (IS_FCOE_FP(fp)) {
2959  }
2960 }
2961 
2962 static void bnx2x_pf_init(struct bnx2x *bp)
2963 {
2964  struct bnx2x_func_init_params func_init = {0};
2965  struct event_ring_data eq_data = { {0} };
2966  u16 flags;
2967 
2968  if (!CHIP_IS_E1x(bp)) {
2969  /* reset IGU PF statistics: MSIX + ATTN */
2970  /* PF */
2973  (CHIP_MODE_IS_4_PORT(bp) ?
2974  BP_FUNC(bp) : BP_VN(bp))*4, 0);
2975  /* ATTN */
2979  (CHIP_MODE_IS_4_PORT(bp) ?
2980  BP_FUNC(bp) : BP_VN(bp))*4, 0);
2981  }
2982 
2983  /* function setup flags */
2985 
2986  /* This flag is relevant for E1x only.
2987  * E2 doesn't have a TPA configuration in a function level.
2988  */
2989  flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2990 
2991  func_init.func_flgs = flags;
2992  func_init.pf_id = BP_FUNC(bp);
2993  func_init.func_id = BP_FUNC(bp);
2994  func_init.spq_map = bp->spq_mapping;
2995  func_init.spq_prod = bp->spq_prod_idx;
2996 
2997  bnx2x_func_init(bp, &func_init);
2998 
2999  memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3000 
3001  /*
3002  * Congestion management values depend on the link rate
3003  * There is no active link so initial link rate is set to 10 Gbps.
3004  * When the link comes up The congestion management values are
3005  * re-calculated according to the actual link rate.
3006  */
3007  bp->link_vars.line_speed = SPEED_10000;
3008  bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3009 
3010  /* Only the PMF sets the HW */
3011  if (bp->port.pmf)
3012  storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3013 
3014  /* init Event Queue */
3015  eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3016  eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3017  eq_data.producer = bp->eq_prod;
3018  eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3019  eq_data.sb_id = DEF_SB_ID;
3020  storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3021 }
3022 
3023 
3024 static void bnx2x_e1h_disable(struct bnx2x *bp)
3025 {
3026  int port = BP_PORT(bp);
3027 
3028  bnx2x_tx_disable(bp);
3029 
3030  REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3031 }
3032 
3033 static void bnx2x_e1h_enable(struct bnx2x *bp)
3034 {
3035  int port = BP_PORT(bp);
3036 
3037  REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3038 
3039  /* Tx queue should be only reenabled */
3040  netif_tx_wake_all_queues(bp->dev);
3041 
3042  /*
3043  * Should not call netif_carrier_on since it will be called if the link
3044  * is up when checking for link state
3045  */
3046 }
3047 
3048 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3049 
3050 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3051 {
3052  struct eth_stats_info *ether_stat =
3053  &bp->slowpath->drv_info_to_mcp.ether_stat;
3054 
3055  strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3057 
3058  bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3060  ether_stat->mac_local);
3061 
3062  ether_stat->mtu_size = bp->dev->mtu;
3063 
3064  if (bp->dev->features & NETIF_F_RXCSUM)
3066  if (bp->dev->features & NETIF_F_TSO)
3067  ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3068  ether_stat->feature_flags |= bp->common.boot_mode;
3069 
3070  ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3071 
3072  ether_stat->txq_size = bp->tx_ring_size;
3073  ether_stat->rxq_size = bp->rx_ring_size;
3074 }
3075 
3076 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3077 {
3078 #ifdef BCM_CNIC
3079  struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3080  struct fcoe_stats_info *fcoe_stat =
3081  &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3082 
3083  memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT,
3084  bp->fip_mac, ETH_ALEN);
3085 
3086  fcoe_stat->qos_priority =
3088 
3089  /* insert FCoE stats from ramrod response */
3090  if (!NO_FCOE(bp)) {
3091  struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3092  &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3093  tstorm_queue_statistics;
3094 
3095  struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3096  &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3097  xstorm_queue_statistics;
3098 
3099  struct fcoe_statistics_params *fw_fcoe_stat =
3100  &bp->fw_stats_data->fcoe;
3101 
3102  ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
3103  fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3104 
3105  ADD_64(fcoe_stat->rx_bytes_hi,
3106  fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3107  fcoe_stat->rx_bytes_lo,
3108  fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3109 
3110  ADD_64(fcoe_stat->rx_bytes_hi,
3111  fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3112  fcoe_stat->rx_bytes_lo,
3113  fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3114 
3115  ADD_64(fcoe_stat->rx_bytes_hi,
3116  fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3117  fcoe_stat->rx_bytes_lo,
3118  fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3119 
3120  ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3121  fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3122 
3123  ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3124  fcoe_q_tstorm_stats->rcv_ucast_pkts);
3125 
3126  ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3127  fcoe_q_tstorm_stats->rcv_bcast_pkts);
3128 
3129  ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3130  fcoe_q_tstorm_stats->rcv_mcast_pkts);
3131 
3132  ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
3133  fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3134 
3135  ADD_64(fcoe_stat->tx_bytes_hi,
3136  fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3137  fcoe_stat->tx_bytes_lo,
3138  fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3139 
3140  ADD_64(fcoe_stat->tx_bytes_hi,
3141  fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3142  fcoe_stat->tx_bytes_lo,
3143  fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3144 
3145  ADD_64(fcoe_stat->tx_bytes_hi,
3146  fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3147  fcoe_stat->tx_bytes_lo,
3148  fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3149 
3150  ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3151  fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3152 
3153  ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3154  fcoe_q_xstorm_stats->ucast_pkts_sent);
3155 
3156  ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3157  fcoe_q_xstorm_stats->bcast_pkts_sent);
3158 
3159  ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3160  fcoe_q_xstorm_stats->mcast_pkts_sent);
3161  }
3162 
3163  /* ask L5 driver to add data to the struct */
3164  bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3165 #endif
3166 }
3167 
3168 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3169 {
3170 #ifdef BCM_CNIC
3171  struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3172  struct iscsi_stats_info *iscsi_stat =
3173  &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3174 
3175  memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT,
3176  bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
3177 
3178  iscsi_stat->qos_priority =
3180 
3181  /* ask L5 driver to add data to the struct */
3182  bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3183 #endif
3184 }
3185 
3186 /* called due to MCP event (on pmf):
3187  * reread new bandwidth configuration
3188  * configure FW
3189  * notify others function about the change
3190  */
3191 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3192 {
3193  if (bp->link_vars.link_up) {
3194  bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3195  bnx2x_link_sync_notify(bp);
3196  }
3197  storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3198 }
3199 
3200 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3201 {
3202  bnx2x_config_mf_bw(bp);
3204 }
3205 
3206 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3207 {
3208  DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3210 }
3211 
3212 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3213 {
3214  enum drv_info_opcode op_code;
3215  u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3216 
3217  /* if drv_info version supported by MFW doesn't match - send NACK */
3218  if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3220  return;
3221  }
3222 
3223  op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3225 
3226  memset(&bp->slowpath->drv_info_to_mcp, 0,
3227  sizeof(union drv_info_to_mcp));
3228 
3229  switch (op_code) {
3230  case ETH_STATS_OPCODE:
3231  bnx2x_drv_info_ether_stat(bp);
3232  break;
3233  case FCOE_STATS_OPCODE:
3234  bnx2x_drv_info_fcoe_stat(bp);
3235  break;
3236  case ISCSI_STATS_OPCODE:
3237  bnx2x_drv_info_iscsi_stat(bp);
3238  break;
3239  default:
3240  /* if op code isn't supported - send NACK */
3242  return;
3243  }
3244 
3245  /* if we got drv_info attn from MFW then these fields are defined in
3246  * shmem2 for sure
3247  */
3248  SHMEM2_WR(bp, drv_info_host_addr_lo,
3250  SHMEM2_WR(bp, drv_info_host_addr_hi,
3252 
3254 }
3255 
3256 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3257 {
3258  DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3259 
3260  if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3261 
3262  /*
3263  * This is the only place besides the function initialization
3264  * where the bp->flags can change so it is done without any
3265  * locks
3266  */
3267  if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3268  DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3269  bp->flags |= MF_FUNC_DIS;
3270 
3271  bnx2x_e1h_disable(bp);
3272  } else {
3273  DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3274  bp->flags &= ~MF_FUNC_DIS;
3275 
3276  bnx2x_e1h_enable(bp);
3277  }
3278  dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3279  }
3280  if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3281  bnx2x_config_mf_bw(bp);
3282  dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3283  }
3284 
3285  /* Report results to MCP */
3286  if (dcc_event)
3288  else
3290 }
3291 
3292 /* must be called under the spq lock */
3293 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3294 {
3295  struct eth_spe *next_spe = bp->spq_prod_bd;
3296 
3297  if (bp->spq_prod_bd == bp->spq_last_bd) {
3298  bp->spq_prod_bd = bp->spq;
3299  bp->spq_prod_idx = 0;
3300  DP(BNX2X_MSG_SP, "end of spq\n");
3301  } else {
3302  bp->spq_prod_bd++;
3303  bp->spq_prod_idx++;
3304  }
3305  return next_spe;
3306 }
3307 
3308 /* must be called under the spq lock */
3309 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3310 {
3311  int func = BP_FUNC(bp);
3312 
3313  /*
3314  * Make sure that BD data is updated before writing the producer:
3315  * BD data is written to the memory, the producer is read from the
3316  * memory, thus we need a full memory barrier to ensure the ordering.
3317  */
3318  mb();
3319 
3321  bp->spq_prod_idx);
3322  mmiowb();
3323 }
3324 
3331 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3332 {
3333  if ((cmd_type == NONE_CONNECTION_TYPE) ||
3336  (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3338  (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3340  return true;
3341  else
3342  return false;
3343 
3344 }
3345 
3346 
3361 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3362  u32 data_hi, u32 data_lo, int cmd_type)
3363 {
3364  struct eth_spe *spe;
3365  u16 type;
3366  bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3367 
3368 #ifdef BNX2X_STOP_ON_ERROR
3369  if (unlikely(bp->panic)) {
3370  BNX2X_ERR("Can't post SP when there is panic\n");
3371  return -EIO;
3372  }
3373 #endif
3374 
3375  spin_lock_bh(&bp->spq_lock);
3376 
3377  if (common) {
3378  if (!atomic_read(&bp->eq_spq_left)) {
3379  BNX2X_ERR("BUG! EQ ring full!\n");
3380  spin_unlock_bh(&bp->spq_lock);
3381  bnx2x_panic();
3382  return -EBUSY;
3383  }
3384  } else if (!atomic_read(&bp->cq_spq_left)) {
3385  BNX2X_ERR("BUG! SPQ ring full!\n");
3386  spin_unlock_bh(&bp->spq_lock);
3387  bnx2x_panic();
3388  return -EBUSY;
3389  }
3390 
3391  spe = bnx2x_sp_get_next(bp);
3392 
3393  /* CID needs port number to be encoded int it */
3394  spe->hdr.conn_and_cmd_data =
3395  cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3396  HW_CID(bp, cid));
3397 
3398  type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3399 
3400  type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3402 
3403  spe->hdr.type = cpu_to_le16(type);
3404 
3405  spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3406  spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3407 
3408  /*
3409  * It's ok if the actual decrement is issued towards the memory
3410  * somewhere between the spin_lock and spin_unlock. Thus no
3411  * more explict memory barrier is needed.
3412  */
3413  if (common)
3414  atomic_dec(&bp->eq_spq_left);
3415  else
3416  atomic_dec(&bp->cq_spq_left);
3417 
3418 
3419  DP(BNX2X_MSG_SP,
3420  "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3421  bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3422  (u32)(U64_LO(bp->spq_mapping) +
3423  (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3424  HW_CID(bp, cid), data_hi, data_lo, type,
3426 
3427  bnx2x_sp_prod_update(bp);
3428  spin_unlock_bh(&bp->spq_lock);
3429  return 0;
3430 }
3431 
3432 /* acquire split MCP access lock register */
3433 static int bnx2x_acquire_alr(struct bnx2x *bp)
3434 {
3435  u32 j, val;
3436  int rc = 0;
3437 
3438  might_sleep();
3439  for (j = 0; j < 1000; j++) {
3440  val = (1UL << 31);
3441  REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3442  val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3443  if (val & (1L << 31))
3444  break;
3445 
3446  msleep(5);
3447  }
3448  if (!(val & (1L << 31))) {
3449  BNX2X_ERR("Cannot acquire MCP access lock register\n");
3450  rc = -EBUSY;
3451  }
3452 
3453  return rc;
3454 }
3455 
3456 /* release split MCP access lock register */
3457 static void bnx2x_release_alr(struct bnx2x *bp)
3458 {
3459  REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3460 }
3461 
3462 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3463 #define BNX2X_DEF_SB_IDX 0x0002
3464 
3465 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3466 {
3467  struct host_sp_status_block *def_sb = bp->def_status_blk;
3468  u16 rc = 0;
3469 
3470  barrier(); /* status block is written to by the chip */
3471  if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3472  bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3473  rc |= BNX2X_DEF_SB_ATT_IDX;
3474  }
3475 
3476  if (bp->def_idx != def_sb->sp_sb.running_index) {
3477  bp->def_idx = def_sb->sp_sb.running_index;
3478  rc |= BNX2X_DEF_SB_IDX;
3479  }
3480 
3481  /* Do not reorder: indecies reading should complete before handling */
3482  barrier();
3483  return rc;
3484 }
3485 
3486 /*
3487  * slow path service functions
3488  */
3489 
3490 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3491 {
3492  int port = BP_PORT(bp);
3493  u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3495  u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3497  u32 aeu_mask;
3498  u32 nig_mask = 0;
3499  u32 reg_addr;
3500 
3501  if (bp->attn_state & asserted)
3502  BNX2X_ERR("IGU ERROR\n");
3503 
3505  aeu_mask = REG_RD(bp, aeu_addr);
3506 
3507  DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3508  aeu_mask, asserted);
3509  aeu_mask &= ~(asserted & 0x3ff);
3510  DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3511 
3512  REG_WR(bp, aeu_addr, aeu_mask);
3514 
3515  DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3516  bp->attn_state |= asserted;
3517  DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3518 
3519  if (asserted & ATTN_HARD_WIRED_MASK) {
3520  if (asserted & ATTN_NIG_FOR_FUNC) {
3521 
3523 
3524  /* save nig interrupt mask */
3525  nig_mask = REG_RD(bp, nig_int_mask_addr);
3526 
3527  /* If nig_mask is not set, no need to call the update
3528  * function.
3529  */
3530  if (nig_mask) {
3531  REG_WR(bp, nig_int_mask_addr, 0);
3532 
3533  bnx2x_link_attn(bp);
3534  }
3535 
3536  /* handle unicore attn? */
3537  }
3538  if (asserted & ATTN_SW_TIMER_4_FUNC)
3539  DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3540 
3541  if (asserted & GPIO_2_FUNC)
3542  DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3543 
3544  if (asserted & GPIO_3_FUNC)
3545  DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3546 
3547  if (asserted & GPIO_4_FUNC)
3548  DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3549 
3550  if (port == 0) {
3551  if (asserted & ATTN_GENERAL_ATTN_1) {
3552  DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3554  }
3555  if (asserted & ATTN_GENERAL_ATTN_2) {
3556  DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3558  }
3559  if (asserted & ATTN_GENERAL_ATTN_3) {
3560  DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3562  }
3563  } else {
3564  if (asserted & ATTN_GENERAL_ATTN_4) {
3565  DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3567  }
3568  if (asserted & ATTN_GENERAL_ATTN_5) {
3569  DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3571  }
3572  if (asserted & ATTN_GENERAL_ATTN_6) {
3573  DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3575  }
3576  }
3577 
3578  } /* if hardwired */
3579 
3580  if (bp->common.int_block == INT_BLOCK_HC)
3581  reg_addr = (HC_REG_COMMAND_REG + port*32 +
3583  else
3584  reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3585 
3586  DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3587  (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3588  REG_WR(bp, reg_addr, asserted);
3589 
3590  /* now set back the mask */
3591  if (asserted & ATTN_NIG_FOR_FUNC) {
3592  REG_WR(bp, nig_int_mask_addr, nig_mask);
3594  }
3595 }
3596 
3597 static void bnx2x_fan_failure(struct bnx2x *bp)
3598 {
3599  int port = BP_PORT(bp);
3600  u32 ext_phy_config;
3601  /* mark the failure */
3602  ext_phy_config =
3603  SHMEM_RD(bp,
3604  dev_info.port_hw_config[port].external_phy_config);
3605 
3606  ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3607  ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3608  SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3609  ext_phy_config);
3610 
3611  /* log the failure */
3612  netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3613  "Please contact OEM Support for assistance\n");
3614 
3615  /*
3616  * Scheudle device reset (unload)
3617  * This is due to some boards consuming sufficient power when driver is
3618  * up to overheat if fan fails.
3619  */
3624 
3625 }
3626 
3627 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3628 {
3629  int port = BP_PORT(bp);
3630  int reg_offset;
3631  u32 val;
3632 
3633  reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3635 
3636  if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3637 
3638  val = REG_RD(bp, reg_offset);
3639  val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3640  REG_WR(bp, reg_offset, val);
3641 
3642  BNX2X_ERR("SPIO5 hw attention\n");
3643 
3644  /* Fan failure attention */
3646  bnx2x_fan_failure(bp);
3647  }
3648 
3649  if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3653  }
3654 
3655  if (attn & HW_INTERRUT_ASSERT_SET_0) {
3656 
3657  val = REG_RD(bp, reg_offset);
3658  val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3659  REG_WR(bp, reg_offset, val);
3660 
3661  BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3662  (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3663  bnx2x_panic();
3664  }
3665 }
3666 
3667 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3668 {
3669  u32 val;
3670 
3672 
3673  val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3674  BNX2X_ERR("DB hw attention 0x%x\n", val);
3675  /* DORQ discard attention */
3676  if (val & 0x2)
3677  BNX2X_ERR("FATAL error from DORQ\n");
3678  }
3679 
3680  if (attn & HW_INTERRUT_ASSERT_SET_1) {
3681 
3682  int port = BP_PORT(bp);
3683  int reg_offset;
3684 
3685  reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3687 
3688  val = REG_RD(bp, reg_offset);
3689  val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3690  REG_WR(bp, reg_offset, val);
3691 
3692  BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3693  (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3694  bnx2x_panic();
3695  }
3696 }
3697 
3698 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3699 {
3700  u32 val;
3701 
3703 
3704  val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3705  BNX2X_ERR("CFC hw attention 0x%x\n", val);
3706  /* CFC error attention */
3707  if (val & 0x2)
3708  BNX2X_ERR("FATAL error from CFC\n");
3709  }
3710 
3712  val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3713  BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3714  /* RQ_USDMDP_FIFO_OVERFLOW */
3715  if (val & 0x18000)
3716  BNX2X_ERR("FATAL error from PXP\n");
3717 
3718  if (!CHIP_IS_E1x(bp)) {
3719  val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3720  BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3721  }
3722  }
3723 
3724  if (attn & HW_INTERRUT_ASSERT_SET_2) {
3725 
3726  int port = BP_PORT(bp);
3727  int reg_offset;
3728 
3729  reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3731 
3732  val = REG_RD(bp, reg_offset);
3733  val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3734  REG_WR(bp, reg_offset, val);
3735 
3736  BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3737  (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3738  bnx2x_panic();
3739  }
3740 }
3741 
3742 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3743 {
3744  u32 val;
3745 
3746  if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3747 
3748  if (attn & BNX2X_PMF_LINK_ASSERT) {
3749  int func = BP_FUNC(bp);
3750 
3751  REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3752  bnx2x_read_mf_cfg(bp);
3753  bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3754  func_mf_config[BP_ABS_FUNC(bp)].config);
3755  val = SHMEM_RD(bp,
3756  func_mb[BP_FW_MB_IDX(bp)].drv_status);
3757  if (val & DRV_STATUS_DCC_EVENT_MASK)
3758  bnx2x_dcc_event(bp,
3759  (val & DRV_STATUS_DCC_EVENT_MASK));
3760 
3761  if (val & DRV_STATUS_SET_MF_BW)
3762  bnx2x_set_mf_bw(bp);
3763 
3764  if (val & DRV_STATUS_DRV_INFO_REQ)
3765  bnx2x_handle_drv_info_req(bp);
3766  if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3767  bnx2x_pmf_update(bp);
3768 
3769  if (bp->port.pmf &&
3771  bp->dcbx_enabled > 0)
3772  /* start dcbx state machine */
3775  if (val & DRV_STATUS_AFEX_EVENT_MASK)
3776  bnx2x_handle_afex_cmd(bp,
3777  val & DRV_STATUS_AFEX_EVENT_MASK);
3779  bnx2x_handle_eee_event(bp);
3780  if (bp->link_vars.periodic_flags &
3782  /* sync with link */
3784  bp->link_vars.periodic_flags &=
3787  if (IS_MF(bp))
3788  bnx2x_link_sync_notify(bp);
3789  bnx2x_link_report(bp);
3790  }
3791  /* Always call it here: bnx2x_link_report() will
3792  * prevent the link indication duplication.
3793  */
3795  } else if (attn & BNX2X_MC_ASSERT_BITS) {
3796 
3797  BNX2X_ERR("MC assert!\n");
3798  bnx2x_mc_assert(bp);
3803  bnx2x_panic();
3804 
3805  } else if (attn & BNX2X_MCP_ASSERT) {
3806 
3807  BNX2X_ERR("MCP assert!\n");
3809  bnx2x_fw_dump(bp);
3810 
3811  } else
3812  BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3813  }
3814 
3815  if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3816  BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3817  if (attn & BNX2X_GRC_TIMEOUT) {
3818  val = CHIP_IS_E1(bp) ? 0 :
3820  BNX2X_ERR("GRC time-out 0x%08x\n", val);
3821  }
3822  if (attn & BNX2X_GRC_RSV) {
3823  val = CHIP_IS_E1(bp) ? 0 :
3825  BNX2X_ERR("GRC reserved 0x%08x\n", val);
3826  }
3828  }
3829 }
3830 
3831 /*
3832  * Bits map:
3833  * 0-7 - Engine0 load counter.
3834  * 8-15 - Engine1 load counter.
3835  * 16 - Engine0 RESET_IN_PROGRESS bit.
3836  * 17 - Engine1 RESET_IN_PROGRESS bit.
3837  * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3838  * on the engine
3839  * 19 - Engine1 ONE_IS_LOADED.
3840  * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3841  * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3842  * just the one belonging to its engine).
3843  *
3844  */
3845 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3846 
3847 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3848 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3849 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3850 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3851 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3852 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3853 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3854 
3855 /*
3856  * Set the GLOBAL_RESET bit.
3857  *
3858  * Should be run under rtnl lock
3859  */
3861 {
3862  u32 val;
3864  val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3867 }
3868 
3869 /*
3870  * Clear the GLOBAL_RESET bit.
3871  *
3872  * Should be run under rtnl lock
3873  */
3874 static void bnx2x_clear_reset_global(struct bnx2x *bp)
3875 {
3876  u32 val;
3878  val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3881 }
3882 
3883 /*
3884  * Checks the GLOBAL_RESET bit.
3885  *
3886  * should be run under rtnl lock
3887  */
3888 static bool bnx2x_reset_is_global(struct bnx2x *bp)
3889 {
3890  u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3891 
3892  DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3893  return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3894 }
3895 
3896 /*
3897  * Clear RESET_IN_PROGRESS bit for the current engine.
3898  *
3899  * Should be run under rtnl lock
3900  */
3901 static void bnx2x_set_reset_done(struct bnx2x *bp)
3902 {
3903  u32 val;
3904  u32 bit = BP_PATH(bp) ?
3907  val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3908 
3909  /* Clear the bit */
3910  val &= ~bit;
3911  REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3912 
3914 }
3915 
3916 /*
3917  * Set RESET_IN_PROGRESS for the current engine.
3918  *
3919  * should be run under rtnl lock
3920  */
3922 {
3923  u32 val;
3924  u32 bit = BP_PATH(bp) ?
3927  val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3928 
3929  /* Set the bit */
3930  val |= bit;
3931  REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3933 }
3934 
3935 /*
3936  * Checks the RESET_IN_PROGRESS bit for the given engine.
3937  * should be run under rtnl lock
3938  */
3939 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3940 {
3941  u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3942  u32 bit = engine ?
3944 
3945  /* return false if bit is set */
3946  return (val & bit) ? false : true;
3947 }
3948 
3949 /*
3950  * set pf load for the current pf.
3951  *
3952  * should be run under rtnl lock
3953  */
3954 void bnx2x_set_pf_load(struct bnx2x *bp)
3955 {
3956  u32 val1, val;
3959  u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3961 
3963  val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3964 
3965  DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
3966 
3967  /* get the current counter value */
3968  val1 = (val & mask) >> shift;
3969 
3970  /* set bit of that PF */
3971  val1 |= (1 << bp->pf_num);
3972 
3973  /* clear the old value */
3974  val &= ~mask;
3975 
3976  /* set the new one */
3977  val |= ((val1 << shift) & mask);
3978 
3979  REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3981 }
3982 
3992 bool bnx2x_clear_pf_load(struct bnx2x *bp)
3993 {
3994  u32 val1, val;
3997  u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3999 
4001  val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4002  DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4003 
4004  /* get the current counter value */
4005  val1 = (val & mask) >> shift;
4006 
4007  /* clear bit of that PF */
4008  val1 &= ~(1 << bp->pf_num);
4009 
4010  /* clear the old value */
4011  val &= ~mask;
4012 
4013  /* set the new one */
4014  val |= ((val1 << shift) & mask);
4015 
4016  REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4018  return val1 != 0;
4019 }
4020 
4021 /*
4022  * Read the load status for the current engine.
4023  *
4024  * should be run under rtnl lock
4025  */
4026 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4027 {
4028  u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4030  u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4032  u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4033 
4034  DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4035 
4036  val = (val & mask) >> shift;
4037 
4038  DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4039  engine, val);
4040 
4041  return val != 0;
4042 }
4043 
4044 static void _print_next_block(int idx, const char *blk)
4045 {
4046  pr_cont("%s%s", idx ? ", " : "", blk);
4047 }
4048 
4049 static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4050  bool print)
4051 {
4052  int i = 0;
4053  u32 cur_bit = 0;
4054  for (i = 0; sig; i++) {
4055  cur_bit = ((u32)0x1 << i);
4056  if (sig & cur_bit) {
4057  switch (cur_bit) {
4059  if (print)
4060  _print_next_block(par_num++, "BRB");
4061  break;
4063  if (print)
4064  _print_next_block(par_num++, "PARSER");
4065  break;
4067  if (print)
4068  _print_next_block(par_num++, "TSDM");
4069  break;
4071  if (print)
4072  _print_next_block(par_num++,
4073  "SEARCHER");
4074  break;
4076  if (print)
4077  _print_next_block(par_num++, "TCM");
4078  break;
4080  if (print)
4081  _print_next_block(par_num++, "TSEMI");
4082  break;
4084  if (print)
4085  _print_next_block(par_num++, "XPB");
4086  break;
4087  }
4088 
4089  /* Clear the bit */
4090  sig &= ~cur_bit;
4091  }
4092  }
4093 
4094  return par_num;
4095 }
4096 
4097 static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4098  bool *global, bool print)
4099 {
4100  int i = 0;
4101  u32 cur_bit = 0;
4102  for (i = 0; sig; i++) {
4103  cur_bit = ((u32)0x1 << i);
4104  if (sig & cur_bit) {
4105  switch (cur_bit) {
4107  if (print)
4108  _print_next_block(par_num++, "PBF");
4109  break;
4111  if (print)
4112  _print_next_block(par_num++, "QM");
4113  break;
4115  if (print)
4116  _print_next_block(par_num++, "TM");
4117  break;
4119  if (print)
4120  _print_next_block(par_num++, "XSDM");
4121  break;
4123  if (print)
4124  _print_next_block(par_num++, "XCM");
4125  break;
4127  if (print)
4128  _print_next_block(par_num++, "XSEMI");
4129  break;
4131  if (print)
4132  _print_next_block(par_num++,
4133  "DOORBELLQ");
4134  break;
4136  if (print)
4137  _print_next_block(par_num++, "NIG");
4138  break;
4140  if (print)
4141  _print_next_block(par_num++,
4142  "VAUX PCI CORE");
4143  *global = true;
4144  break;
4146  if (print)
4147  _print_next_block(par_num++, "DEBUG");
4148  break;
4150  if (print)
4151  _print_next_block(par_num++, "USDM");
4152  break;
4154  if (print)
4155  _print_next_block(par_num++, "UCM");
4156  break;
4158  if (print)
4159  _print_next_block(par_num++, "USEMI");
4160  break;
4162  if (print)
4163  _print_next_block(par_num++, "UPB");
4164  break;
4166  if (print)
4167  _print_next_block(par_num++, "CSDM");
4168  break;
4170  if (print)
4171  _print_next_block(par_num++, "CCM");
4172  break;
4173  }
4174 
4175  /* Clear the bit */
4176  sig &= ~cur_bit;
4177  }
4178  }
4179 
4180  return par_num;
4181 }
4182 
4183 static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4184  bool print)
4185 {
4186  int i = 0;
4187  u32 cur_bit = 0;
4188  for (i = 0; sig; i++) {
4189  cur_bit = ((u32)0x1 << i);
4190  if (sig & cur_bit) {
4191  switch (cur_bit) {
4193  if (print)
4194  _print_next_block(par_num++, "CSEMI");
4195  break;
4197  if (print)
4198  _print_next_block(par_num++, "PXP");
4199  break;
4201  if (print)
4202  _print_next_block(par_num++,
4203  "PXPPCICLOCKCLIENT");
4204  break;
4206  if (print)
4207  _print_next_block(par_num++, "CFC");
4208  break;
4210  if (print)
4211  _print_next_block(par_num++, "CDU");
4212  break;
4214  if (print)
4215  _print_next_block(par_num++, "DMAE");
4216  break;
4218  if (print)
4219  _print_next_block(par_num++, "IGU");
4220  break;
4222  if (print)
4223  _print_next_block(par_num++, "MISC");
4224  break;
4225  }
4226 
4227  /* Clear the bit */
4228  sig &= ~cur_bit;
4229  }
4230  }
4231 
4232  return par_num;
4233 }
4234 
4235 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4236  bool *global, bool print)
4237 {
4238  int i = 0;
4239  u32 cur_bit = 0;
4240  for (i = 0; sig; i++) {
4241  cur_bit = ((u32)0x1 << i);
4242  if (sig & cur_bit) {
4243  switch (cur_bit) {
4245  if (print)
4246  _print_next_block(par_num++, "MCP ROM");
4247  *global = true;
4248  break;
4250  if (print)
4251  _print_next_block(par_num++,
4252  "MCP UMP RX");
4253  *global = true;
4254  break;
4256  if (print)
4257  _print_next_block(par_num++,
4258  "MCP UMP TX");
4259  *global = true;
4260  break;
4262  if (print)
4263  _print_next_block(par_num++,
4264  "MCP SCPAD");
4265  *global = true;
4266  break;
4267  }
4268 
4269  /* Clear the bit */
4270  sig &= ~cur_bit;
4271  }
4272  }
4273 
4274  return par_num;
4275 }
4276 
4277 static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4278  bool print)
4279 {
4280  int i = 0;
4281  u32 cur_bit = 0;
4282  for (i = 0; sig; i++) {
4283  cur_bit = ((u32)0x1 << i);
4284  if (sig & cur_bit) {
4285  switch (cur_bit) {
4287  if (print)
4288  _print_next_block(par_num++, "PGLUE_B");
4289  break;
4291  if (print)
4292  _print_next_block(par_num++, "ATC");
4293  break;
4294  }
4295 
4296  /* Clear the bit */
4297  sig &= ~cur_bit;
4298  }
4299  }
4300 
4301  return par_num;
4302 }
4303 
4304 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4305  u32 *sig)
4306 {
4307  if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4308  (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4309  (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4310  (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4311  (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4312  int par_num = 0;
4313  DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4314  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4315  sig[0] & HW_PRTY_ASSERT_SET_0,
4316  sig[1] & HW_PRTY_ASSERT_SET_1,
4317  sig[2] & HW_PRTY_ASSERT_SET_2,
4318  sig[3] & HW_PRTY_ASSERT_SET_3,
4319  sig[4] & HW_PRTY_ASSERT_SET_4);
4320  if (print)
4321  netdev_err(bp->dev,
4322  "Parity errors detected in blocks: ");
4323  par_num = bnx2x_check_blocks_with_parity0(
4324  sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4325  par_num = bnx2x_check_blocks_with_parity1(
4326  sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4327  par_num = bnx2x_check_blocks_with_parity2(
4328  sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4329  par_num = bnx2x_check_blocks_with_parity3(
4330  sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4331  par_num = bnx2x_check_blocks_with_parity4(
4332  sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4333 
4334  if (print)
4335  pr_cont("\n");
4336 
4337  return true;
4338  } else
4339  return false;
4340 }
4341 
4349 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4350 {
4351  struct attn_route attn = { {0} };
4352  int port = BP_PORT(bp);
4353 
4354  attn.sig[0] = REG_RD(bp,
4356  port*4);
4357  attn.sig[1] = REG_RD(bp,
4359  port*4);
4360  attn.sig[2] = REG_RD(bp,
4362  port*4);
4363  attn.sig[3] = REG_RD(bp,
4365  port*4);
4366 
4367  if (!CHIP_IS_E1x(bp))
4368  attn.sig[4] = REG_RD(bp,
4370  port*4);
4371 
4372  return bnx2x_parity_attn(bp, global, print, attn.sig);
4373 }
4374 
4375 
4376 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4377 {
4378  u32 val;
4380 
4382  BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4384  BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4386  BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4388  BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4390  BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4391  if (val &
4393  BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4394  if (val &
4396  BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4398  BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4400  BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4402  BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4403  }
4405  val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4406  BNX2X_ERR("ATC hw attention 0x%x\n", val);
4408  BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4410  BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4412  BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4414  BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4416  BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4418  BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4419  }
4420 
4423  BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4426  }
4427 
4428 }
4429 
4430 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4431 {
4432  struct attn_route attn, *group_mask;
4433  int port = BP_PORT(bp);
4434  int index;
4435  u32 reg_addr;
4436  u32 val;
4437  u32 aeu_mask;
4438  bool global = false;
4439 
4440  /* need to take HW lock because MCP or other port might also
4441  try to handle this event */
4442  bnx2x_acquire_alr(bp);
4443 
4444  if (bnx2x_chk_parity_attn(bp, &global, true)) {
4445 #ifndef BNX2X_STOP_ON_ERROR
4448  /* Disable HW interrupts */
4449  bnx2x_int_disable(bp);
4450  /* In case of parity errors don't handle attentions so that
4451  * other function would "see" parity errors.
4452  */
4453 #else
4454  bnx2x_panic();
4455 #endif
4456  bnx2x_release_alr(bp);
4457  return;
4458  }
4459 
4460  attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4461  attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4462  attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4463  attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4464  if (!CHIP_IS_E1x(bp))
4465  attn.sig[4] =
4467  else
4468  attn.sig[4] = 0;
4469 
4470  DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4471  attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4472 
4473  for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4474  if (deasserted & (1 << index)) {
4475  group_mask = &bp->attn_group[index];
4476 
4477  DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4478  index,
4479  group_mask->sig[0], group_mask->sig[1],
4480  group_mask->sig[2], group_mask->sig[3],
4481  group_mask->sig[4]);
4482 
4483  bnx2x_attn_int_deasserted4(bp,
4484  attn.sig[4] & group_mask->sig[4]);
4485  bnx2x_attn_int_deasserted3(bp,
4486  attn.sig[3] & group_mask->sig[3]);
4487  bnx2x_attn_int_deasserted1(bp,
4488  attn.sig[1] & group_mask->sig[1]);
4489  bnx2x_attn_int_deasserted2(bp,
4490  attn.sig[2] & group_mask->sig[2]);
4491  bnx2x_attn_int_deasserted0(bp,
4492  attn.sig[0] & group_mask->sig[0]);
4493  }
4494  }
4495 
4496  bnx2x_release_alr(bp);
4497 
4498  if (bp->common.int_block == INT_BLOCK_HC)
4499  reg_addr = (HC_REG_COMMAND_REG + port*32 +
4501  else
4502  reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4503 
4504  val = ~deasserted;
4505  DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4506  (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4507  REG_WR(bp, reg_addr, val);
4508 
4509  if (~bp->attn_state & deasserted)
4510  BNX2X_ERR("IGU ERROR\n");
4511 
4512  reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4514 
4516  aeu_mask = REG_RD(bp, reg_addr);
4517 
4518  DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4519  aeu_mask, deasserted);
4520  aeu_mask |= (deasserted & 0x3ff);
4521  DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4522 
4523  REG_WR(bp, reg_addr, aeu_mask);
4525 
4526  DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4527  bp->attn_state &= ~deasserted;
4528  DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4529 }
4530 
4531 static void bnx2x_attn_int(struct bnx2x *bp)
4532 {
4533  /* read local copy of bits */
4534  u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4535  attn_bits);
4536  u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4537  attn_bits_ack);
4538  u32 attn_state = bp->attn_state;
4539 
4540  /* look for changed bits */
4541  u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4542  u32 deasserted = ~attn_bits & attn_ack & attn_state;
4543 
4544  DP(NETIF_MSG_HW,
4545  "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4546  attn_bits, attn_ack, asserted, deasserted);
4547 
4548  if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4549  BNX2X_ERR("BAD attention state\n");
4550 
4551  /* handle bits that were raised */
4552  if (asserted)
4553  bnx2x_attn_int_asserted(bp, asserted);
4554 
4555  if (deasserted)
4556  bnx2x_attn_int_deasserted(bp, deasserted);
4557 }
4558 
4559 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4560  u16 index, u8 op, u8 update)
4561 {
4562  u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4563 
4564  bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4565  igu_addr);
4566 }
4567 
4568 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4569 {
4570  /* No memory barriers */
4571  storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4572  mmiowb(); /* keep prod updates ordered */
4573 }
4574 
4575 #ifdef BCM_CNIC
4576 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4577  union event_ring_elem *elem)
4578 {
4579  u8 err = elem->message.error;
4580 
4581  if (!bp->cnic_eth_dev.starting_cid ||
4582  (cid < bp->cnic_eth_dev.starting_cid &&
4583  cid != bp->cnic_eth_dev.iscsi_l2_cid))
4584  return 1;
4585 
4586  DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4587 
4588  if (unlikely(err)) {
4589 
4590  BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4591  cid);
4592  bnx2x_panic_dump(bp);
4593  }
4594  bnx2x_cnic_cfc_comp(bp, cid, err);
4595  return 0;
4596 }
4597 #endif
4598 
4599 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4600 {
4601  struct bnx2x_mcast_ramrod_params rparam;
4602  int rc;
4603 
4604  memset(&rparam, 0, sizeof(rparam));
4605 
4606  rparam.mcast_obj = &bp->mcast_obj;
4607 
4608  netif_addr_lock_bh(bp->dev);
4609 
4610  /* Clear pending state for the last command */
4611  bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4612 
4613  /* If there are pending mcast commands - send them */
4614  if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4615  rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4616  if (rc < 0)
4617  BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4618  rc);
4619  }
4620 
4621  netif_addr_unlock_bh(bp->dev);
4622 }
4623 
4624 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4625  union event_ring_elem *elem)
4626 {
4627  unsigned long ramrod_flags = 0;
4628  int rc = 0;
4629  u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4630  struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4631 
4632  /* Always push next commands out, don't wait here */
4633  __set_bit(RAMROD_CONT, &ramrod_flags);
4634 
4635  switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4637  DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4638 #ifdef BCM_CNIC
4639  if (cid == BNX2X_ISCSI_ETH_CID(bp))
4640  vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4641  else
4642 #endif
4643  vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4644 
4645  break;
4647  DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4648  /* This is only relevant for 57710 where multicast MACs are
4649  * configured as unicast MACs using the same ramrod.
4650  */
4651  bnx2x_handle_mcast_eqe(bp);
4652  return;
4653  default:
4654  BNX2X_ERR("Unsupported classification command: %d\n",
4655  elem->message.data.eth_event.echo);
4656  return;
4657  }
4658 
4659  rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4660 
4661  if (rc < 0)
4662  BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4663  else if (rc > 0)
4664  DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4665 
4666 }
4667 
4668 #ifdef BCM_CNIC
4669 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4670 #endif
4671 
4672 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4673 {
4674  netif_addr_lock_bh(bp->dev);
4675 
4677 
4678  /* Send rx_mode command again if was requested */
4681 #ifdef BCM_CNIC
4683  &bp->sp_state))
4684  bnx2x_set_iscsi_eth_rx_mode(bp, true);
4686  &bp->sp_state))
4687  bnx2x_set_iscsi_eth_rx_mode(bp, false);
4688 #endif
4689 
4690  netif_addr_unlock_bh(bp->dev);
4691 }
4692 
4693 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
4694  union event_ring_elem *elem)
4695 {
4696  if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4697  DP(BNX2X_MSG_SP,
4698  "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4699  elem->message.data.vif_list_event.func_bit_map);
4701  elem->message.data.vif_list_event.func_bit_map);
4702  } else if (elem->message.data.vif_list_event.echo ==
4704  DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4706  }
4707 }
4708 
4709 /* called with rtnl_lock */
4710 static void bnx2x_after_function_update(struct bnx2x *bp)
4711 {
4712  int q, rc;
4713  struct bnx2x_fastpath *fp;
4714  struct bnx2x_queue_state_params queue_params = {NULL};
4715  struct bnx2x_queue_update_params *q_update_params =
4716  &queue_params.params.update;
4717 
4718  /* Send Q update command with afex vlan removal values for all Qs */
4719  queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4720 
4721  /* set silent vlan removal values according to vlan mode */
4723  &q_update_params->update_flags);
4725  &q_update_params->update_flags);
4726  __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4727 
4728  /* in access mode mark mask and value are 0 to strip all vlans */
4730  q_update_params->silent_removal_value = 0;
4731  q_update_params->silent_removal_mask = 0;
4732  } else {
4733  q_update_params->silent_removal_value =
4735  q_update_params->silent_removal_mask = VLAN_VID_MASK;
4736  }
4737 
4738  for_each_eth_queue(bp, q) {
4739  /* Set the appropriate Queue object */
4740  fp = &bp->fp[q];
4741  queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4742 
4743  /* send the ramrod */
4744  rc = bnx2x_queue_state_change(bp, &queue_params);
4745  if (rc < 0)
4746  BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4747  q);
4748  }
4749 
4750 #ifdef BCM_CNIC
4751  if (!NO_FCOE(bp)) {
4752  fp = &bp->fp[FCOE_IDX(bp)];
4753  queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4754 
4755  /* clear pending completion bit */
4756  __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4757 
4758  /* mark latest Q bit */
4762 
4763  /* send Q update ramrod for FCoE Q */
4764  rc = bnx2x_queue_state_change(bp, &queue_params);
4765  if (rc < 0)
4766  BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4767  q);
4768  } else {
4769  /* If no FCoE ring - ACK MCP now */
4770  bnx2x_link_report(bp);
4772  }
4773 #else
4774  /* If no FCoE ring - ACK MCP now */
4775  bnx2x_link_report(bp);
4777 #endif /* BCM_CNIC */
4778 }
4779 
4780 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4781  struct bnx2x *bp, u32 cid)
4782 {
4783  DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4784 #ifdef BCM_CNIC
4785  if (cid == BNX2X_FCOE_ETH_CID(bp))
4786  return &bnx2x_fcoe_sp_obj(bp, q_obj);
4787  else
4788 #endif
4789  return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
4790 }
4791 
4792 static void bnx2x_eq_int(struct bnx2x *bp)
4793 {
4794  u16 hw_cons, sw_cons, sw_prod;
4795  union event_ring_elem *elem;
4796  u32 cid;
4797  u8 opcode;
4798  int spqe_cnt = 0;
4799  struct bnx2x_queue_sp_obj *q_obj;
4800  struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4801  struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4802 
4803  hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4804 
4805  /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4806  * when we get the the next-page we nned to adjust so the loop
4807  * condition below will be met. The next element is the size of a
4808  * regular element and hence incrementing by 1
4809  */
4810  if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4811  hw_cons++;
4812 
4813  /* This function may never run in parallel with itself for a
4814  * specific bp, thus there is no need in "paired" read memory
4815  * barrier here.
4816  */
4817  sw_cons = bp->eq_cons;
4818  sw_prod = bp->eq_prod;
4819 
4820  DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4821  hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4822 
4823  for (; sw_cons != hw_cons;
4824  sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4825 
4826 
4827  elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4828 
4829  cid = SW_CID(elem->message.data.cfc_del_event.cid);
4830  opcode = elem->message.opcode;
4831 
4832 
4833  /* handle eq element */
4834  switch (opcode) {
4837  "got statistics comp event %d\n",
4838  bp->stats_comp++);
4839  /* nothing to do with stats comp */
4840  goto next_spqe;
4841 
4843  /* handle according to cid range */
4844  /*
4845  * we may want to verify here that the bp state is
4846  * HALTING
4847  */
4848  DP(BNX2X_MSG_SP,
4849  "got delete ramrod for MULTI[%d]\n", cid);
4850 #ifdef BCM_CNIC
4851  if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4852  goto next_spqe;
4853 #endif
4854  q_obj = bnx2x_cid_to_q_obj(bp, cid);
4855 
4856  if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4857  break;
4858 
4859 
4860 
4861  goto next_spqe;
4862 
4864  DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
4865  if (f_obj->complete_cmd(bp, f_obj,
4867  break;
4869  goto next_spqe;
4870 
4872  DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
4873  if (f_obj->complete_cmd(bp, f_obj,
4875  break;
4877  goto next_spqe;
4880  "AFEX: ramrod completed FUNCTION_UPDATE\n");
4881  f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_AFEX_UPDATE);
4882 
4883  /* We will perform the Queues update from sp_rtnl task
4884  * as all Queue SP operations should run under
4885  * rtnl_lock.
4886  */
4889  &bp->sp_rtnl_state);
4891 
4893  goto next_spqe;
4894 
4896  f_obj->complete_cmd(bp, f_obj,
4898  bnx2x_after_afex_vif_lists(bp, elem);
4899  goto next_spqe;
4902  "got FUNC_START ramrod\n");
4903  if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4904  break;
4905 
4906  goto next_spqe;
4907 
4910  "got FUNC_STOP ramrod\n");
4911  if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4912  break;
4913 
4914  goto next_spqe;
4915  }
4916 
4917  switch (opcode | bp->state) {
4922  cid = elem->message.data.eth_event.echo &
4924  DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
4925  cid);
4926  rss_raw->clear_pending(rss_raw);
4927  break;
4928 
4939  DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
4940  bnx2x_handle_classification_eqe(bp, elem);
4941  break;
4942 
4949  DP(BNX2X_MSG_SP, "got mcast ramrod\n");
4950  bnx2x_handle_mcast_eqe(bp);
4951  break;
4952 
4959  DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
4960  bnx2x_handle_rx_mode_eqe(bp);
4961  break;
4962  default:
4963  /* unknown event log error and continue */
4964  BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4965  elem->message.opcode, bp->state);
4966  }
4967 next_spqe:
4968  spqe_cnt++;
4969  } /* for */
4970 
4972  atomic_add(spqe_cnt, &bp->eq_spq_left);
4973 
4974  bp->eq_cons = sw_cons;
4975  bp->eq_prod = sw_prod;
4976  /* Make sure that above mem writes were issued towards the memory */
4977  smp_wmb();
4978 
4979  /* update producer */
4980  bnx2x_update_eq_prod(bp, bp->eq_prod);
4981 }
4982 
4983 static void bnx2x_sp_task(struct work_struct *work)
4984 {
4985  struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
4986  u16 status;
4987 
4988  status = bnx2x_update_dsb_idx(bp);
4989 /* if (status == 0) */
4990 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4991 
4992  DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status);
4993 
4994  /* HW attentions */
4995  if (status & BNX2X_DEF_SB_ATT_IDX) {
4996  bnx2x_attn_int(bp);
4997  status &= ~BNX2X_DEF_SB_ATT_IDX;
4998  }
4999 
5000  /* SP events: STAT_QUERY and others */
5001  if (status & BNX2X_DEF_SB_IDX) {
5002 #ifdef BCM_CNIC
5003  struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5004 
5005  if ((!NO_FCOE(bp)) &&
5006  (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5007  /*
5008  * Prevent local bottom-halves from running as
5009  * we are going to change the local NAPI list.
5010  */
5011  local_bh_disable();
5012  napi_schedule(&bnx2x_fcoe(bp, napi));
5013  local_bh_enable();
5014  }
5015 #endif
5016  /* Handle EQ completions */
5017  bnx2x_eq_int(bp);
5018 
5019  bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5020  le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5021 
5022  status &= ~BNX2X_DEF_SB_IDX;
5023  }
5024 
5025  if (unlikely(status))
5026  DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n",
5027  status);
5028 
5029  bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5031 
5032  /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5034  &bp->sp_state)) {
5035  bnx2x_link_report(bp);
5037  }
5038 }
5039 
5040 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5041 {
5042  struct net_device *dev = dev_instance;
5043  struct bnx2x *bp = netdev_priv(dev);
5044 
5045  bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5046  IGU_INT_DISABLE, 0);
5047 
5048 #ifdef BNX2X_STOP_ON_ERROR
5049  if (unlikely(bp->panic))
5050  return IRQ_HANDLED;
5051 #endif
5052 
5053 #ifdef BCM_CNIC
5054  {
5055  struct cnic_ops *c_ops;
5056 
5057  rcu_read_lock();
5058  c_ops = rcu_dereference(bp->cnic_ops);
5059  if (c_ops)
5060  c_ops->cnic_handler(bp->cnic_data, NULL);
5061  rcu_read_unlock();
5062  }
5063 #endif
5064  queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
5065 
5066  return IRQ_HANDLED;
5067 }
5068 
5069 /* end of slow path */
5070 
5071 
5072 void bnx2x_drv_pulse(struct bnx2x *bp)
5073 {
5074  SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5075  bp->fw_drv_pulse_wr_seq);
5076 }
5077 
5078 
5079 static void bnx2x_timer(unsigned long data)
5080 {
5081  struct bnx2x *bp = (struct bnx2x *) data;
5082 
5083  if (!netif_running(bp->dev))
5084  return;
5085 
5086  if (!BP_NOMCP(bp)) {
5087  int mb_idx = BP_FW_MB_IDX(bp);
5088  u32 drv_pulse;
5089  u32 mcp_pulse;
5090 
5091  ++bp->fw_drv_pulse_wr_seq;
5093  /* TBD - add SYSTEM_TIME */
5094  drv_pulse = bp->fw_drv_pulse_wr_seq;
5095  bnx2x_drv_pulse(bp);
5096 
5097  mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5099  /* The delta between driver pulse and mcp response
5100  * should be 1 (before mcp response) or 0 (after mcp response)
5101  */
5102  if ((drv_pulse != mcp_pulse) &&
5103  (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5104  /* someone lost a heartbeat... */
5105  BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5106  drv_pulse, mcp_pulse);
5107  }
5108  }
5109 
5110  if (bp->state == BNX2X_STATE_OPEN)
5112 
5113  mod_timer(&bp->timer, jiffies + bp->current_interval);
5114 }
5115 
5116 /* end of Statistics */
5117 
5118 /* nic init */
5119 
5120 /*
5121  * nic init service functions
5122  */
5123 
5124 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5125 {
5126  u32 i;
5127  if (!(len%4) && !(addr%4))
5128  for (i = 0; i < len; i += 4)
5129  REG_WR(bp, addr + i, fill);
5130  else
5131  for (i = 0; i < len; i++)
5132  REG_WR8(bp, addr + i, fill);
5133 
5134 }
5135 
5136 /* helper: writes FP SP data to FW - data_size in dwords */
5137 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5138  int fw_sb_id,
5139  u32 *sb_data_p,
5140  u32 data_size)
5141 {
5142  int index;
5143  for (index = 0; index < data_size; index++)
5146  sizeof(u32)*index,
5147  *(sb_data_p + index));
5148 }
5149 
5150 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5151 {
5152  u32 *sb_data_p;
5153  u32 data_size = 0;
5154  struct hc_status_block_data_e2 sb_data_e2;
5155  struct hc_status_block_data_e1x sb_data_e1x;
5156 
5157  /* disable the function first */
5158  if (!CHIP_IS_E1x(bp)) {
5159  memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5160  sb_data_e2.common.state = SB_DISABLED;
5161  sb_data_e2.common.p_func.vf_valid = false;
5162  sb_data_p = (u32 *)&sb_data_e2;
5163  data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5164  } else {
5165  memset(&sb_data_e1x, 0,
5166  sizeof(struct hc_status_block_data_e1x));
5167  sb_data_e1x.common.state = SB_DISABLED;
5168  sb_data_e1x.common.p_func.vf_valid = false;
5169  sb_data_p = (u32 *)&sb_data_e1x;
5170  data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5171  }
5172  bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5173 
5174  bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5175  CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5177  bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5178  CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5180 }
5181 
5182 /* helper: writes SP SB data to FW */
5183 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5184  struct hc_sp_status_block_data *sp_sb_data)
5185 {
5186  int func = BP_FUNC(bp);
5187  int i;
5188  for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5191  i*sizeof(u32),
5192  *((u32 *)sp_sb_data + i));
5193 }
5194 
5195 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5196 {
5197  int func = BP_FUNC(bp);
5198  struct hc_sp_status_block_data sp_sb_data;
5199  memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5200 
5201  sp_sb_data.state = SB_DISABLED;
5202  sp_sb_data.p_func.vf_valid = false;
5203 
5204  bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5205 
5206  bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5209  bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5210  CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5212 
5213 }
5214 
5215 
5216 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5217  int igu_sb_id, int igu_seg_id)
5218 {
5219  hc_sm->igu_sb_id = igu_sb_id;
5220  hc_sm->igu_seg_id = igu_seg_id;
5221  hc_sm->timer_value = 0xFF;
5222  hc_sm->time_to_expire = 0xFFFFFFFF;
5223 }
5224 
5225 
5226 /* allocates state machine ids. */
5227 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5228 {
5229  /* zero out state machine indices */
5230  /* rx indices */
5231  index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5232 
5233  /* tx indices */
5234  index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5235  index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5236  index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5237  index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5238 
5239  /* map indices */
5240  /* rx indices */
5241  index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5242  SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5243 
5244  /* tx indices */
5245  index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5246  SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5247  index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5248  SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5249  index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5250  SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5251  index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5252  SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5253 }
5254 
5255 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5256  u8 vf_valid, int fw_sb_id, int igu_sb_id)
5257 {
5258  int igu_seg_id;
5259 
5260  struct hc_status_block_data_e2 sb_data_e2;
5261  struct hc_status_block_data_e1x sb_data_e1x;
5262  struct hc_status_block_sm *hc_sm_p;
5263  int data_size;
5264  u32 *sb_data_p;
5265 
5266  if (CHIP_INT_MODE_IS_BC(bp))
5267  igu_seg_id = HC_SEG_ACCESS_NORM;
5268  else
5269  igu_seg_id = IGU_SEG_ACCESS_NORM;
5270 
5271  bnx2x_zero_fp_sb(bp, fw_sb_id);
5272 
5273  if (!CHIP_IS_E1x(bp)) {
5274  memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5275  sb_data_e2.common.state = SB_ENABLED;
5276  sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5277  sb_data_e2.common.p_func.vf_id = vfid;
5278  sb_data_e2.common.p_func.vf_valid = vf_valid;
5279  sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5280  sb_data_e2.common.same_igu_sb_1b = true;
5281  sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5282  sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5283  hc_sm_p = sb_data_e2.common.state_machine;
5284  sb_data_p = (u32 *)&sb_data_e2;
5285  data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5286  bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5287  } else {
5288  memset(&sb_data_e1x, 0,
5289  sizeof(struct hc_status_block_data_e1x));
5290  sb_data_e1x.common.state = SB_ENABLED;
5291  sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5292  sb_data_e1x.common.p_func.vf_id = 0xff;
5293  sb_data_e1x.common.p_func.vf_valid = false;
5294  sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5295  sb_data_e1x.common.same_igu_sb_1b = true;
5296  sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5297  sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5298  hc_sm_p = sb_data_e1x.common.state_machine;
5299  sb_data_p = (u32 *)&sb_data_e1x;
5300  data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5301  bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5302  }
5303 
5304  bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5305  igu_sb_id, igu_seg_id);
5306  bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5307  igu_sb_id, igu_seg_id);
5308 
5309  DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5310 
5311  /* write indecies to HW */
5312  bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5313 }
5314 
5315 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5316  u16 tx_usec, u16 rx_usec)
5317 {
5319  false, rx_usec);
5320  bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5322  tx_usec);
5323  bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5325  tx_usec);
5326  bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5328  tx_usec);
5329 }
5330 
5331 static void bnx2x_init_def_sb(struct bnx2x *bp)
5332 {
5333  struct host_sp_status_block *def_sb = bp->def_status_blk;
5334  dma_addr_t mapping = bp->def_status_blk_mapping;
5335  int igu_sp_sb_index;
5336  int igu_seg_id;
5337  int port = BP_PORT(bp);
5338  int func = BP_FUNC(bp);
5339  int reg_offset, reg_offset_en5;
5340  u64 section;
5341  int index;
5342  struct hc_sp_status_block_data sp_sb_data;
5343  memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5344 
5345  if (CHIP_INT_MODE_IS_BC(bp)) {
5346  igu_sp_sb_index = DEF_SB_IGU_ID;
5347  igu_seg_id = HC_SEG_ACCESS_DEF;
5348  } else {
5349  igu_sp_sb_index = bp->igu_dsb_id;
5350  igu_seg_id = IGU_SEG_ACCESS_DEF;
5351  }
5352 
5353  /* ATTN */
5354  section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5355  atten_status_block);
5356  def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5357 
5358  bp->attn_state = 0;
5359 
5360  reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5362  reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5364  for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5365  int sindex;
5366  /* take care of sig[0]..sig[4] */
5367  for (sindex = 0; sindex < 4; sindex++)
5368  bp->attn_group[index].sig[sindex] =
5369  REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5370 
5371  if (!CHIP_IS_E1x(bp))
5372  /*
5373  * enable5 is separate from the rest of the registers,
5374  * and therefore the address skip is 4
5375  * and not 16 between the different groups
5376  */
5377  bp->attn_group[index].sig[4] = REG_RD(bp,
5378  reg_offset_en5 + 0x4*index);
5379  else
5380  bp->attn_group[index].sig[4] = 0;
5381  }
5382 
5383  if (bp->common.int_block == INT_BLOCK_HC) {
5384  reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5386 
5387  REG_WR(bp, reg_offset, U64_LO(section));
5388  REG_WR(bp, reg_offset + 4, U64_HI(section));
5389  } else if (!CHIP_IS_E1x(bp)) {
5390  REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5391  REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5392  }
5393 
5394  section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5395  sp_sb);
5396 
5397  bnx2x_zero_sp_sb(bp);
5398 
5399  sp_sb_data.state = SB_ENABLED;
5400  sp_sb_data.host_sb_addr.lo = U64_LO(section);
5401  sp_sb_data.host_sb_addr.hi = U64_HI(section);
5402  sp_sb_data.igu_sb_id = igu_sp_sb_index;
5403  sp_sb_data.igu_seg_id = igu_seg_id;
5404  sp_sb_data.p_func.pf_id = func;
5405  sp_sb_data.p_func.vnic_id = BP_VN(bp);
5406  sp_sb_data.p_func.vf_id = 0xff;
5407 
5408  bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5409 
5410  bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5411 }
5412 
5414 {
5415  int i;
5416 
5417  for_each_eth_queue(bp, i)
5418  bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5419  bp->tx_ticks, bp->rx_ticks);
5420 }
5421 
5422 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5423 {
5424  spin_lock_init(&bp->spq_lock);
5426 
5427  bp->spq_prod_idx = 0;
5429  bp->spq_prod_bd = bp->spq;
5431 }
5432 
5433 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5434 {
5435  int i;
5436  for (i = 1; i <= NUM_EQ_PAGES; i++) {
5437  union event_ring_elem *elem =
5438  &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5439 
5440  elem->next_page.addr.hi =
5442  BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5443  elem->next_page.addr.lo =
5445  BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5446  }
5447  bp->eq_cons = 0;
5448  bp->eq_prod = NUM_EQ_DESC;
5449  bp->eq_cons_sb = BNX2X_EQ_INDEX;
5450  /* we want a warning message before it gets rought... */
5451  atomic_set(&bp->eq_spq_left,
5453 }
5454 
5455 
5456 /* called with netif_addr_lock_bh() */
5457 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5458  unsigned long rx_mode_flags,
5459  unsigned long rx_accept_flags,
5460  unsigned long tx_accept_flags,
5461  unsigned long ramrod_flags)
5462 {
5463  struct bnx2x_rx_mode_ramrod_params ramrod_param;
5464  int rc;
5465 
5466  memset(&ramrod_param, 0, sizeof(ramrod_param));
5467 
5468  /* Prepare ramrod parameters */
5469  ramrod_param.cid = 0;
5470  ramrod_param.cl_id = cl_id;
5471  ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5472  ramrod_param.func_id = BP_FUNC(bp);
5473 
5474  ramrod_param.pstate = &bp->sp_state;
5475  ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5476 
5477  ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5478  ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5479 
5481 
5482  ramrod_param.ramrod_flags = ramrod_flags;
5483  ramrod_param.rx_mode_flags = rx_mode_flags;
5484 
5485  ramrod_param.rx_accept_flags = rx_accept_flags;
5486  ramrod_param.tx_accept_flags = tx_accept_flags;
5487 
5488  rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5489  if (rc < 0) {
5490  BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5491  return;
5492  }
5493 }
5494 
5495 /* called with netif_addr_lock_bh() */
5497 {
5498  unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5499  unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5500 
5501 #ifdef BCM_CNIC
5502  if (!NO_FCOE(bp))
5503 
5504  /* Configure rx_mode of FCoE Queue */
5505  __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5506 #endif
5507 
5508  switch (bp->rx_mode) {
5509  case BNX2X_RX_MODE_NONE:
5510  /*
5511  * 'drop all' supersedes any accept flags that may have been
5512  * passed to the function.
5513  */
5514  break;
5515  case BNX2X_RX_MODE_NORMAL:
5516  __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5517  __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5518  __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5519 
5520  /* internal switching mode */
5524 
5525  break;
5527  __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5528  __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5529  __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5530 
5531  /* internal switching mode */
5535 
5536  break;
5537  case BNX2X_RX_MODE_PROMISC:
5538  /* According to deffinition of SI mode, iface in promisc mode
5539  * should receive matched and unmatched (in resolution of port)
5540  * unicast packets.
5541  */
5542  __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5543  __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5544  __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5545  __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5546 
5547  /* internal switching mode */
5550 
5551  if (IS_MF_SI(bp))
5553  else
5555 
5556  break;
5557  default:
5558  BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5559  return;
5560  }
5561 
5562  if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5563  __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5565  }
5566 
5567  __set_bit(RAMROD_RX, &ramrod_flags);
5568  __set_bit(RAMROD_TX, &ramrod_flags);
5569 
5570  bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5571  tx_accept_flags, ramrod_flags);
5572 }
5573 
5574 static void bnx2x_init_internal_common(struct bnx2x *bp)
5575 {
5576  int i;
5577 
5578  if (IS_MF_SI(bp))
5579  /*
5580  * In switch independent mode, the TSTORM needs to accept
5581  * packets that failed classification, since approximate match
5582  * mac addresses aren't written to NIG LLH
5583  */
5586  else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5589 
5590  /* Zero this manually as its initialization is
5591  currently missing in the initTool */
5592  for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5594  USTORM_AGG_DATA_OFFSET + i * 4, 0);
5595  if (!CHIP_IS_E1x(bp)) {
5597  CHIP_INT_MODE_IS_BC(bp) ?
5599  }
5600 }
5601 
5602 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5603 {
5604  switch (load_code) {
5607  bnx2x_init_internal_common(bp);
5608  /* no break */
5609 
5611  /* nothing to do */
5612  /* no break */
5613 
5615  /* internal memory per function is
5616  initialized inside bnx2x_pf_init */
5617  break;
5618 
5619  default:
5620  BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5621  break;
5622  }
5623 }
5624 
5625 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5626 {
5627  return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
5628 }
5629 
5630 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5631 {
5632  return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
5633 }
5634 
5635 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5636 {
5637  if (CHIP_IS_E1x(fp->bp))
5638  return BP_L_ID(fp->bp) + fp->index;
5639  else /* We want Client ID to be the same as IGU SB ID for 57712 */
5640  return bnx2x_fp_igu_sb_id(fp);
5641 }
5642 
5643 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5644 {
5645  struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5646  u8 cos;
5647  unsigned long q_type = 0;
5648  u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5649  fp->rx_queue = fp_idx;
5650  fp->cid = fp_idx;
5651  fp->cl_id = bnx2x_fp_cl_id(fp);
5652  fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5653  fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5654  /* qZone id equals to FW (per path) client id */
5655  fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5656 
5657  /* init shortcut */
5658  fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5659 
5660  /* Setup SB indicies */
5662 
5663  /* Configure Queue State object */
5664  __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5665  __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5666 
5668 
5669  /* init tx data */
5670  for_each_cos_in_tx_queue(fp, cos) {
5671  bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5672  CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5673  FP_COS_TO_TXQ(fp, cos, bp),
5674  BNX2X_TX_SB_INDEX_BASE + cos, fp);
5675  cids[cos] = fp->txdata_ptr[cos]->cid;
5676  }
5677 
5678  bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5679  fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5680  bnx2x_sp_mapping(bp, q_rdata), q_type);
5681 
5685  bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5686 
5687  DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
5688  fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5689  fp->igu_sb_id);
5690  bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5691  fp->fw_sb_id, fp->igu_sb_id);
5692 
5693  bnx2x_update_fpsb_idx(fp);
5694 }
5695 
5696 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5697 {
5698  int i;
5699 
5700  for (i = 1; i <= NUM_TX_RINGS; i++) {
5701  struct eth_tx_next_bd *tx_next_bd =
5702  &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5703 
5704  tx_next_bd->addr_hi =
5706  BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5707  tx_next_bd->addr_lo =
5709  BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5710  }
5711 
5712  SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5713  txdata->tx_db.data.zero_fill1 = 0;
5714  txdata->tx_db.data.prod = 0;
5715 
5716  txdata->tx_pkt_prod = 0;
5717  txdata->tx_pkt_cons = 0;
5718  txdata->tx_bd_prod = 0;
5719  txdata->tx_bd_cons = 0;
5720  txdata->tx_pkt = 0;
5721 }
5722 
5723 static void bnx2x_init_tx_rings(struct bnx2x *bp)
5724 {
5725  int i;
5726  u8 cos;
5727 
5728  for_each_tx_queue(bp, i)
5729  for_each_cos_in_tx_queue(&bp->fp[i], cos)
5730  bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
5731 }
5732 
5733 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5734 {
5735  int i;
5736 
5737  for_each_eth_queue(bp, i)
5738  bnx2x_init_eth_fp(bp, i);
5739 #ifdef BCM_CNIC
5740  if (!NO_FCOE(bp))
5741  bnx2x_init_fcoe_fp(bp);
5742 
5743  bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5744  BNX2X_VF_ID_INVALID, false,
5745  bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5746 
5747 #endif
5748 
5749  /* Initialize MOD_ABS interrupts */
5750  bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5751  bp->common.shmem_base, bp->common.shmem2_base,
5752  BP_PORT(bp));
5753  /* ensure status block indices were read */
5754  rmb();
5755 
5756  bnx2x_init_def_sb(bp);
5757  bnx2x_update_dsb_idx(bp);
5758  bnx2x_init_rx_rings(bp);
5759  bnx2x_init_tx_rings(bp);
5760  bnx2x_init_sp_ring(bp);
5761  bnx2x_init_eq_ring(bp);
5762  bnx2x_init_internal(bp, load_code);
5763  bnx2x_pf_init(bp);
5764  bnx2x_stats_init(bp);
5765 
5766  /* flush all before enabling interrupts */
5767  mb();
5768  mmiowb();
5769 
5770  bnx2x_int_enable(bp);
5771 
5772  /* Check for SPIO5 */
5773  bnx2x_attn_int_deasserted0(bp,
5775  AEU_INPUTS_ATTN_BITS_SPIO5);
5776 }
5777 
5778 /* end of nic init */
5779 
5780 /*
5781  * gzip service functions
5782  */
5783 
5784 static int bnx2x_gunzip_init(struct bnx2x *bp)
5785 {
5786  bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5787  &bp->gunzip_mapping, GFP_KERNEL);
5788  if (bp->gunzip_buf == NULL)
5789  goto gunzip_nomem1;
5790 
5791  bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5792  if (bp->strm == NULL)
5793  goto gunzip_nomem2;
5794 
5795  bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5796  if (bp->strm->workspace == NULL)
5797  goto gunzip_nomem3;
5798 
5799  return 0;
5800 
5801 gunzip_nomem3:
5802  kfree(bp->strm);
5803  bp->strm = NULL;
5804 
5805 gunzip_nomem2:
5806  dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5807  bp->gunzip_mapping);
5808  bp->gunzip_buf = NULL;
5809 
5810 gunzip_nomem1:
5811  BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
5812  return -ENOMEM;
5813 }
5814 
5815 static void bnx2x_gunzip_end(struct bnx2x *bp)
5816 {
5817  if (bp->strm) {
5818  vfree(bp->strm->workspace);
5819  kfree(bp->strm);
5820  bp->strm = NULL;
5821  }
5822 
5823  if (bp->gunzip_buf) {
5824  dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5825  bp->gunzip_mapping);
5826  bp->gunzip_buf = NULL;
5827  }
5828 }
5829 
5830 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5831 {
5832  int n, rc;
5833 
5834  /* check gzip header */
5835  if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5836  BNX2X_ERR("Bad gzip header\n");
5837  return -EINVAL;
5838  }
5839 
5840  n = 10;
5841 
5842 #define FNAME 0x8
5843 
5844  if (zbuf[3] & FNAME)
5845  while ((zbuf[n++] != 0) && (n < len));
5846 
5847  bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5848  bp->strm->avail_in = len - n;
5849  bp->strm->next_out = bp->gunzip_buf;
5850  bp->strm->avail_out = FW_BUF_SIZE;
5851 
5852  rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5853  if (rc != Z_OK)
5854  return rc;
5855 
5856  rc = zlib_inflate(bp->strm, Z_FINISH);
5857  if ((rc != Z_OK) && (rc != Z_STREAM_END))
5858  netdev_err(bp->dev, "Firmware decompression error: %s\n",
5859  bp->strm->msg);
5860 
5861  bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5862  if (bp->gunzip_outlen & 0x3)
5863  netdev_err(bp->dev,
5864  "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
5865  bp->gunzip_outlen);
5866  bp->gunzip_outlen >>= 2;
5867 
5868  zlib_inflateEnd(bp->strm);
5869 
5870  if (rc == Z_STREAM_END)
5871  return 0;
5872 
5873  return rc;
5874 }
5875 
5876 /* nic load/unload */
5877 
5878 /*
5879  * General service functions
5880  */
5881 
5882 /* send a NIG loopback debug packet */
5883 static void bnx2x_lb_pckt(struct bnx2x *bp)
5884 {
5885  u32 wb_write[3];
5886 
5887  /* Ethernet source and destination addresses */
5888  wb_write[0] = 0x55555555;
5889  wb_write[1] = 0x55555555;
5890  wb_write[2] = 0x20; /* SOP */
5891  REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5892 
5893  /* NON-IP protocol */
5894  wb_write[0] = 0x09000000;
5895  wb_write[1] = 0x55555555;
5896  wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5897  REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5898 }
5899 
5900 /* some of the internal memories
5901  * are not directly readable from the driver
5902  * to test them we send debug packets
5903  */
5904 static int bnx2x_int_mem_test(struct bnx2x *bp)
5905 {
5906  int factor;
5907  int count, i;
5908  u32 val = 0;
5909 
5910  if (CHIP_REV_IS_FPGA(bp))
5911  factor = 120;
5912  else if (CHIP_REV_IS_EMUL(bp))
5913  factor = 200;
5914  else
5915  factor = 1;
5916 
5917  /* Disable inputs of parser neighbor blocks */
5918  REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5919  REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5920  REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5921  REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5922 
5923  /* Write 0 to parser credits for CFC search request */
5925 
5926  /* send Ethernet packet */
5927  bnx2x_lb_pckt(bp);
5928 
5929  /* TODO do i reset NIG statistic? */
5930  /* Wait until NIG register shows 1 packet of size 0x10 */
5931  count = 1000 * factor;
5932  while (count) {
5933 
5935  val = *bnx2x_sp(bp, wb_data[0]);
5936  if (val == 0x10)
5937  break;
5938 
5939  msleep(10);
5940  count--;
5941  }
5942  if (val != 0x10) {
5943  BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5944  return -1;
5945  }
5946 
5947  /* Wait until PRS register shows 1 packet */
5948  count = 1000 * factor;
5949  while (count) {
5950  val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5951  if (val == 1)
5952  break;
5953 
5954  msleep(10);
5955  count--;
5956  }
5957  if (val != 0x1) {
5958  BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5959  return -2;
5960  }
5961 
5962  /* Reset and init BRB, PRS */
5964  msleep(50);
5966  msleep(50);
5967  bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5968  bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5969 
5970  DP(NETIF_MSG_HW, "part2\n");
5971 
5972  /* Disable inputs of parser neighbor blocks */
5973  REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5974  REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5975  REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5976  REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5977 
5978  /* Write 0 to parser credits for CFC search request */
5980 
5981  /* send 10 Ethernet packets */
5982  for (i = 0; i < 10; i++)
5983  bnx2x_lb_pckt(bp);
5984 
5985  /* Wait until NIG register shows 10 + 1
5986  packets of size 11*0x10 = 0xb0 */
5987  count = 1000 * factor;
5988  while (count) {
5989 
5991  val = *bnx2x_sp(bp, wb_data[0]);
5992  if (val == 0xb0)
5993  break;
5994 
5995  msleep(10);
5996  count--;
5997  }
5998  if (val != 0xb0) {
5999  BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6000  return -3;
6001  }
6002 
6003  /* Wait until PRS register shows 2 packets */
6004  val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6005  if (val != 2)
6006  BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6007 
6008  /* Write 1 to parser credits for CFC search request */
6010 
6011  /* Wait until PRS register shows 3 packets */
6012  msleep(10 * factor);
6013  /* Wait until NIG register shows 1 packet of size 0x10 */
6014  val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6015  if (val != 3)
6016  BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6017 
6018  /* clear NIG EOP FIFO */
6019  for (i = 0; i < 11; i++)
6022  if (val != 1) {
6023  BNX2X_ERR("clear of NIG failed\n");
6024  return -4;
6025  }
6026 
6027  /* Reset and init BRB, PRS, NIG */
6029  msleep(50);
6031  msleep(50);
6032  bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6033  bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6034 #ifndef BCM_CNIC
6035  /* set NIC mode */
6036  REG_WR(bp, PRS_REG_NIC_MODE, 1);
6037 #endif
6038 
6039  /* Enable inputs of parser neighbor blocks */
6040  REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6041  REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6042  REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6043  REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6044 
6045  DP(NETIF_MSG_HW, "done\n");
6046 
6047  return 0; /* OK */
6048 }
6049 
6050 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6051 {
6053  if (!CHIP_IS_E1x(bp))
6054  REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6055  else
6058  REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6059  /*
6060  * mask read length error interrupts in brb for parser
6061  * (parsing unit and 'checksum and crc' unit)
6062  * these errors are legal (PU reads fixed length and CAC can cause
6063  * read length error on truncated packets)
6064  */
6065  REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6066  REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6067  REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6070  REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6071 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6072 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6075  REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6076 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6077 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6081  REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6082 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6083 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6084 
6085  if (CHIP_REV_IS_FPGA(bp))
6086  REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
6087  else if (!CHIP_IS_E1x(bp))
6094  else
6095  REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
6098  REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6099 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6100 
6101  if (!CHIP_IS_E1x(bp))
6102  /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6103  REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6104 
6105  REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6107 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6108  REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6109 }
6110 
6111 static void bnx2x_reset_common(struct bnx2x *bp)
6112 {
6113  u32 val = 0x1400;
6114 
6115  /* reset_common */
6117  0xd3ffff7f);
6118 
6119  if (CHIP_IS_E3(bp)) {
6122  }
6123 
6125 }
6126 
6127 static void bnx2x_setup_dmae(struct bnx2x *bp)
6128 {
6129  bp->dmae_ready = 0;
6130  spin_lock_init(&bp->dmae_lock);
6131 }
6132 
6133 static void bnx2x_init_pxp(struct bnx2x *bp)
6134 {
6135  u16 devctl;
6136  int r_order, w_order;
6137 
6139  DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6140  w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6141  if (bp->mrrs == -1)
6142  r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6143  else {
6144  DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6145  r_order = bp->mrrs;
6146  }
6147 
6148  bnx2x_init_pxp_arb(bp, r_order, w_order);
6149 }
6150 
6151 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6152 {
6153  int is_required;
6154  u32 val;
6155  int port;
6156 
6157  if (BP_NOMCP(bp))
6158  return;
6159 
6160  is_required = 0;
6161  val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6163 
6165  is_required = 1;
6166 
6167  /*
6168  * The fan failure mechanism is usually related to the PHY type since
6169  * the power consumption of the board is affected by the PHY. Currently,
6170  * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6171  */
6172  else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6173  for (port = PORT_0; port < PORT_MAX; port++) {
6174  is_required |=
6176  bp,
6177  bp->common.shmem_base,
6178  bp->common.shmem2_base,
6179  port);
6180  }
6181 
6182  DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6183 
6184  if (is_required == 0)
6185  return;
6186 
6187  /* Fan failure is indicated by SPIO 5 */
6188  bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
6190 
6191  /* set to active low mode */
6192  val = REG_RD(bp, MISC_REG_SPIO_INT);
6193  val |= ((1 << MISC_REGISTERS_SPIO_5) <<
6195  REG_WR(bp, MISC_REG_SPIO_INT, val);
6196 
6197  /* enable interrupt to signal the IGU */
6198  val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6199  val |= (1 << MISC_REGISTERS_SPIO_5);
6200  REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6201 }
6202 
6203 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
6204 {
6205  u32 offset = 0;
6206 
6207  if (CHIP_IS_E1(bp))
6208  return;
6209  if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
6210  return;
6211 
6212  switch (BP_ABS_FUNC(bp)) {
6213  case 0:
6215  break;
6216  case 1:
6218  break;
6219  case 2:
6221  break;
6222  case 3:
6224  break;
6225  case 4:
6227  break;
6228  case 5:
6230  break;
6231  case 6:
6233  break;
6234  case 7:
6236  break;
6237  default:
6238  return;
6239  }
6240 
6241  REG_WR(bp, offset, pretend_func_num);
6242  REG_RD(bp, offset);
6243  DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
6244 }
6245 
6246 void bnx2x_pf_disable(struct bnx2x *bp)
6247 {
6248  u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6249  val &= ~IGU_PF_CONF_FUNC_EN;
6250 
6251  REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6254 }
6255 
6256 static void bnx2x__common_init_phy(struct bnx2x *bp)
6257 {
6258  u32 shmem_base[2], shmem2_base[2];
6259  shmem_base[0] = bp->common.shmem_base;
6260  shmem2_base[0] = bp->common.shmem2_base;
6261  if (!CHIP_IS_E1x(bp)) {
6262  shmem_base[1] =
6263  SHMEM2_RD(bp, other_shmem_base_addr);
6264  shmem2_base[1] =
6265  SHMEM2_RD(bp, other_shmem2_base_addr);
6266  }
6268  bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6269  bp->common.chip_id);
6271 }
6272 
6278 static int bnx2x_init_hw_common(struct bnx2x *bp)
6279 {
6280  u32 val;
6281 
6282  DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
6283 
6284  /*
6285  * take the UNDI lock to protect undi_unload flow from accessing
6286  * registers while we're resetting the chip
6287  */
6289 
6290  bnx2x_reset_common(bp);
6292 
6293  val = 0xfffc;
6294  if (CHIP_IS_E3(bp)) {
6297  }
6299 
6301 
6302  bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6303 
6304  if (!CHIP_IS_E1x(bp)) {
6305  u8 abs_func_id;
6306 
6314  for (abs_func_id = BP_PATH(bp);
6315  abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6316  if (abs_func_id == BP_ABS_FUNC(bp)) {
6317  REG_WR(bp,
6319  1);
6320  continue;
6321  }
6322 
6323  bnx2x_pretend_func(bp, abs_func_id);
6324  /* clear pf enable */
6325  bnx2x_pf_disable(bp);
6326  bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6327  }
6328  }
6329 
6330  bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6331  if (CHIP_IS_E1(bp)) {
6332  /* enable HW interrupt from PXP on USDM overflow
6333  bit 16 on INT_MASK_0 */
6335  }
6336 
6337  bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6338  bnx2x_init_pxp(bp);
6339 
6340 #ifdef __BIG_ENDIAN
6346  /* make sure this value is 0 */
6348 
6349 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6354 #endif
6355 
6356  bnx2x_ilt_init_page_size(bp, INITOP_SET);
6357 
6358  if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6359  REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6360 
6361  /* let the HW do it's magic ... */
6362  msleep(100);
6363  /* finish PXP init */
6364  val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6365  if (val != 1) {
6366  BNX2X_ERR("PXP2 CFG failed\n");
6367  return -EBUSY;
6368  }
6369  val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6370  if (val != 1) {
6371  BNX2X_ERR("PXP2 RD_INIT failed\n");
6372  return -EBUSY;
6373  }
6374 
6375  /* Timers bug workaround E2 only. We need to set the entire ILT to
6376  * have entries with value "0" and valid bit on.
6377  * This needs to be done by the first PF that is loaded in a path
6378  * (i.e. common phase)
6379  */
6380  if (!CHIP_IS_E1x(bp)) {
6381 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6382  * (i.e. vnic3) to start even if it is marked as "scan-off".
6383  * This occurs when a different function (func2,3) is being marked
6384  * as "scan-off". Real-life scenario for example: if a driver is being
6385  * load-unloaded while func6,7 are down. This will cause the timer to access
6386  * the ilt, translate to a logical address and send a request to read/write.
6387  * Since the ilt for the function that is down is not valid, this will cause
6388  * a translation error which is unrecoverable.
6389  * The Workaround is intended to make sure that when this happens nothing fatal
6390  * will occur. The workaround:
6391  * 1. First PF driver which loads on a path will:
6392  * a. After taking the chip out of reset, by using pretend,
6393  * it will write "0" to the following registers of
6394  * the other vnics.
6395  * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6396  * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6397  * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6398  * And for itself it will write '1' to
6399  * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6400  * dmae-operations (writing to pram for example.)
6401  * note: can be done for only function 6,7 but cleaner this
6402  * way.
6403  * b. Write zero+valid to the entire ILT.
6404  * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6405  * VNIC3 (of that port). The range allocated will be the
6406  * entire ILT. This is needed to prevent ILT range error.
6407  * 2. Any PF driver load flow:
6408  * a. ILT update with the physical addresses of the allocated
6409  * logical pages.
6410  * b. Wait 20msec. - note that this timeout is needed to make
6411  * sure there are no requests in one of the PXP internal
6412  * queues with "old" ILT addresses.
6413  * c. PF enable in the PGLC.
6414  * d. Clear the was_error of the PF in the PGLC. (could have
6415  * occured while driver was down)
6416  * e. PF enable in the CFC (WEAK + STRONG)
6417  * f. Timers scan enable
6418  * 3. PF driver unload flow:
6419  * a. Clear the Timers scan_en.
6420  * b. Polling for scan_on=0 for that PF.
6421  * c. Clear the PF enable bit in the PXP.
6422  * d. Clear the PF enable in the CFC (WEAK + STRONG)
6423  * e. Write zero+valid to all ILT entries (The valid bit must
6424  * stay set)
6425  * f. If this is VNIC 3 of a port then also init
6426  * first_timers_ilt_entry to zero and last_timers_ilt_entry
6427  * to the last enrty in the ILT.
6428  *
6429  * Notes:
6430  * Currently the PF error in the PGLC is non recoverable.
6431  * In the future the there will be a recovery routine for this error.
6432  * Currently attention is masked.
6433  * Having an MCP lock on the load/unload process does not guarantee that
6434  * there is no Timer disable during Func6/7 enable. This is because the
6435  * Timers scan is currently being cleared by the MCP on FLR.
6436  * Step 2.d can be done only for PF6/7 and the driver can also check if
6437  * there is error before clearing it. But the flow above is simpler and
6438  * more general.
6439  * All ILT entries are written by zero+valid and not just PF6/7
6440  * ILT entries since in the future the ILT entries allocation for
6441  * PF-s might be dynamic.
6442  */
6443  struct ilt_client_info ilt_cli;
6444  struct bnx2x_ilt ilt;
6445  memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6446  memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6447 
6448  /* initialize dummy TM client */
6449  ilt_cli.start = 0;
6450  ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6451  ilt_cli.client_num = ILT_CLIENT_TM;
6452 
6453  /* Step 1: set zeroes to all ilt page entries with valid bit on
6454  * Step 2: set the timers first/last ilt entry to point
6455  * to the entire range to prevent ILT range error for 3rd/4th
6456  * vnic (this code assumes existance of the vnic)
6457  *
6458  * both steps performed by call to bnx2x_ilt_client_init_op()
6459  * with dummy TM client
6460  *
6461  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6462  * and his brother are split registers
6463  */
6464  bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6465  bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6466  bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6467 
6471  }
6472 
6473 
6476 
6477  if (!CHIP_IS_E1x(bp)) {
6478  int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6479  (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6480  bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6481 
6482  bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6483 
6484  /* let the HW do it's magic ... */
6485  do {
6486  msleep(200);
6487  val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6488  } while (factor-- && (val != 1));
6489 
6490  if (val != 1) {
6491  BNX2X_ERR("ATC_INIT failed\n");
6492  return -EBUSY;
6493  }
6494  }
6495 
6496  bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6497 
6498  /* clean the DMAE memory */
6499  bp->dmae_ready = 1;
6500  bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6501 
6502  bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6503 
6504  bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6505 
6506  bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6507 
6508  bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6509 
6514 
6515  bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6516 
6517 
6518  /* QM queues pointers table */
6519  bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6520 
6521  /* soft reset pulse */
6522  REG_WR(bp, QM_REG_SOFT_RESET, 1);
6523  REG_WR(bp, QM_REG_SOFT_RESET, 0);
6524 
6525 #ifdef BCM_CNIC
6526  bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6527 #endif
6528 
6529  bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6531  if (!CHIP_REV_IS_SLOW(bp))
6532  /* enable hw interrupt from doorbell Q */
6534 
6535  bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6536 
6537  bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6538  REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6539 
6540  if (!CHIP_IS_E1(bp))
6542 
6543  if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6544  if (IS_MF_AFEX(bp)) {
6545  /* configure that VNTag and VLAN headers must be
6546  * received in afex mode
6547  */
6548  REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6549  REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6550  REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6551  REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6552  REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6553  } else {
6554  /* Bit-map indicating which L2 hdrs may appear
6555  * after the basic Ethernet header
6556  */
6558  bp->path_has_ovlan ? 7 : 6);
6559  }
6560  }
6561 
6562  bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6563  bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6564  bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6565  bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6566 
6567  if (!CHIP_IS_E1x(bp)) {
6568  /* reset VFC memories */
6575 
6576  msleep(20);
6577  }
6578 
6579  bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6580  bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6581  bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6582  bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6583 
6584  /* sync semi rtc */
6586  0x80000000);
6588  0x80000000);
6589 
6590  bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6591  bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6592  bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6593 
6594  if (!CHIP_IS_E1x(bp)) {
6595  if (IS_MF_AFEX(bp)) {
6596  /* configure that VNTag and VLAN headers must be
6597  * sent in afex mode
6598  */
6599  REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6600  REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6601  REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6602  REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6603  REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6604  } else {
6606  bp->path_has_ovlan ? 7 : 6);
6607  }
6608  }
6609 
6610  REG_WR(bp, SRC_REG_SOFT_RST, 1);
6611 
6612  bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6613 
6614 #ifdef BCM_CNIC
6615  REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6616  REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6617  REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6618  REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6619  REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6620  REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6621  REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6622  REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6623  REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6624  REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6625 #endif
6626  REG_WR(bp, SRC_REG_SOFT_RST, 0);
6627 
6628  if (sizeof(union cdu_context) != 1024)
6629  /* we currently assume that a context is 1024 bytes */
6630  dev_alert(&bp->pdev->dev,
6631  "please adjust the size of cdu_context(%ld)\n",
6632  (long)sizeof(union cdu_context));
6633 
6634  bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6635  val = (4 << 24) + (0 << 12) + 1024;
6637 
6638  bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6639  REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6640  /* enable context validation interrupt from CFC */
6641  REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6642 
6643  /* set the thresholds to prevent CFC/CDU race */
6644  REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6645 
6646  bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6647 
6648  if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6649  REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6650 
6651  bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6652  bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6653 
6654  /* Reset PCIE errors for debug */
6655  REG_WR(bp, 0x2814, 0xffffffff);
6656  REG_WR(bp, 0x3820, 0xffffffff);
6657 
6658  if (!CHIP_IS_E1x(bp)) {
6670  }
6671 
6672  bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6673  if (!CHIP_IS_E1(bp)) {
6674  /* in E3 this done in per-port section */
6675  if (!CHIP_IS_E3(bp))
6676  REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6677  }
6678  if (CHIP_IS_E1H(bp))
6679  /* not applicable for E2 (and above ...) */
6681 
6682  if (CHIP_REV_IS_SLOW(bp))
6683  msleep(200);
6684 
6685  /* finish CFC init */
6686  val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6687  if (val != 1) {
6688  BNX2X_ERR("CFC LL_INIT failed\n");
6689  return -EBUSY;
6690  }
6691  val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6692  if (val != 1) {
6693  BNX2X_ERR("CFC AC_INIT failed\n");
6694  return -EBUSY;
6695  }
6696  val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6697  if (val != 1) {
6698  BNX2X_ERR("CFC CAM_INIT failed\n");
6699  return -EBUSY;
6700  }
6701  REG_WR(bp, CFC_REG_DEBUG0, 0);
6702 
6703  if (CHIP_IS_E1(bp)) {
6704  /* read NIG statistic
6705  to see if this is our first up since powerup */
6707  val = *bnx2x_sp(bp, wb_data[0]);
6708 
6709  /* do internal memory self test */
6710  if ((val == 0) && bnx2x_int_mem_test(bp)) {
6711  BNX2X_ERR("internal mem self test failed\n");
6712  return -EBUSY;
6713  }
6714  }
6715 
6716  bnx2x_setup_fan_failure_detection(bp);
6717 
6718  /* clear PXP2 attentions */
6720 
6721  bnx2x_enable_blocks_attention(bp);
6722  bnx2x_enable_blocks_parity(bp);
6723 
6724  if (!BP_NOMCP(bp)) {
6725  if (CHIP_IS_E1x(bp))
6726  bnx2x__common_init_phy(bp);
6727  } else
6728  BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6729 
6730  return 0;
6731 }
6732 
6738 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6739 {
6740  int rc = bnx2x_init_hw_common(bp);
6741 
6742  if (rc)
6743  return rc;
6744 
6745  /* In E2 2-PORT mode, same ext phy is used for the two paths */
6746  if (!BP_NOMCP(bp))
6747  bnx2x__common_init_phy(bp);
6748 
6749  return 0;
6750 }
6751 
6752 static int bnx2x_init_hw_port(struct bnx2x *bp)
6753 {
6754  int port = BP_PORT(bp);
6755  int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6756  u32 low, high;
6757  u32 val;
6758 
6759 
6760  DP(NETIF_MSG_HW, "starting port init port %d\n", port);
6761 
6762  REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6763 
6764  bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6765  bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6766  bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6767 
6768  /* Timers bug workaround: disables the pf_master bit in pglue at
6769  * common phase, we need to enable it here before any dmae access are
6770  * attempted. Therefore we manually added the enable-master to the
6771  * port phase (it also happens in the function phase)
6772  */
6773  if (!CHIP_IS_E1x(bp))
6775 
6776  bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6777  bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6778  bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6779  bnx2x_init_block(bp, BLOCK_QM, init_phase);
6780 
6781  bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6782  bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6783  bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6784  bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6785 
6786  /* QM cid (connection) count */
6787  bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6788 
6789 #ifdef BCM_CNIC
6790  bnx2x_init_block(bp, BLOCK_TM, init_phase);
6791  REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6792  REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6793 #endif
6794 
6795  bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6796 
6797  bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6798 
6799  if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6800 
6801  if (IS_MF(bp))
6802  low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6803  else if (bp->dev->mtu > 4096) {
6804  if (bp->flags & ONE_PORT_FLAG)
6805  low = 160;
6806  else {
6807  val = bp->dev->mtu;
6808  /* (24*1024 + val*4)/256 */
6809  low = 96 + (val/64) +
6810  ((val % 64) ? 1 : 0);
6811  }
6812  } else
6813  low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6814  high = low + 56; /* 14*1024/256 */
6815  REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6816  REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6817  }
6818 
6819  if (CHIP_MODE_IS_4_PORT(bp))
6820  REG_WR(bp, (BP_PORT(bp) ?
6823 
6824 
6825  bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6826  if (CHIP_IS_E3B0(bp)) {
6827  if (IS_MF_AFEX(bp)) {
6828  /* configure headers for AFEX mode */
6829  REG_WR(bp, BP_PORT(bp) ?
6832  REG_WR(bp, BP_PORT(bp) ?
6835  REG_WR(bp, BP_PORT(bp) ?
6838  } else {
6839  /* Ovlan exists only if we are in multi-function +
6840  * switch-dependent mode, in switch-independent there
6841  * is no ovlan headers
6842  */
6843  REG_WR(bp, BP_PORT(bp) ?
6846  (bp->path_has_ovlan ? 7 : 6));
6847  }
6848  }
6849 
6850  bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6851  bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6852  bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6853  bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6854 
6855  bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6856  bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6857  bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6858  bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6859 
6860  bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6861  bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6862 
6863  bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6864 
6865  if (CHIP_IS_E1x(bp)) {
6866  /* configure PBF to work without PAUSE mtu 9000 */
6867  REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6868 
6869  /* update threshold */
6870  REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6871  /* update init credit */
6872  REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6873 
6874  /* probe changes */
6875  REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6876  udelay(50);
6877  REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6878  }
6879 
6880 #ifdef BCM_CNIC
6881  bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6882 #endif
6883  bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6884  bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6885 
6886  if (CHIP_IS_E1(bp)) {
6887  REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6888  REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6889  }
6890  bnx2x_init_block(bp, BLOCK_HC, init_phase);
6891 
6892  bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6893 
6894  bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6895  /* init aeu_mask_attn_func_0/1:
6896  * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6897  * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6898  * bits 4-7 are used for "per vn group attention" */
6899  val = IS_MF(bp) ? 0xF7 : 0x7;
6900  /* Enable DCBX attention for all but E1 */
6901  val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6902  REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6903 
6904  bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6905 
6906  if (!CHIP_IS_E1x(bp)) {
6907  /* Bit-map indicating which L2 hdrs may appear after the
6908  * basic Ethernet header
6909  */
6910  if (IS_MF_AFEX(bp))
6911  REG_WR(bp, BP_PORT(bp) ?
6914  else
6915  REG_WR(bp, BP_PORT(bp) ?
6918  IS_MF_SD(bp) ? 7 : 6);
6919 
6920  if (CHIP_IS_E3(bp))
6921  REG_WR(bp, BP_PORT(bp) ?
6923  NIG_REG_LLH_MF_MODE, IS_MF(bp));
6924  }
6925  if (!CHIP_IS_E3(bp))
6926  REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6927 
6928  if (!CHIP_IS_E1(bp)) {
6929  /* 0x2 disable mf_ov, 0x1 enable */
6931  (IS_MF_SD(bp) ? 0x1 : 0x2));
6932 
6933  if (!CHIP_IS_E1x(bp)) {
6934  val = 0;
6935  switch (bp->mf_mode) {
6936  case MULTI_FUNCTION_SD:
6937  val = 1;
6938  break;
6939  case MULTI_FUNCTION_SI:
6940  case MULTI_FUNCTION_AFEX:
6941  val = 2;
6942  break;
6943  }
6944 
6945  REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6946  NIG_REG_LLH0_CLS_TYPE), val);
6947  }
6948  {
6949  REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6950  REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6951  REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6952  }
6953  }
6954 
6955 
6956  /* If SPIO5 is set to generate interrupts, enable it for this port */
6957  val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6958  if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6959  u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6961  val = REG_RD(bp, reg_addr);
6963  REG_WR(bp, reg_addr, val);
6964  }
6965 
6966  return 0;
6967 }
6968 
6969 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6970 {
6971  int reg;
6972  u32 wb_write[2];
6973 
6974  if (CHIP_IS_E1(bp))
6975  reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6976  else
6977  reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6978 
6979  wb_write[0] = ONCHIP_ADDR1(addr);
6980  wb_write[1] = ONCHIP_ADDR2(addr);
6981  REG_WR_DMAE(bp, reg, wb_write, 2);
6982 }
6983 
6984 static void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func,
6985  u8 idu_sb_id, bool is_Pf)
6986 {
6987  u32 data, ctl, cnt = 100;
6988  u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
6989  u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
6990  u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
6991  u32 sb_bit = 1 << (idu_sb_id%32);
6992  u32 func_encode = func | (is_Pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
6993  u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
6994 
6995  /* Not supported in BC mode */
6996  if (CHIP_INT_MODE_IS_BC(bp))
6997  return;
6998 
7003 
7004  ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7005  func_encode << IGU_CTRL_REG_FID_SHIFT |
7007 
7008  DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7009  data, igu_addr_data);
7010  REG_WR(bp, igu_addr_data, data);
7011  mmiowb();
7012  barrier();
7013  DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7014  ctl, igu_addr_ctl);
7015  REG_WR(bp, igu_addr_ctl, ctl);
7016  mmiowb();
7017  barrier();
7018 
7019  /* wait for clean up to finish */
7020  while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7021  msleep(20);
7022 
7023 
7024  if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7025  DP(NETIF_MSG_HW,
7026  "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7027  idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7028  }
7029 }
7030 
7031 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7032 {
7033  bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7034 }
7035 
7036 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7037 {
7038  u32 i, base = FUNC_ILT_BASE(func);
7039  for (i = base; i < base + ILT_PER_FUNC; i++)
7040  bnx2x_ilt_wr(bp, i, 0);
7041 }
7042 
7043 static int bnx2x_init_hw_func(struct bnx2x *bp)
7044 {
7045  int port = BP_PORT(bp);
7046  int func = BP_FUNC(bp);
7047  int init_phase = PHASE_PF0 + func;
7048  struct bnx2x_ilt *ilt = BP_ILT(bp);
7049  u16 cdu_ilt_start;
7050  u32 addr, val;
7051  u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7052  int i, main_mem_width, rc;
7053 
7054  DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7055 
7056  /* FLR cleanup - hmmm */
7057  if (!CHIP_IS_E1x(bp)) {
7058  rc = bnx2x_pf_flr_clnup(bp);
7059  if (rc)
7060  return rc;
7061  }
7062 
7063  /* set MSI reconfigure capability */
7064  if (bp->common.int_block == INT_BLOCK_HC) {
7065  addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7066  val = REG_RD(bp, addr);
7068  REG_WR(bp, addr, val);
7069  }
7070 
7071  bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7072  bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7073 
7074  ilt = BP_ILT(bp);
7075  cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7076 
7077  for (i = 0; i < L2_ILT_LINES(bp); i++) {
7078  ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7079  ilt->lines[cdu_ilt_start + i].page_mapping =
7080  bp->context[i].cxt_mapping;
7081  ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7082  }
7083  bnx2x_ilt_init_op(bp, INITOP_SET);
7084 
7085 #ifdef BCM_CNIC
7086  bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7087 
7088  /* T1 hash bits value determines the T1 number of entries */
7089  REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7090 #endif
7091 
7092 #ifndef BCM_CNIC
7093  /* set NIC mode */
7094  REG_WR(bp, PRS_REG_NIC_MODE, 1);
7095 #endif /* BCM_CNIC */
7096 
7097  if (!CHIP_IS_E1x(bp)) {
7098  u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7099 
7100  /* Turn on a single ISR mode in IGU if driver is going to use
7101  * INT#x or MSI
7102  */
7103  if (!(bp->flags & USING_MSIX_FLAG))
7104  pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7105  /*
7106  * Timers workaround bug: function init part.
7107  * Need to wait 20msec after initializing ILT,
7108  * needed to make sure there are no requests in
7109  * one of the PXP internal queues with "old" ILT addresses
7110  */
7111  msleep(20);
7112  /*
7113  * Master enable - Due to WB DMAE writes performed before this
7114  * register is re-initialized as part of the regular function
7115  * init
7116  */
7118  /* Enable the function in IGU */
7119  REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7120  }
7121 
7122  bp->dmae_ready = 1;
7123 
7124  bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7125 
7126  if (!CHIP_IS_E1x(bp))
7128 
7129  bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7130  bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7131  bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7132  bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7133  bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7134  bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7135  bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7136  bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7137  bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7138  bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7139  bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7140  bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7141  bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7142 
7143  if (!CHIP_IS_E1x(bp))
7144  REG_WR(bp, QM_REG_PF_EN, 1);
7145 
7146  if (!CHIP_IS_E1x(bp)) {
7151  }
7152  bnx2x_init_block(bp, BLOCK_QM, init_phase);
7153 
7154  bnx2x_init_block(bp, BLOCK_TM, init_phase);
7155  bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7156  bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7157  bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7158  bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7159  bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7160  bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7161  bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7162  bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7163  bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7164  bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7165  if (!CHIP_IS_E1x(bp))
7166  REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7167 
7168  bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7169 
7170  bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7171 
7172  if (!CHIP_IS_E1x(bp))
7174 
7175  if (IS_MF(bp)) {
7176  REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7177  REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7178  }
7179 
7180  bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7181 
7182  /* HC init per function */
7183  if (bp->common.int_block == INT_BLOCK_HC) {
7184  if (CHIP_IS_E1H(bp)) {
7185  REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7186 
7187  REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7188  REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7189  }
7190  bnx2x_init_block(bp, BLOCK_HC, init_phase);
7191 
7192  } else {
7193  int num_segs, sb_idx, prod_offset;
7194 
7195  REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7196 
7197  if (!CHIP_IS_E1x(bp)) {
7200  }
7201 
7202  bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7203 
7204  if (!CHIP_IS_E1x(bp)) {
7205  int dsb_idx = 0;
7226  /* non-default-status-blocks */
7227  num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7229  for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7230  prod_offset = (bp->igu_base_sb + sb_idx) *
7231  num_segs;
7232 
7233  for (i = 0; i < num_segs; i++) {
7234  addr = IGU_REG_PROD_CONS_MEMORY +
7235  (prod_offset + i) * 4;
7236  REG_WR(bp, addr, 0);
7237  }
7238  /* send consumer update with value 0 */
7239  bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7240  USTORM_ID, 0, IGU_INT_NOP, 1);
7241  bnx2x_igu_clear_sb(bp,
7242  bp->igu_base_sb + sb_idx);
7243  }
7244 
7245  /* default-status-blocks */
7246  num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7248 
7249  if (CHIP_MODE_IS_4_PORT(bp))
7250  dsb_idx = BP_FUNC(bp);
7251  else
7252  dsb_idx = BP_VN(bp);
7253 
7254  prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7255  IGU_BC_BASE_DSB_PROD + dsb_idx :
7256  IGU_NORM_BASE_DSB_PROD + dsb_idx);
7257 
7258  /*
7259  * igu prods come in chunks of E1HVN_MAX (4) -
7260  * does not matters what is the current chip mode
7261  */
7262  for (i = 0; i < (num_segs * E1HVN_MAX);
7263  i += E1HVN_MAX) {
7264  addr = IGU_REG_PROD_CONS_MEMORY +
7265  (prod_offset + i)*4;
7266  REG_WR(bp, addr, 0);
7267  }
7268  /* send consumer update with 0 */
7269  if (CHIP_INT_MODE_IS_BC(bp)) {
7270  bnx2x_ack_sb(bp, bp->igu_dsb_id,
7271  USTORM_ID, 0, IGU_INT_NOP, 1);
7272  bnx2x_ack_sb(bp, bp->igu_dsb_id,
7273  CSTORM_ID, 0, IGU_INT_NOP, 1);
7274  bnx2x_ack_sb(bp, bp->igu_dsb_id,
7275  XSTORM_ID, 0, IGU_INT_NOP, 1);
7276  bnx2x_ack_sb(bp, bp->igu_dsb_id,
7277  TSTORM_ID, 0, IGU_INT_NOP, 1);
7278  bnx2x_ack_sb(bp, bp->igu_dsb_id,
7279  ATTENTION_ID, 0, IGU_INT_NOP, 1);
7280  } else {
7281  bnx2x_ack_sb(bp, bp->igu_dsb_id,
7282  USTORM_ID, 0, IGU_INT_NOP, 1);
7283  bnx2x_ack_sb(bp, bp->igu_dsb_id,
7284  ATTENTION_ID, 0, IGU_INT_NOP, 1);
7285  }
7286  bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7287 
7288  /* !!! these should become driver const once
7289  rf-tool supports split-68 const */
7292  REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7293  REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7296  }
7297  }
7298 
7299  /* Reset PCIE errors for debug */
7300  REG_WR(bp, 0x2114, 0xffffffff);
7301  REG_WR(bp, 0x2120, 0xffffffff);
7302 
7303  if (CHIP_IS_E1x(bp)) {
7304  main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7305  main_mem_base = HC_REG_MAIN_MEMORY +
7306  BP_PORT(bp) * (main_mem_size * 4);
7307  main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7308  main_mem_width = 8;
7309 
7310  val = REG_RD(bp, main_mem_prty_clr);
7311  if (val)
7312  DP(NETIF_MSG_HW,
7313  "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7314  val);
7315 
7316  /* Clear "false" parity errors in MSI-X table */
7317  for (i = main_mem_base;
7318  i < main_mem_base + main_mem_size * 4;
7319  i += main_mem_width) {
7320  bnx2x_read_dmae(bp, i, main_mem_width / 4);
7321  bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7322  i, main_mem_width / 4);
7323  }
7324  /* Clear HC parity attention */
7325  REG_RD(bp, main_mem_prty_clr);
7326  }
7327 
7328 #ifdef BNX2X_STOP_ON_ERROR
7329  /* Enable STORMs SP logging */
7338 #endif
7339 
7341 
7342  return 0;
7343 }
7344 
7345 
7346 void bnx2x_free_mem(struct bnx2x *bp)
7347 {
7348  int i;
7349 
7350  /* fastpath */
7351  bnx2x_free_fp_mem(bp);
7352  /* end of fastpath */
7353 
7355  sizeof(struct host_sp_status_block));
7356 
7358  bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7359 
7361  sizeof(struct bnx2x_slowpath));
7362 
7363  for (i = 0; i < L2_ILT_LINES(bp); i++)
7364  BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7365  bp->context[i].size);
7366  bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7367 
7368  BNX2X_FREE(bp->ilt->lines);
7369 
7370 #ifdef BCM_CNIC
7371  if (!CHIP_IS_E1x(bp))
7372  BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7373  sizeof(struct host_hc_status_block_e2));
7374  else
7375  BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7376  sizeof(struct host_hc_status_block_e1x));
7377 
7378  BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7379 #endif
7380 
7382 
7385 }
7386 
7387 static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
7388 {
7389  int num_groups;
7390  int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
7391 
7392  /* number of queues for statistics is number of eth queues + FCoE */
7393  u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
7394 
7395  /* Total number of FW statistics requests =
7396  * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
7397  * num of queues
7398  */
7399  bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
7400 
7401 
7402  /* Request is built from stats_query_header and an array of
7403  * stats_query_cmd_group each of which contains
7404  * STATS_QUERY_CMD_COUNT rules. The real number or requests is
7405  * configured in the stats_query_header.
7406  */
7407  num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) +
7408  (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
7409 
7410  bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
7411  num_groups * sizeof(struct stats_query_cmd_group);
7412 
7413  /* Data for statistics requests + stats_conter
7414  *
7415  * stats_counter holds per-STORM counters that are incremented
7416  * when STORM has finished with the current request.
7417  *
7418  * memory for FCoE offloaded statistics are counted anyway,
7419  * even if they will not be sent.
7420  */
7421  bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
7424  sizeof(struct per_queue_stats) * num_queue_stats +
7425  sizeof(struct stats_counter);
7426 
7428  bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7429 
7430  /* Set shortcuts */
7431  bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
7433 
7434  bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
7435  ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
7436 
7438  bp->fw_stats_req_sz;
7439  return 0;
7440 
7441 alloc_mem_err:
7443  bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7444  BNX2X_ERR("Can't allocate memory\n");
7445  return -ENOMEM;
7446 }
7447 
7448 
7449 int bnx2x_alloc_mem(struct bnx2x *bp)
7450 {
7451  int i, allocated, context_size;
7452 
7453 #ifdef BCM_CNIC
7454  if (!CHIP_IS_E1x(bp))
7455  /* size = the status block + ramrod buffers */
7456  BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7457  sizeof(struct host_hc_status_block_e2));
7458  else
7459  BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
7460  sizeof(struct host_hc_status_block_e1x));
7461 
7462  /* allocate searcher T2 table */
7463  BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7464 #endif
7465 
7466 
7468  sizeof(struct host_sp_status_block));
7469 
7471  sizeof(struct bnx2x_slowpath));
7472 
7473 #ifdef BCM_CNIC
7474  /* write address to which L5 should insert its values */
7475  bp->cnic_eth_dev.addr_drv_info_to_mcp = &bp->slowpath->drv_info_to_mcp;
7476 #endif
7477 
7478  /* Allocated memory for FW statistics */
7479  if (bnx2x_alloc_fw_stats_mem(bp))
7480  goto alloc_mem_err;
7481 
7482  /* Allocate memory for CDU context:
7483  * This memory is allocated separately and not in the generic ILT
7484  * functions because CDU differs in few aspects:
7485  * 1. There are multiple entities allocating memory for context -
7486  * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7487  * its own ILT lines.
7488  * 2. Since CDU page-size is not a single 4KB page (which is the case
7489  * for the other ILT clients), to be efficient we want to support
7490  * allocation of sub-page-size in the last entry.
7491  * 3. Context pointers are used by the driver to pass to FW / update
7492  * the context (for the other ILT clients the pointers are used just to
7493  * free the memory during unload).
7494  */
7495  context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7496 
7497  for (i = 0, allocated = 0; allocated < context_size; i++) {
7498  bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7499  (context_size - allocated));
7500  BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7501  &bp->context[i].cxt_mapping,
7502  bp->context[i].size);
7503  allocated += bp->context[i].size;
7504  }
7505  BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7506 
7507  if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7508  goto alloc_mem_err;
7509 
7510  /* Slow path ring */
7512 
7513  /* EQ */
7516 
7517 
7518  /* fastpath */
7519  /* need to be done at the end, since it's self adjusting to amount
7520  * of memory available for RSS queues
7521  */
7522  if (bnx2x_alloc_fp_mem(bp))
7523  goto alloc_mem_err;
7524  return 0;
7525 
7526 alloc_mem_err:
7527  bnx2x_free_mem(bp);
7528  BNX2X_ERR("Can't allocate memory\n");
7529  return -ENOMEM;
7530 }
7531 
7532 /*
7533  * Init service functions
7534  */
7535 
7536 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7537  struct bnx2x_vlan_mac_obj *obj, bool set,
7538  int mac_type, unsigned long *ramrod_flags)
7539 {
7540  int rc;
7541  struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7542 
7543  memset(&ramrod_param, 0, sizeof(ramrod_param));
7544 
7545  /* Fill general parameters */
7546  ramrod_param.vlan_mac_obj = obj;
7547  ramrod_param.ramrod_flags = *ramrod_flags;
7548 
7549  /* Fill a user request section if needed */
7550  if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7551  memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7552 
7553  __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7554 
7555  /* Set the command: ADD or DEL */
7556  if (set)
7557  ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7558  else
7559  ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7560  }
7561 
7562  rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7563 
7564  if (rc == -EEXIST) {
7565  DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7566  /* do not treat adding same MAC as error */
7567  rc = 0;
7568  } else if (rc < 0)
7569  BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7570 
7571  return rc;
7572 }
7573 
7574 int bnx2x_del_all_macs(struct bnx2x *bp,
7575  struct bnx2x_vlan_mac_obj *mac_obj,
7576  int mac_type, bool wait_for_comp)
7577 {
7578  int rc;
7579  unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7580 
7581  /* Wait for completion of requested */
7582  if (wait_for_comp)
7583  __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7584 
7585  /* Set the mac type of addresses we want to clear */
7586  __set_bit(mac_type, &vlan_mac_flags);
7587 
7588  rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7589  if (rc < 0)
7590  BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7591 
7592  return rc;
7593 }
7594 
7595 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7596 {
7597  unsigned long ramrod_flags = 0;
7598 
7599 #ifdef BCM_CNIC
7600  if (is_zero_ether_addr(bp->dev->dev_addr) &&
7601  (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
7603  "Ignoring Zero MAC for STORAGE SD mode\n");
7604  return 0;
7605  }
7606 #endif
7607 
7608  DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7609 
7610  __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7611  /* Eth MAC is set on RSS leading client (fp[0]) */
7612  return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7613  set, BNX2X_ETH_MAC, &ramrod_flags);
7614 }
7615 
7617 {
7618  return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7619 }
7620 
7628 void bnx2x_set_int_mode(struct bnx2x *bp)
7629 {
7630  switch (int_mode) {
7631  case INT_MODE_MSI:
7632  bnx2x_enable_msi(bp);
7633  /* falling through... */
7634  case INT_MODE_INTx:
7635  bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7636  BNX2X_DEV_INFO("set number of queues to 1\n");
7637  break;
7638  default:
7639  /* if we can't use MSI-X we only need one fp,
7640  * so try to enable MSI-X with the requested number of fp's
7641  * and fallback to MSI or legacy INTx with one fp
7642  */
7643  if (bnx2x_enable_msix(bp) ||
7644  bp->flags & USING_SINGLE_MSIX_FLAG) {
7645  /* failed to enable multiple MSI-X */
7646  BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7647  bp->num_queues, 1 + NON_ETH_CONTEXT_USE);
7648 
7649  bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7650 
7651  /* Try to enable MSI */
7652  if (!(bp->flags & USING_SINGLE_MSIX_FLAG) &&
7653  !(bp->flags & DISABLE_MSI_FLAG))
7654  bnx2x_enable_msi(bp);
7655  }
7656  break;
7657  }
7658 }
7659 
7660 /* must be called prioir to any HW initializations */
7661 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7662 {
7663  return L2_ILT_LINES(bp);
7664 }
7665 
7666 void bnx2x_ilt_set_info(struct bnx2x *bp)
7667 {
7668  struct ilt_client_info *ilt_client;
7669  struct bnx2x_ilt *ilt = BP_ILT(bp);
7670  u16 line = 0;
7671 
7672  ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7673  DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7674 
7675  /* CDU */
7676  ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7677  ilt_client->client_num = ILT_CLIENT_CDU;
7678  ilt_client->page_size = CDU_ILT_PAGE_SZ;
7679  ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7680  ilt_client->start = line;
7681  line += bnx2x_cid_ilt_lines(bp);
7682 #ifdef BCM_CNIC
7683  line += CNIC_ILT_LINES;
7684 #endif
7685  ilt_client->end = line - 1;
7686 
7687  DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7688  ilt_client->start,
7689  ilt_client->end,
7690  ilt_client->page_size,
7691  ilt_client->flags,
7692  ilog2(ilt_client->page_size >> 12));
7693 
7694  /* QM */
7695  if (QM_INIT(bp->qm_cid_count)) {
7696  ilt_client = &ilt->clients[ILT_CLIENT_QM];
7697  ilt_client->client_num = ILT_CLIENT_QM;
7698  ilt_client->page_size = QM_ILT_PAGE_SZ;
7699  ilt_client->flags = 0;
7700  ilt_client->start = line;
7701 
7702  /* 4 bytes for each cid */
7703  line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7704  QM_ILT_PAGE_SZ);
7705 
7706  ilt_client->end = line - 1;
7707 
7709  "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7710  ilt_client->start,
7711  ilt_client->end,
7712  ilt_client->page_size,
7713  ilt_client->flags,
7714  ilog2(ilt_client->page_size >> 12));
7715 
7716  }
7717  /* SRC */
7718  ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7719 #ifdef BCM_CNIC
7720  ilt_client->client_num = ILT_CLIENT_SRC;
7721  ilt_client->page_size = SRC_ILT_PAGE_SZ;
7722  ilt_client->flags = 0;
7723  ilt_client->start = line;
7724  line += SRC_ILT_LINES;
7725  ilt_client->end = line - 1;
7726 
7728  "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7729  ilt_client->start,
7730  ilt_client->end,
7731  ilt_client->page_size,
7732  ilt_client->flags,
7733  ilog2(ilt_client->page_size >> 12));
7734 
7735 #else
7737 #endif
7738 
7739  /* TM */
7740  ilt_client = &ilt->clients[ILT_CLIENT_TM];
7741 #ifdef BCM_CNIC
7742  ilt_client->client_num = ILT_CLIENT_TM;
7743  ilt_client->page_size = TM_ILT_PAGE_SZ;
7744  ilt_client->flags = 0;
7745  ilt_client->start = line;
7746  line += TM_ILT_LINES;
7747  ilt_client->end = line - 1;
7748 
7750  "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7751  ilt_client->start,
7752  ilt_client->end,
7753  ilt_client->page_size,
7754  ilt_client->flags,
7755  ilog2(ilt_client->page_size >> 12));
7756 
7757 #else
7759 #endif
7760  BUG_ON(line > ILT_MAX_LINES);
7761 }
7762 
7774 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7775  struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7776 {
7777 
7778  u8 cos;
7779  int cxt_index, cxt_offset;
7780 
7781  /* FCoE Queue uses Default SB, thus has no HC capabilities */
7782  if (!IS_FCOE_FP(fp)) {
7783  __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7784  __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7785 
7786  /* If HC is supporterd, enable host coalescing in the transition
7787  * to INIT state.
7788  */
7789  __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7790  __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7791 
7792  /* HC rate */
7793  init_params->rx.hc_rate = bp->rx_ticks ?
7794  (1000000 / bp->rx_ticks) : 0;
7795  init_params->tx.hc_rate = bp->tx_ticks ?
7796  (1000000 / bp->tx_ticks) : 0;
7797 
7798  /* FW SB ID */
7799  init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7800  fp->fw_sb_id;
7801 
7802  /*
7803  * CQ index among the SB indices: FCoE clients uses the default
7804  * SB, therefore it's different.
7805  */
7806  init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7807  init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7808  }
7809 
7810  /* set maximum number of COSs supported by this queue */
7811  init_params->max_cos = fp->max_cos;
7812 
7813  DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
7814  fp->index, init_params->max_cos);
7815 
7816  /* set the context pointers queue object */
7817  for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
7818  cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
7819  cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
7820  ILT_PAGE_CIDS);
7821  init_params->cxts[cos] =
7822  &bp->context[cxt_index].vcxt[cxt_offset].eth;
7823  }
7824 }
7825 
7826 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7827  struct bnx2x_queue_state_params *q_params,
7828  struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7829  int tx_index, bool leading)
7830 {
7831  memset(tx_only_params, 0, sizeof(*tx_only_params));
7832 
7833  /* Set the command */
7834  q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7835 
7836  /* Set tx-only QUEUE flags: don't zero statistics */
7837  tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7838 
7839  /* choose the index of the cid to send the slow path on */
7840  tx_only_params->cid_index = tx_index;
7841 
7842  /* Set general TX_ONLY_SETUP parameters */
7843  bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7844 
7845  /* Set Tx TX_ONLY_SETUP parameters */
7846  bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7847 
7849  "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
7850  tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7851  q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7852  tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7853 
7854  /* send the ramrod */
7855  return bnx2x_queue_state_change(bp, q_params);
7856 }
7857 
7858 
7870 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7871  bool leading)
7872 {
7873  struct bnx2x_queue_state_params q_params = {NULL};
7874  struct bnx2x_queue_setup_params *setup_params =
7875  &q_params.params.setup;
7876  struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7877  &q_params.params.tx_only;
7878  int rc;
7879  u8 tx_index;
7880 
7881  DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
7882 
7883  /* reset IGU state skip FCoE L2 queue */
7884  if (!IS_FCOE_FP(fp))
7885  bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
7886  IGU_INT_ENABLE, 0);
7887 
7888  q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
7889  /* We want to wait for completion in this context */
7891 
7892  /* Prepare the INIT parameters */
7893  bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
7894 
7895  /* Set the command */
7896  q_params.cmd = BNX2X_Q_CMD_INIT;
7897 
7898  /* Change the state to INIT */
7899  rc = bnx2x_queue_state_change(bp, &q_params);
7900  if (rc) {
7901  BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
7902  return rc;
7903  }
7904 
7905  DP(NETIF_MSG_IFUP, "init complete\n");
7906 
7907 
7908  /* Now move the Queue to the SETUP state... */
7909  memset(setup_params, 0, sizeof(*setup_params));
7910 
7911  /* Set QUEUE flags */
7912  setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
7913 
7914  /* Set general SETUP parameters */
7915  bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7917 
7918  bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
7919  &setup_params->rxq_params);
7920 
7921  bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7923 
7924  /* Set the command */
7925  q_params.cmd = BNX2X_Q_CMD_SETUP;
7926 
7927  /* Change the state to SETUP */
7928  rc = bnx2x_queue_state_change(bp, &q_params);
7929  if (rc) {
7930  BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7931  return rc;
7932  }
7933 
7934  /* loop through the relevant tx-only indices */
7935  for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7936  tx_index < fp->max_cos;
7937  tx_index++) {
7938 
7939  /* prepare and send tx-only ramrod*/
7940  rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7941  tx_only_params, tx_index, leading);
7942  if (rc) {
7943  BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7944  fp->index, tx_index);
7945  return rc;
7946  }
7947  }
7948 
7949  return rc;
7950 }
7951 
7952 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7953 {
7954  struct bnx2x_fastpath *fp = &bp->fp[index];
7955  struct bnx2x_fp_txdata *txdata;
7956  struct bnx2x_queue_state_params q_params = {NULL};
7957  int rc, tx_index;
7958 
7959  DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
7960 
7961  q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
7962  /* We want to wait for completion in this context */
7964 
7965 
7966  /* close tx-only connections */
7967  for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7968  tx_index < fp->max_cos;
7969  tx_index++){
7970 
7971  /* ascertain this is a normal queue*/
7972  txdata = fp->txdata_ptr[tx_index];
7973 
7974  DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
7975  txdata->txq_index);
7976 
7977  /* send halt terminate on tx-only connection */
7978  q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7979  memset(&q_params.params.terminate, 0,
7980  sizeof(q_params.params.terminate));
7981  q_params.params.terminate.cid_index = tx_index;
7982 
7983  rc = bnx2x_queue_state_change(bp, &q_params);
7984  if (rc)
7985  return rc;
7986 
7987  /* send halt terminate on tx-only connection */
7988  q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7989  memset(&q_params.params.cfc_del, 0,
7990  sizeof(q_params.params.cfc_del));
7991  q_params.params.cfc_del.cid_index = tx_index;
7992  rc = bnx2x_queue_state_change(bp, &q_params);
7993  if (rc)
7994  return rc;
7995  }
7996  /* Stop the primary connection: */
7997  /* ...halt the connection */
7998  q_params.cmd = BNX2X_Q_CMD_HALT;
7999  rc = bnx2x_queue_state_change(bp, &q_params);
8000  if (rc)
8001  return rc;
8002 
8003  /* ...terminate the connection */
8004  q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8005  memset(&q_params.params.terminate, 0,
8006  sizeof(q_params.params.terminate));
8007  q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8008  rc = bnx2x_queue_state_change(bp, &q_params);
8009  if (rc)
8010  return rc;
8011  /* ...delete cfc entry */
8012  q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8013  memset(&q_params.params.cfc_del, 0,
8014  sizeof(q_params.params.cfc_del));
8015  q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8016  return bnx2x_queue_state_change(bp, &q_params);
8017 }
8018 
8019 
8020 static void bnx2x_reset_func(struct bnx2x *bp)
8021 {
8022  int port = BP_PORT(bp);
8023  int func = BP_FUNC(bp);
8024  int i;
8025 
8026  /* Disable the function in the FW */
8031 
8032  /* FP SBs */
8033  for_each_eth_queue(bp, i) {
8034  struct bnx2x_fastpath *fp = &bp->fp[i];
8037  SB_DISABLED);
8038  }
8039 
8040 #ifdef BCM_CNIC
8041  /* CNIC SB */
8043  CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
8044  SB_DISABLED);
8045 #endif
8046  /* SP SB */
8049  SB_DISABLED);
8050 
8051  for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8053  0);
8054 
8055  /* Configure IGU */
8056  if (bp->common.int_block == INT_BLOCK_HC) {
8057  REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8058  REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8059  } else {
8062  }
8063 
8064 #ifdef BCM_CNIC
8065  /* Disable Timer scan */
8066  REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8067  /*
8068  * Wait for at least 10ms and up to 2 second for the timers scan to
8069  * complete
8070  */
8071  for (i = 0; i < 200; i++) {
8072  msleep(10);
8073  if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8074  break;
8075  }
8076 #endif
8077  /* Clear ILT */
8078  bnx2x_clear_func_ilt(bp, func);
8079 
8080  /* Timers workaround bug for E2: if this is vnic-3,
8081  * we need to set the entire ilt range for this timers.
8082  */
8083  if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8084  struct ilt_client_info ilt_cli;
8085  /* use dummy TM client */
8086  memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8087  ilt_cli.start = 0;
8088  ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8089  ilt_cli.client_num = ILT_CLIENT_TM;
8090 
8091  bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8092  }
8093 
8094  /* this assumes that reset_port() called before reset_func()*/
8095  if (!CHIP_IS_E1x(bp))
8096  bnx2x_pf_disable(bp);
8097 
8098  bp->dmae_ready = 0;
8099 }
8100 
8101 static void bnx2x_reset_port(struct bnx2x *bp)
8102 {
8103  int port = BP_PORT(bp);
8104  u32 val;
8105 
8106  /* Reset physical Link */
8107  bnx2x__link_reset(bp);
8108 
8109  REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8110 
8111  /* Do not rcv packets to BRB */
8112  REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8113  /* Do not direct rcv packets that are not for MCP to the BRB */
8114  REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8116 
8117  /* Configure AEU */
8118  REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8119 
8120  msleep(100);
8121  /* Check for BRB port occupancy */
8122  val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8123  if (val)
8125  "BRB1 is not empty %d blocks are occupied\n", val);
8126 
8127  /* TODO: Close Doorbell port? */
8128 }
8129 
8130 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8131 {
8132  struct bnx2x_func_state_params func_params = {NULL};
8133 
8134  /* Prepare parameters for function state transitions */
8135  __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8136 
8137  func_params.f_obj = &bp->func_obj;
8138  func_params.cmd = BNX2X_F_CMD_HW_RESET;
8139 
8140  func_params.params.hw_init.load_phase = load_code;
8141 
8142  return bnx2x_func_state_change(bp, &func_params);
8143 }
8144 
8145 static int bnx2x_func_stop(struct bnx2x *bp)
8146 {
8147  struct bnx2x_func_state_params func_params = {NULL};
8148  int rc;
8149 
8150  /* Prepare parameters for function state transitions */
8151  __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8152  func_params.f_obj = &bp->func_obj;
8153  func_params.cmd = BNX2X_F_CMD_STOP;
8154 
8155  /*
8156  * Try to stop the function the 'good way'. If fails (in case
8157  * of a parity error during bnx2x_chip_cleanup()) and we are
8158  * not in a debug mode, perform a state transaction in order to
8159  * enable further HW_RESET transaction.
8160  */
8161  rc = bnx2x_func_state_change(bp, &func_params);
8162  if (rc) {
8163 #ifdef BNX2X_STOP_ON_ERROR
8164  return rc;
8165 #else
8166  BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8168  return bnx2x_func_state_change(bp, &func_params);
8169 #endif
8170  }
8171 
8172  return 0;
8173 }
8174 
8183 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8184 {
8185  u32 reset_code = 0;
8186  int port = BP_PORT(bp);
8187 
8188  /* Select the UNLOAD request mode */
8189  if (unload_mode == UNLOAD_NORMAL)
8190  reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8191 
8192  else if (bp->flags & NO_WOL_FLAG)
8193  reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8194 
8195  else if (bp->wol) {
8196  u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8197  u8 *mac_addr = bp->dev->dev_addr;
8198  u32 val;
8199  u16 pmc;
8200 
8201  /* The mac address is written to entries 1-4 to
8202  * preserve entry 0 which is used by the PMF
8203  */
8204  u8 entry = (BP_VN(bp) + 1)*8;
8205 
8206  val = (mac_addr[0] << 8) | mac_addr[1];
8207  EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8208 
8209  val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8210  (mac_addr[4] << 8) | mac_addr[5];
8211  EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8212 
8213  /* Enable the PME and clear the status */
8214  pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8216  pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8217 
8218  reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8219 
8220  } else
8221  reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8222 
8223  /* Send the request to the MCP */
8224  if (!BP_NOMCP(bp))
8225  reset_code = bnx2x_fw_command(bp, reset_code, 0);
8226  else {
8227  int path = BP_PATH(bp);
8228 
8229  DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
8230  path, load_count[path][0], load_count[path][1],
8231  load_count[path][2]);
8232  load_count[path][0]--;
8233  load_count[path][1 + port]--;
8234  DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
8235  path, load_count[path][0], load_count[path][1],
8236  load_count[path][2]);
8237  if (load_count[path][0] == 0)
8238  reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8239  else if (load_count[path][1 + port] == 0)
8240  reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8241  else
8242  reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8243  }
8244 
8245  return reset_code;
8246 }
8247 
8254 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8255 {
8256  u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8257 
8258  /* Report UNLOAD_DONE to MCP */
8259  if (!BP_NOMCP(bp))
8260  bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8261 }
8262 
8263 static int bnx2x_func_wait_started(struct bnx2x *bp)
8264 {
8265  int tout = 50;
8266  int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8267 
8268  if (!bp->port.pmf)
8269  return 0;
8270 
8271  /*
8272  * (assumption: No Attention from MCP at this stage)
8273  * PMF probably in the middle of TXdisable/enable transaction
8274  * 1. Sync IRS for default SB
8275  * 2. Sync SP queue - this guarantes us that attention handling started
8276  * 3. Wait, that TXdisable/enable transaction completes
8277  *
8278  * 1+2 guranty that if DCBx attention was scheduled it already changed
8279  * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8280  * received complettion for the transaction the state is TX_STOPPED.
8281  * State will return to STARTED after completion of TX_STOPPED-->STARTED
8282  * transaction.
8283  */
8284 
8285  /* make sure default SB ISR is done */
8286  if (msix)
8287  synchronize_irq(bp->msix_table[0].vector);
8288  else
8289  synchronize_irq(bp->pdev->irq);
8290 
8291  flush_workqueue(bnx2x_wq);
8292 
8293  while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8294  BNX2X_F_STATE_STARTED && tout--)
8295  msleep(20);
8296 
8297  if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8299 #ifdef BNX2X_STOP_ON_ERROR
8300  BNX2X_ERR("Wrong function state\n");
8301  return -EBUSY;
8302 #else
8303  /*
8304  * Failed to complete the transaction in a "good way"
8305  * Force both transactions with CLR bit
8306  */
8307  struct bnx2x_func_state_params func_params = {NULL};
8308 
8310  "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8311 
8312  func_params.f_obj = &bp->func_obj;
8314  &func_params.ramrod_flags);
8315 
8316  /* STARTED-->TX_ST0PPED */
8317  func_params.cmd = BNX2X_F_CMD_TX_STOP;
8318  bnx2x_func_state_change(bp, &func_params);
8319 
8320  /* TX_ST0PPED-->STARTED */
8321  func_params.cmd = BNX2X_F_CMD_TX_START;
8322  return bnx2x_func_state_change(bp, &func_params);
8323 #endif
8324  }
8325 
8326  return 0;
8327 }
8328 
8329 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8330 {
8331  int port = BP_PORT(bp);
8332  int i, rc = 0;
8333  u8 cos;
8334  struct bnx2x_mcast_ramrod_params rparam = {NULL};
8335  u32 reset_code;
8336 
8337  /* Wait until tx fastpath tasks complete */
8338  for_each_tx_queue(bp, i) {
8339  struct bnx2x_fastpath *fp = &bp->fp[i];
8340 
8341  for_each_cos_in_tx_queue(fp, cos)
8342  rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8343 #ifdef BNX2X_STOP_ON_ERROR
8344  if (rc)
8345  return;
8346 #endif
8347  }
8348 
8349  /* Give HW time to discard old tx messages */
8350  usleep_range(1000, 1000);
8351 
8352  /* Clean all ETH MACs */
8353  rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8354  false);
8355  if (rc < 0)
8356  BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8357 
8358  /* Clean up UC list */
8359  rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8360  true);
8361  if (rc < 0)
8362  BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8363  rc);
8364 
8365  /* Disable LLH */
8366  if (!CHIP_IS_E1(bp))
8367  REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8368 
8369  /* Set "drop all" (stop Rx).
8370  * We need to take a netif_addr_lock() here in order to prevent
8371  * a race between the completion code and this code.
8372  */
8373  netif_addr_lock_bh(bp->dev);
8374  /* Schedule the rx_mode command */
8377  else
8379 
8380  /* Cleanup multicast configuration */
8381  rparam.mcast_obj = &bp->mcast_obj;
8382  rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8383  if (rc < 0)
8384  BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8385 
8386  netif_addr_unlock_bh(bp->dev);
8387 
8388 
8389 
8390  /*
8391  * Send the UNLOAD_REQUEST to the MCP. This will return if
8392  * this function should perform FUNC, PORT or COMMON HW
8393  * reset.
8394  */
8395  reset_code = bnx2x_send_unload_req(bp, unload_mode);
8396 
8397  /*
8398  * (assumption: No Attention from MCP at this stage)
8399  * PMF probably in the middle of TXdisable/enable transaction
8400  */
8401  rc = bnx2x_func_wait_started(bp);
8402  if (rc) {
8403  BNX2X_ERR("bnx2x_func_wait_started failed\n");
8404 #ifdef BNX2X_STOP_ON_ERROR
8405  return;
8406 #endif
8407  }
8408 
8409  /* Close multi and leading connections
8410  * Completions for ramrods are collected in a synchronous way
8411  */
8412  for_each_queue(bp, i)
8413  if (bnx2x_stop_queue(bp, i))
8414 #ifdef BNX2X_STOP_ON_ERROR
8415  return;
8416 #else
8417  goto unload_error;
8418 #endif
8419  /* If SP settings didn't get completed so far - something
8420  * very wrong has happen.
8421  */
8422  if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8423  BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8424 
8425 #ifndef BNX2X_STOP_ON_ERROR
8426 unload_error:
8427 #endif
8428  rc = bnx2x_func_stop(bp);
8429  if (rc) {
8430  BNX2X_ERR("Function stop failed!\n");
8431 #ifdef BNX2X_STOP_ON_ERROR
8432  return;
8433 #endif
8434  }
8435 
8436  /* Disable HW interrupts, NAPI */
8437  bnx2x_netif_stop(bp, 1);
8438  /* Delete all NAPI objects */
8439  bnx2x_del_all_napi(bp);
8440 
8441  /* Release IRQs */
8442  bnx2x_free_irq(bp);
8443 
8444  /* Reset the chip */
8445  rc = bnx2x_reset_hw(bp, reset_code);
8446  if (rc)
8447  BNX2X_ERR("HW_RESET failed\n");
8448 
8449 
8450  /* Report UNLOAD_DONE to MCP */
8451  bnx2x_send_unload_done(bp, keep_link);
8452 }
8453 
8455 {
8456  u32 val;
8457 
8458  DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8459 
8460  if (CHIP_IS_E1(bp)) {
8461  int port = BP_PORT(bp);
8462  u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8464 
8465  val = REG_RD(bp, addr);
8466  val &= ~(0x300);
8467  REG_WR(bp, addr, val);
8468  } else {
8469  val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8473  }
8474 }
8475 
8476 /* Close gates #2, #3 and #4: */
8477 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8478 {
8479  u32 val;
8480 
8481  /* Gates #2 and #4a are closed/opened for "not E1" only */
8482  if (!CHIP_IS_E1(bp)) {
8483  /* #4 */
8484  REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8485  /* #2 */
8487  }
8488 
8489  /* #3 */
8490  if (CHIP_IS_E1x(bp)) {
8491  /* Prevent interrupts from HC on both ports */
8492  val = REG_RD(bp, HC_REG_CONFIG_1);
8493  REG_WR(bp, HC_REG_CONFIG_1,
8494  (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8496 
8497  val = REG_RD(bp, HC_REG_CONFIG_0);
8498  REG_WR(bp, HC_REG_CONFIG_0,
8499  (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8501  } else {
8502  /* Prevent incomming interrupts in IGU */
8504 
8506  (!close) ?
8509  }
8510 
8511  DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8512  close ? "closing" : "opening");
8513  mmiowb();
8514 }
8515 
8516 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8517 
8518 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8519 {
8520  /* Do some magic... */
8521  u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8522  *magic_val = val & SHARED_MF_CLP_MAGIC;
8523  MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8524 }
8525 
8532 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8533 {
8534  /* Restore the `magic' bit value... */
8535  u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8536  MF_CFG_WR(bp, shared_mf_config.clp_mb,
8537  (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8538 }
8539 
8548 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8549 {
8550  u32 shmem;
8551  u32 validity_offset;
8552 
8553  DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8554 
8555  /* Set `magic' bit in order to save MF config */
8556  if (!CHIP_IS_E1(bp))
8557  bnx2x_clp_reset_prep(bp, magic_val);
8558 
8559  /* Get shmem offset */
8560  shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8561  validity_offset = offsetof(struct shmem_region, validity_map[0]);
8562 
8563  /* Clear validity map flags */
8564  if (shmem > 0)
8565  REG_WR(bp, shmem + validity_offset, 0);
8566 }
8567 
8568 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8569 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
8570 
8576 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
8577 {
8578  /* special handling for emulation and FPGA,
8579  wait 10 times longer */
8580  if (CHIP_REV_IS_SLOW(bp))
8581  msleep(MCP_ONE_TIMEOUT*10);
8582  else
8584 }
8585 
8586 /*
8587  * initializes bp->common.shmem_base and waits for validity signature to appear
8588  */
8589 static int bnx2x_init_shmem(struct bnx2x *bp)
8590 {
8591  int cnt = 0;
8592  u32 val = 0;
8593 
8594  do {
8595  bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8596  if (bp->common.shmem_base) {
8597  val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8598  if (val & SHR_MEM_VALIDITY_MB)
8599  return 0;
8600  }
8601 
8602  bnx2x_mcp_wait_one(bp);
8603 
8604  } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8605 
8606  BNX2X_ERR("BAD MCP validity signature\n");
8607 
8608  return -ENODEV;
8609 }
8610 
8611 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8612 {
8613  int rc = bnx2x_init_shmem(bp);
8614 
8615  /* Restore the `magic' bit value */
8616  if (!CHIP_IS_E1(bp))
8617  bnx2x_clp_reset_done(bp, magic_val);
8618 
8619  return rc;
8620 }
8621 
8622 static void bnx2x_pxp_prep(struct bnx2x *bp)
8623 {
8624  if (!CHIP_IS_E1(bp)) {
8626  REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8627  mmiowb();
8628  }
8629 }
8630 
8631 /*
8632  * Reset the whole chip except for:
8633  * - PCIE core
8634  * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8635  * one reset bit)
8636  * - IGU
8637  * - MISC (including AEU)
8638  * - GRC
8639  * - RBCN, RBCP
8640  */
8641 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8642 {
8643  u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8644  u32 global_bits2, stay_reset2;
8645 
8646  /*
8647  * Bits that have to be set in reset_mask2 if we want to reset 'global'
8648  * (per chip) blocks.
8649  */
8650  global_bits2 =
8653 
8654  /* Don't reset the following blocks */
8655  not_reset_mask1 =
8659 
8660  not_reset_mask2 =
8671 
8672  /*
8673  * Keep the following blocks in reset:
8674  * - all xxMACs are handled by the bnx2x_link code.
8675  */
8676  stay_reset2 =
8685 
8686  /* Full reset masks according to the chip */
8687  reset_mask1 = 0xffffffff;
8688 
8689  if (CHIP_IS_E1(bp))
8690  reset_mask2 = 0xffff;
8691  else if (CHIP_IS_E1H(bp))
8692  reset_mask2 = 0x1ffff;
8693  else if (CHIP_IS_E2(bp))
8694  reset_mask2 = 0xfffff;
8695  else /* CHIP_IS_E3 */
8696  reset_mask2 = 0x3ffffff;
8697 
8698  /* Don't reset global blocks unless we need to */
8699  if (!global)
8700  reset_mask2 &= ~global_bits2;
8701 
8702  /*
8703  * In case of attention in the QM, we need to reset PXP
8704  * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8705  * because otherwise QM reset would release 'close the gates' shortly
8706  * before resetting the PXP, then the PSWRQ would send a write
8707  * request to PGLUE. Then when PXP is reset, PGLUE would try to
8708  * read the payload data from PSWWR, but PSWWR would not
8709  * respond. The write queue in PGLUE would stuck, dmae commands
8710  * would not return. Therefore it's important to reset the second
8711  * reset register (containing the
8712  * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8713  * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8714  * bit).
8715  */
8717  reset_mask2 & (~not_reset_mask2));
8718 
8720  reset_mask1 & (~not_reset_mask1));
8721 
8722  barrier();
8723  mmiowb();
8724 
8726  reset_mask2 & (~stay_reset2));
8727 
8728  barrier();
8729  mmiowb();
8730 
8732  mmiowb();
8733 }
8734 
8744 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8745 {
8746  u32 cnt = 1000;
8747  u32 pend_bits = 0;
8748 
8749  do {
8750  pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8751 
8752  if (pend_bits == 0)
8753  break;
8754 
8755  usleep_range(1000, 1000);
8756  } while (cnt-- > 0);
8757 
8758  if (cnt <= 0) {
8759  BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8760  pend_bits);
8761  return -EBUSY;
8762  }
8763 
8764  return 0;
8765 }
8766 
8767 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8768 {
8769  int cnt = 1000;
8770  u32 val = 0;
8771  u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8772 
8773 
8774  /* Empty the Tetris buffer, wait for 1s */
8775  do {
8776  sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8777  blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8778  port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8779  port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8780  pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8781  if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8782  ((port_is_idle_0 & 0x1) == 0x1) &&
8783  ((port_is_idle_1 & 0x1) == 0x1) &&
8784  (pgl_exp_rom2 == 0xffffffff))
8785  break;
8786  usleep_range(1000, 1000);
8787  } while (cnt-- > 0);
8788 
8789  if (cnt <= 0) {
8790  BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
8791  BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8792  sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8793  pgl_exp_rom2);
8794  return -EAGAIN;
8795  }
8796 
8797  barrier();
8798 
8799  /* Close gates #2, #3 and #4 */
8800  bnx2x_set_234_gates(bp, true);
8801 
8802  /* Poll for IGU VQs for 57712 and newer chips */
8803  if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8804  return -EAGAIN;
8805 
8806 
8807  /* TBD: Indicate that "process kill" is in progress to MCP */
8808 
8809  /* Clear "unprepared" bit */
8810  REG_WR(bp, MISC_REG_UNPREPARED, 0);
8811  barrier();
8812 
8813  /* Make sure all is written to the chip before the reset */
8814  mmiowb();
8815 
8816  /* Wait for 1ms to empty GLUE and PCI-E core queues,
8817  * PSWHST, GRC and PSWRD Tetris buffer.
8818  */
8819  usleep_range(1000, 1000);
8820 
8821  /* Prepare to chip reset: */
8822  /* MCP */
8823  if (global)
8824  bnx2x_reset_mcp_prep(bp, &val);
8825 
8826  /* PXP */
8827  bnx2x_pxp_prep(bp);
8828  barrier();
8829 
8830  /* reset the chip */
8831  bnx2x_process_kill_chip_reset(bp, global);
8832  barrier();
8833 
8834  /* Recover after reset: */
8835  /* MCP */
8836  if (global && bnx2x_reset_mcp_comp(bp, val))
8837  return -EAGAIN;
8838 
8839  /* TBD: Add resetting the NO_MCP mode DB here */
8840 
8841  /* PXP */
8842  bnx2x_pxp_prep(bp);
8843 
8844  /* Open the gates #2, #3 and #4 */
8845  bnx2x_set_234_gates(bp, false);
8846 
8847  /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8848  * reset state, re-enable attentions. */
8849 
8850  return 0;
8851 }
8852 
8853 int bnx2x_leader_reset(struct bnx2x *bp)
8854 {
8855  int rc = 0;
8856  bool global = bnx2x_reset_is_global(bp);
8857  u32 load_code;
8858 
8859  /* if not going to reset MCP - load "fake" driver to reset HW while
8860  * driver is owner of the HW
8861  */
8862  if (!global && !BP_NOMCP(bp)) {
8863  load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
8865  if (!load_code) {
8866  BNX2X_ERR("MCP response failure, aborting\n");
8867  rc = -EAGAIN;
8868  goto exit_leader_reset;
8869  }
8870  if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
8871  (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
8872  BNX2X_ERR("MCP unexpected resp, aborting\n");
8873  rc = -EAGAIN;
8874  goto exit_leader_reset2;
8875  }
8876  load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
8877  if (!load_code) {
8878  BNX2X_ERR("MCP response failure, aborting\n");
8879  rc = -EAGAIN;
8880  goto exit_leader_reset2;
8881  }
8882  }
8883 
8884  /* Try to recover after the failure */
8885  if (bnx2x_process_kill(bp, global)) {
8886  BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
8887  BP_PATH(bp));
8888  rc = -EAGAIN;
8889  goto exit_leader_reset2;
8890  }
8891 
8892  /*
8893  * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8894  * state.
8895  */
8896  bnx2x_set_reset_done(bp);
8897  if (global)
8898  bnx2x_clear_reset_global(bp);
8899 
8900 exit_leader_reset2:
8901  /* unload "fake driver" if it was loaded */
8902  if (!global && !BP_NOMCP(bp)) {
8905  }
8906 exit_leader_reset:
8907  bp->is_leader = 0;
8909  smp_mb();
8910  return rc;
8911 }
8912 
8913 static void bnx2x_recovery_failed(struct bnx2x *bp)
8914 {
8915  netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8916 
8917  /* Disconnect this device */
8918  netif_device_detach(bp->dev);
8919 
8920  /*
8921  * Block ifup for all function on this engine until "process kill"
8922  * or power cycle.
8923  */
8925 
8926  /* Shut down the power */
8928 
8930 
8931  smp_mb();
8932 }
8933 
8934 /*
8935  * Assumption: runs under rtnl lock. This together with the fact
8936  * that it's called only from bnx2x_sp_rtnl() ensure that it
8937  * will never be called when netif_running(bp->dev) is false.
8938  */
8939 static void bnx2x_parity_recover(struct bnx2x *bp)
8940 {
8941  bool global = false;
8942  u32 error_recovered, error_unrecovered;
8943  bool is_parity;
8944 
8945  DP(NETIF_MSG_HW, "Handling parity\n");
8946  while (1) {
8947  switch (bp->recovery_state) {
8948  case BNX2X_RECOVERY_INIT:
8949  DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
8950  is_parity = bnx2x_chk_parity_attn(bp, &global, false);
8951  WARN_ON(!is_parity);
8952 
8953  /* Try to get a LEADER_LOCK HW lock */
8954  if (bnx2x_trylock_leader_lock(bp)) {
8956  /*
8957  * Check if there is a global attention and if
8958  * there was a global attention, set the global
8959  * reset bit.
8960  */
8961 
8962  if (global)
8964 
8965  bp->is_leader = 1;
8966  }
8967 
8968  /* Stop the driver */
8969  /* If interface has been removed - break */
8970  if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
8971  return;
8972 
8974 
8975  /* Ensure "is_leader", MCP command sequence and
8976  * "recovery_state" update values are seen on other
8977  * CPUs.
8978  */
8979  smp_mb();
8980  break;
8981 
8982  case BNX2X_RECOVERY_WAIT:
8983  DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8984  if (bp->is_leader) {
8985  int other_engine = BP_PATH(bp) ? 0 : 1;
8986  bool other_load_status =
8987  bnx2x_get_load_status(bp, other_engine);
8988  bool load_status =
8989  bnx2x_get_load_status(bp, BP_PATH(bp));
8990  global = bnx2x_reset_is_global(bp);
8991 
8992  /*
8993  * In case of a parity in a global block, let
8994  * the first leader that performs a
8995  * leader_reset() reset the global blocks in
8996  * order to clear global attentions. Otherwise
8997  * the the gates will remain closed for that
8998  * engine.
8999  */
9000  if (load_status ||
9001  (global && other_load_status)) {
9002  /* Wait until all other functions get
9003  * down.
9004  */
9006  HZ/10);
9007  return;
9008  } else {
9009  /* If all other functions got down -
9010  * try to bring the chip back to
9011  * normal. In any case it's an exit
9012  * point for a leader.
9013  */
9014  if (bnx2x_leader_reset(bp)) {
9015  bnx2x_recovery_failed(bp);
9016  return;
9017  }
9018 
9019  /* If we are here, means that the
9020  * leader has succeeded and doesn't
9021  * want to be a leader any more. Try
9022  * to continue as a none-leader.
9023  */
9024  break;
9025  }
9026  } else { /* non-leader */
9027  if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9028  /* Try to get a LEADER_LOCK HW lock as
9029  * long as a former leader may have
9030  * been unloaded by the user or
9031  * released a leadership by another
9032  * reason.
9033  */
9034  if (bnx2x_trylock_leader_lock(bp)) {
9035  /* I'm a leader now! Restart a
9036  * switch case.
9037  */
9038  bp->is_leader = 1;
9039  break;
9040  }
9041 
9043  HZ/10);
9044  return;
9045 
9046  } else {
9047  /*
9048  * If there was a global attention, wait
9049  * for it to be cleared.
9050  */
9051  if (bnx2x_reset_is_global(bp)) {
9053  &bp->sp_rtnl_task,
9054  HZ/10);
9055  return;
9056  }
9057 
9058  error_recovered =
9059  bp->eth_stats.recoverable_error;
9060  error_unrecovered =
9061  bp->eth_stats.unrecoverable_error;
9062  bp->recovery_state =
9064  if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9065  error_unrecovered++;
9066  netdev_err(bp->dev,
9067  "Recovery failed. Power cycle needed\n");
9068  /* Disconnect this device */
9069  netif_device_detach(bp->dev);
9070  /* Shut down the power */
9072  bp, PCI_D3hot);
9073  smp_mb();
9074  } else {
9075  bp->recovery_state =
9077  error_recovered++;
9078  smp_mb();
9079  }
9080  bp->eth_stats.recoverable_error =
9081  error_recovered;
9082  bp->eth_stats.unrecoverable_error =
9083  error_unrecovered;
9084 
9085  return;
9086  }
9087  }
9088  default:
9089  return;
9090  }
9091  }
9092 }
9093 
9094 static int bnx2x_close(struct net_device *dev);
9095 
9096 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9097  * scheduled on a general queue in order to prevent a dead lock.
9098  */
9099 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9100 {
9101  struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9102 
9103  rtnl_lock();
9104 
9105  if (!netif_running(bp->dev))
9106  goto sp_rtnl_exit;
9107 
9108  /* if stop on error is defined no recovery flows should be executed */
9109 #ifdef BNX2X_STOP_ON_ERROR
9110  BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9111  "you will need to reboot when done\n");
9112  goto sp_rtnl_not_reset;
9113 #endif
9114 
9116  /*
9117  * Clear all pending SP commands as we are going to reset the
9118  * function anyway.
9119  */
9120  bp->sp_rtnl_state = 0;
9121  smp_mb();
9122 
9123  bnx2x_parity_recover(bp);
9124 
9125  goto sp_rtnl_exit;
9126  }
9127 
9129  /*
9130  * Clear all pending SP commands as we are going to reset the
9131  * function anyway.
9132  */
9133  bp->sp_rtnl_state = 0;
9134  smp_mb();
9135 
9136  bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9138 
9139  goto sp_rtnl_exit;
9140  }
9141 #ifdef BNX2X_STOP_ON_ERROR
9142 sp_rtnl_not_reset:
9143 #endif
9145  bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9147  bnx2x_after_function_update(bp);
9148  /*
9149  * in case of fan failure we need to reset id if the "stop on error"
9150  * debug flag is set, since we trying to prevent permanent overheating
9151  * damage
9152  */
9154  DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9155  netif_device_detach(bp->dev);
9156  bnx2x_close(bp->dev);
9157  }
9158 
9159 sp_rtnl_exit:
9160  rtnl_unlock();
9161 }
9162 
9163 /* end of nic load/unload */
9164 
9165 static void bnx2x_period_task(struct work_struct *work)
9166 {
9167  struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9168 
9169  if (!netif_running(bp->dev))
9170  goto period_task_exit;
9171 
9172  if (CHIP_REV_IS_SLOW(bp)) {
9173  BNX2X_ERR("period task called on emulation, ignoring\n");
9174  goto period_task_exit;
9175  }
9176 
9178  /*
9179  * The barrier is needed to ensure the ordering between the writing to
9180  * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9181  * the reading here.
9182  */
9183  smp_mb();
9184  if (bp->port.pmf) {
9186 
9187  /* Re-queue task in 1 sec */
9188  queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9189  }
9190 
9192 period_task_exit:
9193  return;
9194 }
9195 
9196 /*
9197  * Init service functions
9198  */
9199 
9200 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9201 {
9203  u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9204  return base + (BP_ABS_FUNC(bp)) * stride;
9205 }
9206 
9207 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
9208 {
9209  u32 reg = bnx2x_get_pretend_reg(bp);
9210 
9211  /* Flush all outstanding writes */
9212  mmiowb();
9213 
9214  /* Pretend to be function 0 */
9215  REG_WR(bp, reg, 0);
9216  REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
9217 
9218  /* From now we are in the "like-E1" mode */
9219  bnx2x_int_disable(bp);
9220 
9221  /* Flush all outstanding writes */
9222  mmiowb();
9223 
9224  /* Restore the original function */
9225  REG_WR(bp, reg, BP_ABS_FUNC(bp));
9226  REG_RD(bp, reg);
9227 }
9228 
9229 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
9230 {
9231  if (CHIP_IS_E1(bp))
9232  bnx2x_int_disable(bp);
9233  else
9234  bnx2x_undi_int_disable_e1h(bp);
9235 }
9236 
9237 static void __devinit bnx2x_prev_unload_close_mac(struct bnx2x *bp)
9238 {
9239  u32 val, base_addr, offset, mask, reset_reg;
9240  bool mac_stopped = false;
9241  u8 port = BP_PORT(bp);
9242 
9243  reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9244 
9245  if (!CHIP_IS_E3(bp)) {
9246  val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9248  if ((mask & reset_reg) && val) {
9249  u32 wb_data[2];
9250  BNX2X_DEV_INFO("Disable bmac Rx\n");
9251  base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9255 
9256  /*
9257  * use rd/wr since we cannot use dmae. This is safe
9258  * since MCP won't access the bus due to the request
9259  * to unload, and no function on the path can be
9260  * loaded at this time.
9261  */
9262  wb_data[0] = REG_RD(bp, base_addr + offset);
9263  wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9264  wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9265  REG_WR(bp, base_addr + offset, wb_data[0]);
9266  REG_WR(bp, base_addr + offset + 0x4, wb_data[1]);
9267 
9268  }
9269  BNX2X_DEV_INFO("Disable emac Rx\n");
9270  REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0);
9271 
9272  mac_stopped = true;
9273  } else {
9274  if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9275  BNX2X_DEV_INFO("Disable xmac Rx\n");
9276  base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9277  val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9278  REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9279  val & ~(1 << 1));
9280  REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9281  val | (1 << 1));
9282  REG_WR(bp, base_addr + XMAC_REG_CTRL, 0);
9283  mac_stopped = true;
9284  }
9286  if (mask & reset_reg) {
9287  BNX2X_DEV_INFO("Disable umac Rx\n");
9288  base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9289  REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0);
9290  mac_stopped = true;
9291  }
9292  }
9293 
9294  if (mac_stopped)
9295  msleep(20);
9296 
9297 }
9298 
9299 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9300 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9301 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9302 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9303 
9304 static void __devinit bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port,
9305  u8 inc)
9306 {
9307  u16 rcq, bd;
9308  u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9309 
9310  rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9311  bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9312 
9313  tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9314  REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9315 
9316  BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9317  port, bd, rcq);
9318 }
9319 
9320 static int __devinit bnx2x_prev_mcp_done(struct bnx2x *bp)
9321 {
9324  if (!rc) {
9325  BNX2X_ERR("MCP response failure, aborting\n");
9326  return -EBUSY;
9327  }
9328 
9329  return 0;
9330 }
9331 
9332 static bool __devinit bnx2x_prev_is_path_marked(struct bnx2x *bp)
9333 {
9334  struct bnx2x_prev_path_list *tmp_list;
9335  int rc = false;
9336 
9337  if (down_trylock(&bnx2x_prev_sem))
9338  return false;
9339 
9340  list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
9341  if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9342  bp->pdev->bus->number == tmp_list->bus &&
9343  BP_PATH(bp) == tmp_list->path) {
9344  rc = true;
9345  BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9346  BP_PATH(bp));
9347  break;
9348  }
9349  }
9350 
9351  up(&bnx2x_prev_sem);
9352 
9353  return rc;
9354 }
9355 
9356 static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp)
9357 {
9358  struct bnx2x_prev_path_list *tmp_list;
9359  int rc;
9360 
9361  tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9362  if (!tmp_list) {
9363  BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9364  return -ENOMEM;
9365  }
9366 
9367  tmp_list->bus = bp->pdev->bus->number;
9368  tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9369  tmp_list->path = BP_PATH(bp);
9370 
9371  rc = down_interruptible(&bnx2x_prev_sem);
9372  if (rc) {
9373  BNX2X_ERR("Received %d when tried to take lock\n", rc);
9374  kfree(tmp_list);
9375  } else {
9376  BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
9377  BP_PATH(bp));
9378  list_add(&tmp_list->list, &bnx2x_prev_list);
9379  up(&bnx2x_prev_sem);
9380  }
9381 
9382  return rc;
9383 }
9384 
9385 static int __devinit bnx2x_do_flr(struct bnx2x *bp)
9386 {
9387  int i;
9388  u16 status;
9389  struct pci_dev *dev = bp->pdev;
9390 
9391 
9392  if (CHIP_IS_E1x(bp)) {
9393  BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9394  return -EINVAL;
9395  }
9396 
9397  /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9398  if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9399  BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9400  bp->common.bc_ver);
9401  return -EINVAL;
9402  }
9403 
9404  /* Wait for Transaction Pending bit clean */
9405  for (i = 0; i < 4; i++) {
9406  if (i)
9407  msleep((1 << (i - 1)) * 100);
9408 
9410  if (!(status & PCI_EXP_DEVSTA_TRPND))
9411  goto clear;
9412  }
9413 
9414  dev_err(&dev->dev,
9415  "transaction is not cleared; proceeding with reset anyway\n");
9416 
9417 clear:
9418 
9419  BNX2X_DEV_INFO("Initiating FLR\n");
9421 
9422  return 0;
9423 }
9424 
9425 static int __devinit bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9426 {
9427  int rc;
9428 
9429  BNX2X_DEV_INFO("Uncommon unload Flow\n");
9430 
9431  /* Test if previous unload process was already finished for this path */
9432  if (bnx2x_prev_is_path_marked(bp))
9433  return bnx2x_prev_mcp_done(bp);
9434 
9435  /* If function has FLR capabilities, and existing FW version matches
9436  * the one required, then FLR will be sufficient to clean any residue
9437  * left by previous driver
9438  */
9439  rc = bnx2x_test_firmware_version(bp, false);
9440 
9441  if (!rc) {
9442  /* fw version is good */
9443  BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9444  rc = bnx2x_do_flr(bp);
9445  }
9446 
9447  if (!rc) {
9448  /* FLR was performed */
9449  BNX2X_DEV_INFO("FLR successful\n");
9450  return 0;
9451  }
9452 
9453  BNX2X_DEV_INFO("Could not FLR\n");
9454 
9455  /* Close the MCP request, return failure*/
9456  rc = bnx2x_prev_mcp_done(bp);
9457  if (!rc)
9459 
9460  return rc;
9461 }
9462 
9463 static int __devinit bnx2x_prev_unload_common(struct bnx2x *bp)
9464 {
9465  u32 reset_reg, tmp_reg = 0, rc;
9466  /* It is possible a previous function received 'common' answer,
9467  * but hasn't loaded yet, therefore creating a scenario of
9468  * multiple functions receiving 'common' on the same path.
9469  */
9470  BNX2X_DEV_INFO("Common unload Flow\n");
9471 
9472  if (bnx2x_prev_is_path_marked(bp))
9473  return bnx2x_prev_mcp_done(bp);
9474 
9475  reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9476 
9477  /* Reset should be performed after BRB is emptied */
9478  if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9479  u32 timer_count = 1000;
9480  bool prev_undi = false;
9481 
9482  /* Close the MAC Rx to prevent BRB from filling up */
9483  bnx2x_prev_unload_close_mac(bp);
9484 
9485  /* Check if the UNDI driver was previously loaded
9486  * UNDI driver initializes CID offset for normal bell to 0x7
9487  */
9488  reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9489  if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9490  tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9491  if (tmp_reg == 0x7) {
9492  BNX2X_DEV_INFO("UNDI previously loaded\n");
9493  prev_undi = true;
9494  /* clear the UNDI indication */
9496  }
9497  }
9498  /* wait until BRB is empty */
9499  tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9500  while (timer_count) {
9501  u32 prev_brb = tmp_reg;
9502 
9503  tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9504  if (!tmp_reg)
9505  break;
9506 
9507  BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
9508 
9509  /* reset timer as long as BRB actually gets emptied */
9510  if (prev_brb > tmp_reg)
9511  timer_count = 1000;
9512  else
9513  timer_count--;
9514 
9515  /* If UNDI resides in memory, manually increment it */
9516  if (prev_undi)
9517  bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
9518 
9519  udelay(10);
9520  }
9521 
9522  if (!timer_count)
9523  BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9524 
9525  }
9526 
9527  /* No packets are in the pipeline, path is ready for reset */
9528  bnx2x_reset_common(bp);
9529 
9530  rc = bnx2x_prev_mark_path(bp);
9531  if (rc) {
9532  bnx2x_prev_mcp_done(bp);
9533  return rc;
9534  }
9535 
9536  return bnx2x_prev_mcp_done(bp);
9537 }
9538 
9539 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
9540  * and boot began, or when kdump kernel was loaded. Either case would invalidate
9541  * the addresses of the transaction, resulting in was-error bit set in the pci
9542  * causing all hw-to-host pcie transactions to timeout. If this happened we want
9543  * to clear the interrupt which detected this from the pglueb and the was done
9544  * bit
9545  */
9546 static void __devinit bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
9547 {
9548  if (!CHIP_IS_E1x(bp)) {
9550  if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9551  BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing");
9553  1 << BP_FUNC(bp));
9554  }
9555  }
9556 }
9557 
9558 static int __devinit bnx2x_prev_unload(struct bnx2x *bp)
9559 {
9560  int time_counter = 10;
9561  u32 rc, fw, hw_lock_reg, hw_lock_val;
9562  BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
9563 
9564  /* clear hw from errors which may have resulted from an interrupted
9565  * dmae transaction.
9566  */
9567  bnx2x_prev_interrupted_dmae(bp);
9568 
9569  /* Release previously held locks */
9570  hw_lock_reg = (BP_FUNC(bp) <= 5) ?
9571  (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
9572  (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
9573 
9574  hw_lock_val = (REG_RD(bp, hw_lock_reg));
9575  if (hw_lock_val) {
9576  if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9577  BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
9580  }
9581 
9582  BNX2X_DEV_INFO("Release Previously held hw lock\n");
9583  REG_WR(bp, hw_lock_reg, 0xffffffff);
9584  } else
9585  BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
9586 
9588  BNX2X_DEV_INFO("Release previously held alr\n");
9590  }
9591 
9592 
9593  do {
9594  /* Lock MCP using an unload request */
9596  if (!fw) {
9597  BNX2X_ERR("MCP response failure, aborting\n");
9598  rc = -EBUSY;
9599  break;
9600  }
9601 
9602  if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9603  rc = bnx2x_prev_unload_common(bp);
9604  break;
9605  }
9606 
9607  /* non-common reply from MCP night require looping */
9608  rc = bnx2x_prev_unload_uncommon(bp);
9609  if (rc != BNX2X_PREV_WAIT_NEEDED)
9610  break;
9611 
9612  msleep(20);
9613  } while (--time_counter);
9614 
9615  if (!time_counter || rc) {
9616  BNX2X_ERR("Failed unloading previous driver, aborting\n");
9617  rc = -EBUSY;
9618  }
9619 
9620  BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
9621 
9622  return rc;
9623 }
9624 
9625 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
9626 {
9627  u32 val, val2, val3, val4, id, boot_mode;
9628  u16 pmc;
9629 
9630  /* Get the chip revision id and number. */
9631  /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
9632  val = REG_RD(bp, MISC_REG_CHIP_NUM);
9633  id = ((val & 0xffff) << 16);
9634  val = REG_RD(bp, MISC_REG_CHIP_REV);
9635  id |= ((val & 0xf) << 12);
9636  val = REG_RD(bp, MISC_REG_CHIP_METAL);
9637  id |= ((val & 0xff) << 4);
9638  val = REG_RD(bp, MISC_REG_BOND_ID);
9639  id |= (val & 0xf);
9640  bp->common.chip_id = id;
9641 
9642  /* force 57811 according to MISC register */
9644  if (CHIP_IS_57810(bp))
9645  bp->common.chip_id = (CHIP_NUM_57811 << 16) |
9646  (bp->common.chip_id & 0x0000FFFF);
9647  else if (CHIP_IS_57810_MF(bp))
9648  bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
9649  (bp->common.chip_id & 0x0000FFFF);
9650  bp->common.chip_id |= 0x1;
9651  }
9652 
9653  /* Set doorbell size */
9654  bp->db_size = (1 << BNX2X_DB_SHIFT);
9655 
9656  if (!CHIP_IS_E1x(bp)) {
9658  if ((val & 1) == 0)
9659  val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
9660  else
9661  val = (val >> 1) & 1;
9662  BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
9663  "2_PORT_MODE");
9664  bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
9666 
9667  if (CHIP_MODE_IS_4_PORT(bp))
9668  bp->pfid = (bp->pf_num >> 1); /* 0..3 */
9669  else
9670  bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
9671  } else {
9672  bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
9673  bp->pfid = bp->pf_num; /* 0..7 */
9674  }
9675 
9676  BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
9677 
9678  bp->link_params.chip_id = bp->common.chip_id;
9679  BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
9680 
9681  val = (REG_RD(bp, 0x2874) & 0x55);
9682  if ((bp->common.chip_id & 0x1) ||
9683  (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
9684  bp->flags |= ONE_PORT_FLAG;
9685  BNX2X_DEV_INFO("single port device\n");
9686  }
9687 
9688  val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
9689  bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
9690  (val & MCPR_NVM_CFG4_FLASH_SIZE));
9691  BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
9692  bp->common.flash_size, bp->common.flash_size);
9693 
9694  bnx2x_init_shmem(bp);
9695 
9696 
9697 
9698  bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
9701 
9702  bp->link_params.shmem_base = bp->common.shmem_base;
9703  bp->link_params.shmem2_base = bp->common.shmem2_base;
9704  BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
9705  bp->common.shmem_base, bp->common.shmem2_base);
9706 
9707  if (!bp->common.shmem_base) {
9708  BNX2X_DEV_INFO("MCP not active\n");
9709  bp->flags |= NO_MCP_FLAG;
9710  return;
9711  }
9712 
9713  bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
9714  BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
9715 
9716  bp->link_params.hw_led_mode = ((bp->common.hw_config &
9719 
9720  bp->link_params.feature_config_flags = 0;
9721  val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
9723  bp->link_params.feature_config_flags |=
9725  else
9726  bp->link_params.feature_config_flags &=
9728 
9729  val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
9730  bp->common.bc_ver = val;
9731  BNX2X_DEV_INFO("bc_ver %X\n", val);
9732  if (val < BNX2X_BC_VER) {
9733  /* for now only warn
9734  * later we might need to enforce this */
9735  BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
9736  BNX2X_BC_VER, val);
9737  }
9738  bp->link_params.feature_config_flags |=
9741 
9742  bp->link_params.feature_config_flags |=
9745  bp->link_params.feature_config_flags |=
9748  bp->link_params.feature_config_flags |=
9751  bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
9753 
9754  bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
9756 
9757  bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
9759  boot_mode = SHMEM_RD(bp,
9760  dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
9762  switch (boot_mode) {
9764  bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
9765  break;
9767  bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
9768  break;
9770  bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
9771  break;
9773  bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
9774  break;
9775  }
9776 
9777  pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
9778  bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
9779 
9780  BNX2X_DEV_INFO("%sWoL capable\n",
9781  (bp->flags & NO_WOL_FLAG) ? "not " : "");
9782 
9783  val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
9784  val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
9785  val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
9786  val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
9787 
9788  dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
9789  val, val2, val3, val4);
9790 }
9791 
9792 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
9793 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
9794 
9795 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
9796 {
9797  int pfid = BP_FUNC(bp);
9798  int igu_sb_id;
9799  u32 val;
9800  u8 fid, igu_sb_cnt = 0;
9801 
9802  bp->igu_base_sb = 0xff;
9803  if (CHIP_INT_MODE_IS_BC(bp)) {
9804  int vn = BP_VN(bp);
9805  igu_sb_cnt = bp->igu_sb_cnt;
9806  bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
9807  FP_SB_MAX_E1x;
9808 
9810  (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
9811 
9812  return;
9813  }
9814 
9815  /* IGU in normal mode - read CAM */
9816  for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
9817  igu_sb_id++) {
9818  val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
9819  if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
9820  continue;
9821  fid = IGU_FID(val);
9822  if ((fid & IGU_FID_ENCODE_IS_PF)) {
9823  if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
9824  continue;
9825  if (IGU_VEC(val) == 0)
9826  /* default status block */
9827  bp->igu_dsb_id = igu_sb_id;
9828  else {
9829  if (bp->igu_base_sb == 0xff)
9830  bp->igu_base_sb = igu_sb_id;
9831  igu_sb_cnt++;
9832  }
9833  }
9834  }
9835 
9836 #ifdef CONFIG_PCI_MSI
9837  /* Due to new PF resource allocation by MFW T7.4 and above, it's
9838  * optional that number of CAM entries will not be equal to the value
9839  * advertised in PCI.
9840  * Driver should use the minimal value of both as the actual status
9841  * block count
9842  */
9843  bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
9844 #endif
9845 
9846  if (igu_sb_cnt == 0)
9847  BNX2X_ERR("CAM configuration error\n");
9848 }
9849 
9850 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
9851  u32 switch_cfg)
9852 {
9853  int cfg_size = 0, idx, port = BP_PORT(bp);
9854 
9855  /* Aggregation of supported attributes of all external phys */
9856  bp->port.supported[0] = 0;
9857  bp->port.supported[1] = 0;
9858  switch (bp->link_params.num_phys) {
9859  case 1:
9860  bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
9861  cfg_size = 1;
9862  break;
9863  case 2:
9864  bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
9865  cfg_size = 1;
9866  break;
9867  case 3:
9868  if (bp->link_params.multi_phy_config &
9870  bp->port.supported[1] =
9871  bp->link_params.phy[EXT_PHY1].supported;
9872  bp->port.supported[0] =
9873  bp->link_params.phy[EXT_PHY2].supported;
9874  } else {
9875  bp->port.supported[0] =
9876  bp->link_params.phy[EXT_PHY1].supported;
9877  bp->port.supported[1] =
9878  bp->link_params.phy[EXT_PHY2].supported;
9879  }
9880  cfg_size = 2;
9881  break;
9882  }
9883 
9884  if (!(bp->port.supported[0] || bp->port.supported[1])) {
9885  BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
9886  SHMEM_RD(bp,
9887  dev_info.port_hw_config[port].external_phy_config),
9888  SHMEM_RD(bp,
9889  dev_info.port_hw_config[port].external_phy_config2));
9890  return;
9891  }
9892 
9893  if (CHIP_IS_E3(bp))
9894  bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
9895  else {
9896  switch (switch_cfg) {
9897  case SWITCH_CFG_1G:
9898  bp->port.phy_addr = REG_RD(
9899  bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
9900  break;
9901  case SWITCH_CFG_10G:
9902  bp->port.phy_addr = REG_RD(
9903  bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
9904  break;
9905  default:
9906  BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
9907  bp->port.link_config[0]);
9908  return;
9909  }
9910  }
9911  BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
9912  /* mask what we support according to speed_cap_mask per configuration */
9913  for (idx = 0; idx < cfg_size; idx++) {
9914  if (!(bp->link_params.speed_cap_mask[idx] &
9916  bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
9917 
9918  if (!(bp->link_params.speed_cap_mask[idx] &
9920  bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
9921 
9922  if (!(bp->link_params.speed_cap_mask[idx] &
9924  bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
9925 
9926  if (!(bp->link_params.speed_cap_mask[idx] &
9928  bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
9929 
9930  if (!(bp->link_params.speed_cap_mask[idx] &
9932  bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
9934 
9935  if (!(bp->link_params.speed_cap_mask[idx] &
9937  bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
9938 
9939  if (!(bp->link_params.speed_cap_mask[idx] &
9941  bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
9942 
9943  }
9944 
9945  BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
9946  bp->port.supported[1]);
9947 }
9948 
9949 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
9950 {
9951  u32 link_config, idx, cfg_size = 0;
9952  bp->port.advertising[0] = 0;
9953  bp->port.advertising[1] = 0;
9954  switch (bp->link_params.num_phys) {
9955  case 1:
9956  case 2:
9957  cfg_size = 1;
9958  break;
9959  case 3:
9960  cfg_size = 2;
9961  break;
9962  }
9963  for (idx = 0; idx < cfg_size; idx++) {
9964  bp->link_params.req_duplex[idx] = DUPLEX_FULL;
9965  link_config = bp->port.link_config[idx];
9966  switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
9968  if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
9969  bp->link_params.req_line_speed[idx] =
9971  bp->port.advertising[idx] |=
9972  bp->port.supported[idx];
9973  if (bp->link_params.phy[EXT_PHY1].type ==
9975  bp->port.advertising[idx] |=
9978  } else {
9979  /* force 10G, no AN */
9980  bp->link_params.req_line_speed[idx] =
9981  SPEED_10000;
9982  bp->port.advertising[idx] |=
9985  continue;
9986  }
9987  break;
9988 
9990  if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
9991  bp->link_params.req_line_speed[idx] =
9992  SPEED_10;
9993  bp->port.advertising[idx] |=
9995  ADVERTISED_TP);
9996  } else {
9997  BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9998  link_config,
9999  bp->link_params.speed_cap_mask[idx]);
10000  return;
10001  }
10002  break;
10003 
10005  if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10006  bp->link_params.req_line_speed[idx] =
10007  SPEED_10;
10008  bp->link_params.req_duplex[idx] =
10009  DUPLEX_HALF;
10010  bp->port.advertising[idx] |=
10012  ADVERTISED_TP);
10013  } else {
10014  BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10015  link_config,
10016  bp->link_params.speed_cap_mask[idx]);
10017  return;
10018  }
10019  break;
10020 
10022  if (bp->port.supported[idx] &
10024  bp->link_params.req_line_speed[idx] =
10025  SPEED_100;
10026  bp->port.advertising[idx] |=
10028  ADVERTISED_TP);
10029  } else {
10030  BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10031  link_config,
10032  bp->link_params.speed_cap_mask[idx]);
10033  return;
10034  }
10035  break;
10036 
10038  if (bp->port.supported[idx] &
10040  bp->link_params.req_line_speed[idx] =
10041  SPEED_100;
10042  bp->link_params.req_duplex[idx] =
10043  DUPLEX_HALF;
10044  bp->port.advertising[idx] |=
10046  ADVERTISED_TP);
10047  } else {
10048  BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10049  link_config,
10050  bp->link_params.speed_cap_mask[idx]);
10051  return;
10052  }
10053  break;
10054 
10056  if (bp->port.supported[idx] &
10058  bp->link_params.req_line_speed[idx] =
10059  SPEED_1000;
10060  bp->port.advertising[idx] |=
10062  ADVERTISED_TP);
10063  } else {
10064  BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10065  link_config,
10066  bp->link_params.speed_cap_mask[idx]);
10067  return;
10068  }
10069  break;
10070 
10072  if (bp->port.supported[idx] &
10074  bp->link_params.req_line_speed[idx] =
10075  SPEED_2500;
10076  bp->port.advertising[idx] |=
10078  ADVERTISED_TP);
10079  } else {
10080  BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10081  link_config,
10082  bp->link_params.speed_cap_mask[idx]);
10083  return;
10084  }
10085  break;
10086 
10088  if (bp->port.supported[idx] &
10090  bp->link_params.req_line_speed[idx] =
10091  SPEED_10000;
10092  bp->port.advertising[idx] |=
10095  } else {
10096  BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10097  link_config,
10098  bp->link_params.speed_cap_mask[idx]);
10099  return;
10100  }
10101  break;
10103  bp->link_params.req_line_speed[idx] = SPEED_20000;
10104 
10105  break;
10106  default:
10107  BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10108  link_config);
10109  bp->link_params.req_line_speed[idx] =
10111  bp->port.advertising[idx] =
10112  bp->port.supported[idx];
10113  break;
10114  }
10115 
10116  bp->link_params.req_flow_ctrl[idx] = (link_config &
10118  if ((bp->link_params.req_flow_ctrl[idx] ==
10120  !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
10121  bp->link_params.req_flow_ctrl[idx] =
10123  }
10124 
10125  BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10126  bp->link_params.req_line_speed[idx],
10127  bp->link_params.req_duplex[idx],
10128  bp->link_params.req_flow_ctrl[idx],
10129  bp->port.advertising[idx]);
10130  }
10131 }
10132 
10133 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10134 {
10135  mac_hi = cpu_to_be16(mac_hi);
10136  mac_lo = cpu_to_be32(mac_lo);
10137  memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
10138  memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
10139 }
10140 
10141 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
10142 {
10143  int port = BP_PORT(bp);
10144  u32 config;
10145  u32 ext_phy_type, ext_phy_config, eee_mode;
10146 
10147  bp->link_params.bp = bp;
10148  bp->link_params.port = port;
10149 
10150  bp->link_params.lane_config =
10151  SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10152 
10153  bp->link_params.speed_cap_mask[0] =
10154  SHMEM_RD(bp,
10155  dev_info.port_hw_config[port].speed_capability_mask);
10156  bp->link_params.speed_cap_mask[1] =
10157  SHMEM_RD(bp,
10158  dev_info.port_hw_config[port].speed_capability_mask2);
10159  bp->port.link_config[0] =
10160  SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10161 
10162  bp->port.link_config[1] =
10163  SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10164 
10165  bp->link_params.multi_phy_config =
10166  SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10167  /* If the device is capable of WoL, set the default state according
10168  * to the HW
10169  */
10170  config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10171  bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10172  (config & PORT_FEATURE_WOL_ENABLED));
10173 
10174  BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
10175  bp->link_params.lane_config,
10176  bp->link_params.speed_cap_mask[0],
10177  bp->port.link_config[0]);
10178 
10179  bp->link_params.switch_cfg = (bp->port.link_config[0] &
10182  bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10183 
10184  bnx2x_link_settings_requested(bp);
10185 
10186  /*
10187  * If connected directly, work with the internal PHY, otherwise, work
10188  * with the external PHY
10189  */
10190  ext_phy_config =
10191  SHMEM_RD(bp,
10192  dev_info.port_hw_config[port].external_phy_config);
10193  ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10194  if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10195  bp->mdio.prtad = bp->port.phy_addr;
10196 
10197  else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10198  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10199  bp->mdio.prtad =
10200  XGXS_EXT_PHY_ADDR(ext_phy_config);
10201 
10202  /*
10203  * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
10204  * In MF mode, it is set to cover self test cases
10205  */
10206  if (IS_MF(bp))
10207  bp->port.need_hw_lock = 1;
10208  else
10209  bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
10210  bp->common.shmem_base,
10211  bp->common.shmem2_base);
10212 
10213  /* Configure link feature according to nvram value */
10214  eee_mode = (((SHMEM_RD(bp, dev_info.
10215  port_feature_config[port].eee_power_mode)) &
10218  if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10219  bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10222  } else {
10223  bp->link_params.eee_mode = 0;
10224  }
10225 }
10226 
10227 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10228 {
10229  u32 no_flags = NO_ISCSI_FLAG;
10230 #ifdef BCM_CNIC
10231  int port = BP_PORT(bp);
10232 
10233  u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10234  drv_lic_key[port].max_iscsi_conn);
10235 
10236  /* Get the number of maximum allowed iSCSI connections */
10237  bp->cnic_eth_dev.max_iscsi_conn =
10238  (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10240 
10241  BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10242  bp->cnic_eth_dev.max_iscsi_conn);
10243 
10244  /*
10245  * If maximum allowed number of connections is zero -
10246  * disable the feature.
10247  */
10248  if (!bp->cnic_eth_dev.max_iscsi_conn)
10249  bp->flags |= no_flags;
10250 #else
10251  bp->flags |= no_flags;
10252 #endif
10253 }
10254 
10255 #ifdef BCM_CNIC
10256 static void __devinit bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10257 {
10258  /* Port info */
10259  bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10260  MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10261  bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10262  MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10263 
10264  /* Node info */
10265  bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10266  MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10267  bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10268  MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10269 }
10270 #endif
10271 static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp)
10272 {
10273 #ifdef BCM_CNIC
10274  int port = BP_PORT(bp);
10275  int func = BP_ABS_FUNC(bp);
10276 
10277  u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10278  drv_lic_key[port].max_fcoe_conn);
10279 
10280  /* Get the number of maximum allowed FCoE connections */
10281  bp->cnic_eth_dev.max_fcoe_conn =
10282  (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10284 
10285  /* Read the WWN: */
10286  if (!IS_MF(bp)) {
10287  /* Port info */
10288  bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10289  SHMEM_RD(bp,
10290  dev_info.port_hw_config[port].
10291  fcoe_wwn_port_name_upper);
10292  bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10293  SHMEM_RD(bp,
10294  dev_info.port_hw_config[port].
10295  fcoe_wwn_port_name_lower);
10296 
10297  /* Node info */
10298  bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10299  SHMEM_RD(bp,
10300  dev_info.port_hw_config[port].
10301  fcoe_wwn_node_name_upper);
10302  bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10303  SHMEM_RD(bp,
10304  dev_info.port_hw_config[port].
10305  fcoe_wwn_node_name_lower);
10306  } else if (!IS_MF_SD(bp)) {
10307  /*
10308  * Read the WWN info only if the FCoE feature is enabled for
10309  * this function.
10310  */
10311  if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
10312  bnx2x_get_ext_wwn_info(bp, func);
10313 
10314  } else if (IS_MF_FCOE_SD(bp))
10315  bnx2x_get_ext_wwn_info(bp, func);
10316 
10317  BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10318 
10319  /*
10320  * If maximum allowed number of connections is zero -
10321  * disable the feature.
10322  */
10323  if (!bp->cnic_eth_dev.max_fcoe_conn)
10324  bp->flags |= NO_FCOE_FLAG;
10325 #else
10326  bp->flags |= NO_FCOE_FLAG;
10327 #endif
10328 }
10329 
10330 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
10331 {
10332  /*
10333  * iSCSI may be dynamically disabled but reading
10334  * info here we will decrease memory usage by driver
10335  * if the feature is disabled for good
10336  */
10338  bnx2x_get_fcoe_info(bp);
10339 }
10340 
10341 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
10342 {
10343  u32 val, val2;
10344  int func = BP_ABS_FUNC(bp);
10345  int port = BP_PORT(bp);
10346 #ifdef BCM_CNIC
10347  u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10348  u8 *fip_mac = bp->fip_mac;
10349 #endif
10350 
10351  /* Zero primary MAC configuration */
10352  memset(bp->dev->dev_addr, 0, ETH_ALEN);
10353 
10354  if (BP_NOMCP(bp)) {
10355  BNX2X_ERROR("warning: random MAC workaround active\n");
10356  eth_hw_addr_random(bp->dev);
10357  } else if (IS_MF(bp)) {
10358  val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10359  val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10360  if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10362  bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10363 
10364 #ifdef BCM_CNIC
10365  /*
10366  * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10367  * FCoE MAC then the appropriate feature should be disabled.
10368  *
10369  * In non SD mode features configuration comes from
10370  * struct func_ext_config.
10371  */
10372  if (!IS_MF_SD(bp)) {
10373  u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10375  val2 = MF_CFG_RD(bp, func_ext_config[func].
10376  iscsi_mac_addr_upper);
10377  val = MF_CFG_RD(bp, func_ext_config[func].
10378  iscsi_mac_addr_lower);
10379  bnx2x_set_mac_buf(iscsi_mac, val, val2);
10380  BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
10381  iscsi_mac);
10382  } else
10384 
10386  val2 = MF_CFG_RD(bp, func_ext_config[func].
10387  fcoe_mac_addr_upper);
10388  val = MF_CFG_RD(bp, func_ext_config[func].
10389  fcoe_mac_addr_lower);
10390  bnx2x_set_mac_buf(fip_mac, val, val2);
10391  BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n",
10392  fip_mac);
10393 
10394  } else
10395  bp->flags |= NO_FCOE_FLAG;
10396 
10397  bp->mf_ext_config = cfg;
10398 
10399  } else { /* SD MODE */
10400  if (IS_MF_STORAGE_SD(bp)) {
10401  if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10402  /* use primary mac as iscsi mac */
10403  memcpy(iscsi_mac, bp->dev->dev_addr,
10404  ETH_ALEN);
10405 
10406  BNX2X_DEV_INFO("SD ISCSI MODE\n");
10407  BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
10408  iscsi_mac);
10409  } else { /* FCoE */
10410  memcpy(fip_mac, bp->dev->dev_addr,
10411  ETH_ALEN);
10412  BNX2X_DEV_INFO("SD FCoE MODE\n");
10413  BNX2X_DEV_INFO("Read FIP MAC: %pM\n",
10414  fip_mac);
10415  }
10416  /* Zero primary MAC configuration */
10417  memset(bp->dev->dev_addr, 0, ETH_ALEN);
10418  }
10419  }
10420 
10421  if (IS_MF_FCOE_AFEX(bp))
10422  /* use FIP MAC as primary MAC */
10423  memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10424 
10425 #endif
10426  } else {
10427  /* in SF read MACs from port configuration */
10428  val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10429  val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10430  bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10431 
10432 #ifdef BCM_CNIC
10433  val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10434  iscsi_mac_upper);
10435  val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10436  iscsi_mac_lower);
10437  bnx2x_set_mac_buf(iscsi_mac, val, val2);
10438 
10439  val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10440  fcoe_fip_mac_upper);
10441  val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10442  fcoe_fip_mac_lower);
10443  bnx2x_set_mac_buf(fip_mac, val, val2);
10444 #endif
10445  }
10446 
10447  memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10448  memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
10449 
10450 #ifdef BCM_CNIC
10451  /* Disable iSCSI if MAC configuration is
10452  * invalid.
10453  */
10454  if (!is_valid_ether_addr(iscsi_mac)) {
10455  bp->flags |= NO_ISCSI_FLAG;
10456  memset(iscsi_mac, 0, ETH_ALEN);
10457  }
10458 
10459  /* Disable FCoE if MAC configuration is
10460  * invalid.
10461  */
10462  if (!is_valid_ether_addr(fip_mac)) {
10463  bp->flags |= NO_FCOE_FLAG;
10464  memset(bp->fip_mac, 0, ETH_ALEN);
10465  }
10466 #endif
10467 
10468  if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
10469  dev_err(&bp->pdev->dev,
10470  "bad Ethernet MAC address configuration: %pM\n"
10471  "change it manually before bringing up the appropriate network interface\n",
10472  bp->dev->dev_addr);
10473 
10474 
10475 }
10476 
10477 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
10478 {
10479  int /*abs*/func = BP_ABS_FUNC(bp);
10480  int vn;
10481  u32 val = 0;
10482  int rc = 0;
10483 
10484  bnx2x_get_common_hwinfo(bp);
10485 
10486  /*
10487  * initialize IGU parameters
10488  */
10489  if (CHIP_IS_E1x(bp)) {
10490  bp->common.int_block = INT_BLOCK_HC;
10491 
10492  bp->igu_dsb_id = DEF_SB_IGU_ID;
10493  bp->igu_base_sb = 0;
10494  } else {
10495  bp->common.int_block = INT_BLOCK_IGU;
10496 
10497  /* do not allow device reset during IGU info preocessing */
10499 
10501 
10503  int tout = 5000;
10504 
10505  BNX2X_DEV_INFO("FORCING Normal Mode\n");
10506 
10509  REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
10510 
10511  while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10512  tout--;
10513  usleep_range(1000, 1000);
10514  }
10515 
10516  if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10517  dev_err(&bp->pdev->dev,
10518  "FORCING Normal Mode failed!!!\n");
10519  return -EPERM;
10520  }
10521  }
10522 
10523  if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10524  BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
10525  bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
10526  } else
10527  BNX2X_DEV_INFO("IGU Normal Mode\n");
10528 
10529  bnx2x_get_igu_cam_info(bp);
10530 
10532  }
10533 
10534  /*
10535  * set base FW non-default (fast path) status block id, this value is
10536  * used to initialize the fw_sb_id saved on the fp/queue structure to
10537  * determine the id used by the FW.
10538  */
10539  if (CHIP_IS_E1x(bp))
10540  bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
10541  else /*
10542  * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
10543  * the same queue are indicated on the same IGU SB). So we prefer
10544  * FW and IGU SBs to be the same value.
10545  */
10546  bp->base_fw_ndsb = bp->igu_base_sb;
10547 
10548  BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
10549  "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
10550  bp->igu_sb_cnt, bp->base_fw_ndsb);
10551 
10552  /*
10553  * Initialize MF configuration
10554  */
10555 
10556  bp->mf_ov = 0;
10557  bp->mf_mode = 0;
10558  vn = BP_VN(bp);
10559 
10560  if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
10561  BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
10562  bp->common.shmem2_base, SHMEM2_RD(bp, size),
10563  (u32)offsetof(struct shmem2_region, mf_cfg_addr));
10564 
10565  if (SHMEM2_HAS(bp, mf_cfg_addr))
10566  bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
10567  else
10568  bp->common.mf_cfg_base = bp->common.shmem_base +
10569  offsetof(struct shmem_region, func_mb) +
10570  E1H_FUNC_MAX * sizeof(struct drv_func_mb);
10571  /*
10572  * get mf configuration:
10573  * 1. existence of MF configuration
10574  * 2. MAC address must be legal (check only upper bytes)
10575  * for Switch-Independent mode;
10576  * OVLAN must be legal for Switch-Dependent mode
10577  * 3. SF_MODE configures specific MF mode
10578  */
10579  if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10580  /* get mf configuration */
10581  val = SHMEM_RD(bp,
10582  dev_info.shared_feature_config.config);
10584 
10585  switch (val) {
10587  val = MF_CFG_RD(bp, func_mf_config[func].
10588  mac_upper);
10589  /* check for legal mac (upper bytes)*/
10590  if (val != 0xffff) {
10591  bp->mf_mode = MULTI_FUNCTION_SI;
10592  bp->mf_config[vn] = MF_CFG_RD(bp,
10593  func_mf_config[func].config);
10594  } else
10595  BNX2X_DEV_INFO("illegal MAC address for SI\n");
10596  break;
10598  if ((!CHIP_IS_E1x(bp)) &&
10599  (MF_CFG_RD(bp, func_mf_config[func].
10600  mac_upper) != 0xffff) &&
10601  (SHMEM2_HAS(bp,
10602  afex_driver_support))) {
10604  bp->mf_config[vn] = MF_CFG_RD(bp,
10605  func_mf_config[func].config);
10606  } else {
10607  BNX2X_DEV_INFO("can not configure afex mode\n");
10608  }
10609  break;
10611  /* get OV configuration */
10612  val = MF_CFG_RD(bp,
10613  func_mf_config[FUNC_0].e1hov_tag);
10615 
10616  if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10617  bp->mf_mode = MULTI_FUNCTION_SD;
10618  bp->mf_config[vn] = MF_CFG_RD(bp,
10619  func_mf_config[func].config);
10620  } else
10621  BNX2X_DEV_INFO("illegal OV for SD\n");
10622  break;
10623  default:
10624  /* Unknown configuration: reset mf_config */
10625  bp->mf_config[vn] = 0;
10626  BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
10627  }
10628  }
10629 
10630  BNX2X_DEV_INFO("%s function mode\n",
10631  IS_MF(bp) ? "multi" : "single");
10632 
10633  switch (bp->mf_mode) {
10634  case MULTI_FUNCTION_SD:
10635  val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
10637  if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10638  bp->mf_ov = val;
10639  bp->path_has_ovlan = true;
10640 
10641  BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
10642  func, bp->mf_ov, bp->mf_ov);
10643  } else {
10644  dev_err(&bp->pdev->dev,
10645  "No valid MF OV for func %d, aborting\n",
10646  func);
10647  return -EPERM;
10648  }
10649  break;
10650  case MULTI_FUNCTION_AFEX:
10651  BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
10652  break;
10653  case MULTI_FUNCTION_SI:
10654  BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
10655  func);
10656  break;
10657  default:
10658  if (vn) {
10659  dev_err(&bp->pdev->dev,
10660  "VN %d is in a single function mode, aborting\n",
10661  vn);
10662  return -EPERM;
10663  }
10664  break;
10665  }
10666 
10667  /* check if other port on the path needs ovlan:
10668  * Since MF configuration is shared between ports
10669  * Possible mixed modes are only
10670  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
10671  */
10672  if (CHIP_MODE_IS_4_PORT(bp) &&
10673  !bp->path_has_ovlan &&
10674  !IS_MF(bp) &&
10675  bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10676  u8 other_port = !BP_PORT(bp);
10677  u8 other_func = BP_PATH(bp) + 2*other_port;
10678  val = MF_CFG_RD(bp,
10679  func_mf_config[other_func].e1hov_tag);
10680  if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
10681  bp->path_has_ovlan = true;
10682  }
10683  }
10684 
10685  /* adjust igu_sb_cnt to MF for E1x */
10686  if (CHIP_IS_E1x(bp) && IS_MF(bp))
10687  bp->igu_sb_cnt /= E1HVN_MAX;
10688 
10689  /* port info */
10690  bnx2x_get_port_hwinfo(bp);
10691 
10692  /* Get MAC addresses */
10693  bnx2x_get_mac_hwinfo(bp);
10694 
10695  bnx2x_get_cnic_info(bp);
10696 
10697  return rc;
10698 }
10699 
10700 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
10701 {
10702  int cnt, i, block_end, rodi;
10703  char vpd_start[BNX2X_VPD_LEN+1];
10704  char str_id_reg[VENDOR_ID_LEN+1];
10705  char str_id_cap[VENDOR_ID_LEN+1];
10706  char *vpd_data;
10707  char *vpd_extended_data = NULL;
10708  u8 len;
10709 
10710  cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
10711  memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
10712 
10713  if (cnt < BNX2X_VPD_LEN)
10714  goto out_not_found;
10715 
10716  /* VPD RO tag should be first tag after identifier string, hence
10717  * we should be able to find it in first BNX2X_VPD_LEN chars
10718  */
10719  i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
10721  if (i < 0)
10722  goto out_not_found;
10723 
10724  block_end = i + PCI_VPD_LRDT_TAG_SIZE +
10725  pci_vpd_lrdt_size(&vpd_start[i]);
10726 
10727  i += PCI_VPD_LRDT_TAG_SIZE;
10728 
10729  if (block_end > BNX2X_VPD_LEN) {
10730  vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
10731  if (vpd_extended_data == NULL)
10732  goto out_not_found;
10733 
10734  /* read rest of vpd image into vpd_extended_data */
10735  memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
10736  cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
10737  block_end - BNX2X_VPD_LEN,
10738  vpd_extended_data + BNX2X_VPD_LEN);
10739  if (cnt < (block_end - BNX2X_VPD_LEN))
10740  goto out_not_found;
10741  vpd_data = vpd_extended_data;
10742  } else
10743  vpd_data = vpd_start;
10744 
10745  /* now vpd_data holds full vpd content in both cases */
10746 
10747  rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10749  if (rodi < 0)
10750  goto out_not_found;
10751 
10752  len = pci_vpd_info_field_size(&vpd_data[rodi]);
10753 
10754  if (len != VENDOR_ID_LEN)
10755  goto out_not_found;
10756 
10757  rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10758 
10759  /* vendor specific info */
10760  snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
10761  snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
10762  if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
10763  !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
10764 
10765  rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10767  if (rodi >= 0) {
10768  len = pci_vpd_info_field_size(&vpd_data[rodi]);
10769 
10770  rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10771 
10772  if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
10773  memcpy(bp->fw_ver, &vpd_data[rodi], len);
10774  bp->fw_ver[len] = ' ';
10775  }
10776  }
10777  kfree(vpd_extended_data);
10778  return;
10779  }
10780 out_not_found:
10781  kfree(vpd_extended_data);
10782  return;
10783 }
10784 
10785 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
10786 {
10787  u32 flags = 0;
10788 
10789  if (CHIP_REV_IS_FPGA(bp))
10790  SET_FLAGS(flags, MODE_FPGA);
10791  else if (CHIP_REV_IS_EMUL(bp))
10792  SET_FLAGS(flags, MODE_EMUL);
10793  else
10794  SET_FLAGS(flags, MODE_ASIC);
10795 
10796  if (CHIP_MODE_IS_4_PORT(bp))
10797  SET_FLAGS(flags, MODE_PORT4);
10798  else
10799  SET_FLAGS(flags, MODE_PORT2);
10800 
10801  if (CHIP_IS_E2(bp))
10802  SET_FLAGS(flags, MODE_E2);
10803  else if (CHIP_IS_E3(bp)) {
10804  SET_FLAGS(flags, MODE_E3);
10805  if (CHIP_REV(bp) == CHIP_REV_Ax)
10806  SET_FLAGS(flags, MODE_E3_A0);
10807  else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
10808  SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
10809  }
10810 
10811  if (IS_MF(bp)) {
10812  SET_FLAGS(flags, MODE_MF);
10813  switch (bp->mf_mode) {
10814  case MULTI_FUNCTION_SD:
10815  SET_FLAGS(flags, MODE_MF_SD);
10816  break;
10817  case MULTI_FUNCTION_SI:
10818  SET_FLAGS(flags, MODE_MF_SI);
10819  break;
10820  case MULTI_FUNCTION_AFEX:
10821  SET_FLAGS(flags, MODE_MF_AFEX);
10822  break;
10823  }
10824  } else
10825  SET_FLAGS(flags, MODE_SF);
10826 
10827 #if defined(__LITTLE_ENDIAN)
10828  SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
10829 #else /*(__BIG_ENDIAN)*/
10830  SET_FLAGS(flags, MODE_BIG_ENDIAN);
10831 #endif
10832  INIT_MODE_FLAGS(bp) = flags;
10833 }
10834 
10835 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
10836 {
10837  int func;
10838  int rc;
10839 
10840  mutex_init(&bp->port.phy_mutex);
10841  mutex_init(&bp->fw_mb_mutex);
10842  spin_lock_init(&bp->stats_lock);
10843 #ifdef BCM_CNIC
10844  mutex_init(&bp->cnic_mutex);
10845 #endif
10846 
10847  INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
10848  INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
10849  INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
10850  rc = bnx2x_get_hwinfo(bp);
10851  if (rc)
10852  return rc;
10853 
10854  bnx2x_set_modes_bitmap(bp);
10855 
10856  rc = bnx2x_alloc_mem_bp(bp);
10857  if (rc)
10858  return rc;
10859 
10860  bnx2x_read_fwinfo(bp);
10861 
10862  func = BP_FUNC(bp);
10863 
10864  /* need to reset chip if undi was active */
10865  if (!BP_NOMCP(bp)) {
10866  /* init fw_seq */
10867  bp->fw_seq =
10868  SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10870  BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10871 
10872  bnx2x_prev_unload(bp);
10873  }
10874 
10875 
10876  if (CHIP_REV_IS_FPGA(bp))
10877  dev_err(&bp->pdev->dev, "FPGA detected\n");
10878 
10879  if (BP_NOMCP(bp) && (func == 0))
10880  dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
10881 
10882  bp->disable_tpa = disable_tpa;
10883 
10884 #ifdef BCM_CNIC
10885  bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
10886 #endif
10887 
10888  /* Set TPA flags */
10889  if (bp->disable_tpa) {
10891  bp->dev->features &= ~NETIF_F_LRO;
10892  } else {
10894  bp->dev->features |= NETIF_F_LRO;
10895  }
10896 
10897  if (CHIP_IS_E1(bp))
10898  bp->dropless_fc = 0;
10899  else
10900  bp->dropless_fc = dropless_fc;
10901 
10902  bp->mrrs = mrrs;
10903 
10904  bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
10905 
10906  /* make sure that the numbers are in the right granularity */
10907  bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
10908  bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
10909 
10910  bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
10911 
10912  init_timer(&bp->timer);
10913  bp->timer.expires = jiffies + bp->current_interval;
10914  bp->timer.data = (unsigned long) bp;
10915  bp->timer.function = bnx2x_timer;
10916 
10919 
10920 #ifdef BCM_CNIC
10921  if (CHIP_IS_E1x(bp))
10922  bp->cnic_base_cl_id = FP_SB_MAX_E1x;
10923  else
10924  bp->cnic_base_cl_id = FP_SB_MAX_E2;
10925 #endif
10926 
10927  /* multiple tx priority */
10928  if (CHIP_IS_E1x(bp))
10930  if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
10932  if (CHIP_IS_E3B0(bp))
10934 
10935  return rc;
10936 }
10937 
10938 
10939 /****************************************************************************
10940 * General service functions
10941 ****************************************************************************/
10942 
10943 /*
10944  * net_device service functions
10945  */
10946 
10947 /* called with rtnl_lock */
10948 static int bnx2x_open(struct net_device *dev)
10949 {
10950  struct bnx2x *bp = netdev_priv(dev);
10951  bool global = false;
10952  int other_engine = BP_PATH(bp) ? 0 : 1;
10953  bool other_load_status, load_status;
10954 
10955  bp->stats_init = true;
10956 
10957  netif_carrier_off(dev);
10958 
10960 
10961  other_load_status = bnx2x_get_load_status(bp, other_engine);
10962  load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
10963 
10964  /*
10965  * If parity had happen during the unload, then attentions
10966  * and/or RECOVERY_IN_PROGRES may still be set. In this case we
10967  * want the first function loaded on the current engine to
10968  * complete the recovery.
10969  */
10970  if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
10971  bnx2x_chk_parity_attn(bp, &global, true))
10972  do {
10973  /*
10974  * If there are attentions and they are in a global
10975  * blocks, set the GLOBAL_RESET bit regardless whether
10976  * it will be this function that will complete the
10977  * recovery or not.
10978  */
10979  if (global)
10981 
10982  /*
10983  * Only the first function on the current engine should
10984  * try to recover in open. In case of attentions in
10985  * global blocks only the first in the chip should try
10986  * to recover.
10987  */
10988  if ((!load_status &&
10989  (!global || !other_load_status)) &&
10990  bnx2x_trylock_leader_lock(bp) &&
10991  !bnx2x_leader_reset(bp)) {
10992  netdev_info(bp->dev, "Recovered in open\n");
10993  break;
10994  }
10995 
10996  /* recovery has failed... */
10999 
11000  BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11001  "If you still see this message after a few retries then power cycle is required.\n");
11002 
11003  return -EAGAIN;
11004  } while (0);
11005 
11007  return bnx2x_nic_load(bp, LOAD_OPEN);
11008 }
11009 
11010 /* called with rtnl_lock */
11011 static int bnx2x_close(struct net_device *dev)
11012 {
11013  struct bnx2x *bp = netdev_priv(dev);
11014 
11015  /* Unload the driver, release IRQs */
11016  bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11017 
11018  /* Power off */
11020 
11021  return 0;
11022 }
11023 
11024 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11025  struct bnx2x_mcast_ramrod_params *p)
11026 {
11027  int mc_count = netdev_mc_count(bp->dev);
11028  struct bnx2x_mcast_list_elem *mc_mac =
11029  kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11030  struct netdev_hw_addr *ha;
11031 
11032  if (!mc_mac)
11033  return -ENOMEM;
11034 
11035  INIT_LIST_HEAD(&p->mcast_list);
11036 
11037  netdev_for_each_mc_addr(ha, bp->dev) {
11038  mc_mac->mac = bnx2x_mc_addr(ha);
11039  list_add_tail(&mc_mac->link, &p->mcast_list);
11040  mc_mac++;
11041  }
11042 
11043  p->mcast_list_len = mc_count;
11044 
11045  return 0;
11046 }
11047 
11048 static void bnx2x_free_mcast_macs_list(
11049  struct bnx2x_mcast_ramrod_params *p)
11050 {
11051  struct bnx2x_mcast_list_elem *mc_mac =
11053  link);
11054 
11055  WARN_ON(!mc_mac);
11056  kfree(mc_mac);
11057 }
11058 
11066 static int bnx2x_set_uc_list(struct bnx2x *bp)
11067 {
11068  int rc;
11069  struct net_device *dev = bp->dev;
11070  struct netdev_hw_addr *ha;
11071  struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11072  unsigned long ramrod_flags = 0;
11073 
11074  /* First schedule a cleanup up of old configuration */
11075  rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11076  if (rc < 0) {
11077  BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11078  return rc;
11079  }
11080 
11081  netdev_for_each_uc_addr(ha, dev) {
11082  rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11083  BNX2X_UC_LIST_MAC, &ramrod_flags);
11084  if (rc == -EEXIST) {
11085  DP(BNX2X_MSG_SP,
11086  "Failed to schedule ADD operations: %d\n", rc);
11087  /* do not treat adding same MAC as error */
11088  rc = 0;
11089 
11090  } else if (rc < 0) {
11091 
11092  BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11093  rc);
11094  return rc;
11095  }
11096  }
11097 
11098  /* Execute the pending commands */
11099  __set_bit(RAMROD_CONT, &ramrod_flags);
11100  return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11101  BNX2X_UC_LIST_MAC, &ramrod_flags);
11102 }
11103 
11104 static int bnx2x_set_mc_list(struct bnx2x *bp)
11105 {
11106  struct net_device *dev = bp->dev;
11107  struct bnx2x_mcast_ramrod_params rparam = {NULL};
11108  int rc = 0;
11109 
11110  rparam.mcast_obj = &bp->mcast_obj;
11111 
11112  /* first, clear all configured multicast MACs */
11113  rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11114  if (rc < 0) {
11115  BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11116  return rc;
11117  }
11118 
11119  /* then, configure a new MACs list */
11120  if (netdev_mc_count(dev)) {
11121  rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11122  if (rc) {
11123  BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11124  rc);
11125  return rc;
11126  }
11127 
11128  /* Now add the new MACs */
11129  rc = bnx2x_config_mcast(bp, &rparam,
11131  if (rc < 0)
11132  BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11133  rc);
11134 
11135  bnx2x_free_mcast_macs_list(&rparam);
11136  }
11137 
11138  return rc;
11139 }
11140 
11141 
11142 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11144 {
11145  struct bnx2x *bp = netdev_priv(dev);
11147 
11148  if (bp->state != BNX2X_STATE_OPEN) {
11149  DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11150  return;
11151  }
11152 
11153  DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11154 
11155  if (dev->flags & IFF_PROMISC)
11156  rx_mode = BNX2X_RX_MODE_PROMISC;
11157  else if ((dev->flags & IFF_ALLMULTI) ||
11159  CHIP_IS_E1(bp)))
11160  rx_mode = BNX2X_RX_MODE_ALLMULTI;
11161  else {
11162  /* some multicasts */
11163  if (bnx2x_set_mc_list(bp) < 0)
11164  rx_mode = BNX2X_RX_MODE_ALLMULTI;
11165 
11166  if (bnx2x_set_uc_list(bp) < 0)
11167  rx_mode = BNX2X_RX_MODE_PROMISC;
11168  }
11169 
11170  bp->rx_mode = rx_mode;
11171 #ifdef BCM_CNIC
11172  /* handle ISCSI SD mode */
11173  if (IS_MF_ISCSI_SD(bp))
11175 #endif
11176 
11177  /* Schedule the rx_mode command */
11180  return;
11181  }
11182 
11184 }
11185 
11186 /* called with rtnl_lock */
11187 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11188  int devad, u16 addr)
11189 {
11190  struct bnx2x *bp = netdev_priv(netdev);
11191  u16 value;
11192  int rc;
11193 
11194  DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11195  prtad, devad, addr);
11196 
11197  /* The HW expects different devad if CL22 is used */
11198  devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11199 
11201  rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11203  DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11204 
11205  if (!rc)
11206  rc = value;
11207  return rc;
11208 }
11209 
11210 /* called with rtnl_lock */
11211 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11212  u16 addr, u16 value)
11213 {
11214  struct bnx2x *bp = netdev_priv(netdev);
11215  int rc;
11216 
11218  "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11219  prtad, devad, addr, value);
11220 
11221  /* The HW expects different devad if CL22 is used */
11222  devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11223 
11225  rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11227  return rc;
11228 }
11229 
11230 /* called with rtnl_lock */
11231 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11232 {
11233  struct bnx2x *bp = netdev_priv(dev);
11234  struct mii_ioctl_data *mdio = if_mii(ifr);
11235 
11236  DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11237  mdio->phy_id, mdio->reg_num, mdio->val_in);
11238 
11239  if (!netif_running(dev))
11240  return -EAGAIN;
11241 
11242  return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11243 }
11244 
11245 #ifdef CONFIG_NET_POLL_CONTROLLER
11246 static void poll_bnx2x(struct net_device *dev)
11247 {
11248  struct bnx2x *bp = netdev_priv(dev);
11249  int i;
11250 
11251  for_each_eth_queue(bp, i) {
11252  struct bnx2x_fastpath *fp = &bp->fp[i];
11253  napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11254  }
11255 }
11256 #endif
11257 
11258 static int bnx2x_validate_addr(struct net_device *dev)
11259 {
11260  struct bnx2x *bp = netdev_priv(dev);
11261 
11262  if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11263  BNX2X_ERR("Non-valid Ethernet address\n");
11264  return -EADDRNOTAVAIL;
11265  }
11266  return 0;
11267 }
11268 
11269 static const struct net_device_ops bnx2x_netdev_ops = {
11270  .ndo_open = bnx2x_open,
11271  .ndo_stop = bnx2x_close,
11272  .ndo_start_xmit = bnx2x_start_xmit,
11273  .ndo_select_queue = bnx2x_select_queue,
11274  .ndo_set_rx_mode = bnx2x_set_rx_mode,
11275  .ndo_set_mac_address = bnx2x_change_mac_addr,
11276  .ndo_validate_addr = bnx2x_validate_addr,
11277  .ndo_do_ioctl = bnx2x_ioctl,
11278  .ndo_change_mtu = bnx2x_change_mtu,
11279  .ndo_fix_features = bnx2x_fix_features,
11280  .ndo_set_features = bnx2x_set_features,
11281  .ndo_tx_timeout = bnx2x_tx_timeout,
11282 #ifdef CONFIG_NET_POLL_CONTROLLER
11283  .ndo_poll_controller = poll_bnx2x,
11284 #endif
11285  .ndo_setup_tc = bnx2x_setup_tc,
11286 
11287 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
11288  .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
11289 #endif
11290 };
11291 
11292 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
11293 {
11294  struct device *dev = &bp->pdev->dev;
11295 
11296  if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11297  bp->flags |= USING_DAC_FLAG;
11298  if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
11299  dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
11300  return -EIO;
11301  }
11302  } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11303  dev_err(dev, "System does not support DMA, aborting\n");
11304  return -EIO;
11305  }
11306 
11307  return 0;
11308 }
11309 
11310 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
11311  struct net_device *dev,
11312  unsigned long board_type)
11313 {
11314  struct bnx2x *bp;
11315  int rc;
11316  u32 pci_cfg_dword;
11317  bool chip_is_e1x = (board_type == BCM57710 ||
11318  board_type == BCM57711 ||
11319  board_type == BCM57711E);
11320 
11321  SET_NETDEV_DEV(dev, &pdev->dev);
11322  bp = netdev_priv(dev);
11323 
11324  bp->dev = dev;
11325  bp->pdev = pdev;
11326  bp->flags = 0;
11327 
11328  rc = pci_enable_device(pdev);
11329  if (rc) {
11330  dev_err(&bp->pdev->dev,
11331  "Cannot enable PCI device, aborting\n");
11332  goto err_out;
11333  }
11334 
11335  if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11336  dev_err(&bp->pdev->dev,
11337  "Cannot find PCI device base address, aborting\n");
11338  rc = -ENODEV;
11339  goto err_out_disable;
11340  }
11341 
11342  if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11343  dev_err(&bp->pdev->dev, "Cannot find second PCI device"
11344  " base address, aborting\n");
11345  rc = -ENODEV;
11346  goto err_out_disable;
11347  }
11348 
11349  if (atomic_read(&pdev->enable_cnt) == 1) {
11351  if (rc) {
11352  dev_err(&bp->pdev->dev,
11353  "Cannot obtain PCI resources, aborting\n");
11354  goto err_out_disable;
11355  }
11356 
11357  pci_set_master(pdev);
11358  pci_save_state(pdev);
11359  }
11360 
11362  if (bp->pm_cap == 0) {
11363  dev_err(&bp->pdev->dev,
11364  "Cannot find power management capability, aborting\n");
11365  rc = -EIO;
11366  goto err_out_release;
11367  }
11368 
11369  if (!pci_is_pcie(pdev)) {
11370  dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
11371  rc = -EIO;
11372  goto err_out_release;
11373  }
11374 
11375  rc = bnx2x_set_coherency_mask(bp);
11376  if (rc)
11377  goto err_out_release;
11378 
11379  dev->mem_start = pci_resource_start(pdev, 0);
11380  dev->base_addr = dev->mem_start;
11381  dev->mem_end = pci_resource_end(pdev, 0);
11382 
11383  dev->irq = pdev->irq;
11384 
11385  bp->regview = pci_ioremap_bar(pdev, 0);
11386  if (!bp->regview) {
11387  dev_err(&bp->pdev->dev,
11388  "Cannot map register space, aborting\n");
11389  rc = -ENOMEM;
11390  goto err_out_release;
11391  }
11392 
11393  /* In E1/E1H use pci device function given by kernel.
11394  * In E2/E3 read physical function from ME register since these chips
11395  * support Physical Device Assignment where kernel BDF maybe arbitrary
11396  * (depending on hypervisor).
11397  */
11398  if (chip_is_e1x)
11399  bp->pf_num = PCI_FUNC(pdev->devfn);
11400  else {/* chip is E2/3*/
11401  pci_read_config_dword(bp->pdev,
11402  PCICFG_ME_REGISTER, &pci_cfg_dword);
11403  bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11405  }
11406  BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
11407 
11409 
11410  /* clean indirect addresses */
11411  pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11413  /*
11414  * Clean the following indirect addresses for all functions since it
11415  * is not used by the driver.
11416  */
11421 
11422  if (chip_is_e1x) {
11427  }
11428 
11429  /*
11430  * Enable internal target-read (in case we are probed after PF FLR).
11431  * Must be done prior to any BAR read access. Only for 57712 and up
11432  */
11433  if (!chip_is_e1x)
11435 
11436  dev->watchdog_timeo = TX_TIMEOUT;
11437 
11438  dev->netdev_ops = &bnx2x_netdev_ops;
11439  bnx2x_set_ethtool_ops(dev);
11440 
11441  dev->priv_flags |= IFF_UNICAST_FLT;
11442 
11447 
11450 
11451  dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
11452  if (bp->flags & USING_DAC_FLAG)
11453  dev->features |= NETIF_F_HIGHDMA;
11454 
11455  /* Add Loopback capability to the device */
11456  dev->hw_features |= NETIF_F_LOOPBACK;
11457 
11458 #ifdef BCM_DCBNL
11459  dev->dcbnl_ops = &bnx2x_dcbnl_ops;
11460 #endif
11461 
11462  /* get_port_hwinfo() will set prtad and mmds properly */
11463  bp->mdio.prtad = MDIO_PRTAD_NONE;
11464  bp->mdio.mmds = 0;
11465  bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
11466  bp->mdio.dev = dev;
11467  bp->mdio.mdio_read = bnx2x_mdio_read;
11468  bp->mdio.mdio_write = bnx2x_mdio_write;
11469 
11470  return 0;
11471 
11472 err_out_release:
11473  if (atomic_read(&pdev->enable_cnt) == 1)
11474  pci_release_regions(pdev);
11475 
11476 err_out_disable:
11477  pci_disable_device(pdev);
11478  pci_set_drvdata(pdev, NULL);
11479 
11480 err_out:
11481  return rc;
11482 }
11483 
11484 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
11485  int *width, int *speed)
11486 {
11488 
11489  *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
11490 
11491  /* return value of 1=2.5GHz 2=5GHz */
11492  *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
11493 }
11494 
11495 static int bnx2x_check_firmware(struct bnx2x *bp)
11496 {
11497  const struct firmware *firmware = bp->firmware;
11498  struct bnx2x_fw_file_hdr *fw_hdr;
11499  struct bnx2x_fw_file_section *sections;
11500  u32 offset, len, num_ops;
11501  u16 *ops_offsets;
11502  int i;
11503  const u8 *fw_ver;
11504 
11505  if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
11506  BNX2X_ERR("Wrong FW size\n");
11507  return -EINVAL;
11508  }
11509 
11510  fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
11511  sections = (struct bnx2x_fw_file_section *)fw_hdr;
11512 
11513  /* Make sure none of the offsets and sizes make us read beyond
11514  * the end of the firmware data */
11515  for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
11516  offset = be32_to_cpu(sections[i].offset);
11517  len = be32_to_cpu(sections[i].len);
11518  if (offset + len > firmware->size) {
11519  BNX2X_ERR("Section %d length is out of bounds\n", i);
11520  return -EINVAL;
11521  }
11522  }
11523 
11524  /* Likewise for the init_ops offsets */
11525  offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
11526  ops_offsets = (u16 *)(firmware->data + offset);
11527  num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
11528 
11529  for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
11530  if (be16_to_cpu(ops_offsets[i]) > num_ops) {
11531  BNX2X_ERR("Section offset %d is out of bounds\n", i);
11532  return -EINVAL;
11533  }
11534  }
11535 
11536  /* Check FW version */
11537  offset = be32_to_cpu(fw_hdr->fw_version.offset);
11538  fw_ver = firmware->data + offset;
11539  if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
11540  (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
11541  (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
11542  (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
11543  BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
11544  fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
11549  return -EINVAL;
11550  }
11551 
11552  return 0;
11553 }
11554 
11555 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11556 {
11557  const __be32 *source = (const __be32 *)_source;
11558  u32 *target = (u32 *)_target;
11559  u32 i;
11560 
11561  for (i = 0; i < n/4; i++)
11562  target[i] = be32_to_cpu(source[i]);
11563 }
11564 
11565 /*
11566  Ops array is stored in the following format:
11567  {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
11568  */
11569 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
11570 {
11571  const __be32 *source = (const __be32 *)_source;
11572  struct raw_op *target = (struct raw_op *)_target;
11573  u32 i, j, tmp;
11574 
11575  for (i = 0, j = 0; i < n/8; i++, j += 2) {
11576  tmp = be32_to_cpu(source[j]);
11577  target[i].op = (tmp >> 24) & 0xff;
11578  target[i].offset = tmp & 0xffffff;
11579  target[i].raw_data = be32_to_cpu(source[j + 1]);
11580  }
11581 }
11582 
11583 /* IRO array is stored in the following format:
11584  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
11585  */
11586 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
11587 {
11588  const __be32 *source = (const __be32 *)_source;
11589  struct iro *target = (struct iro *)_target;
11590  u32 i, j, tmp;
11591 
11592  for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
11593  target[i].base = be32_to_cpu(source[j]);
11594  j++;
11595  tmp = be32_to_cpu(source[j]);
11596  target[i].m1 = (tmp >> 16) & 0xffff;
11597  target[i].m2 = tmp & 0xffff;
11598  j++;
11599  tmp = be32_to_cpu(source[j]);
11600  target[i].m3 = (tmp >> 16) & 0xffff;
11601  target[i].size = tmp & 0xffff;
11602  j++;
11603  }
11604 }
11605 
11606 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11607 {
11608  const __be16 *source = (const __be16 *)_source;
11609  u16 *target = (u16 *)_target;
11610  u32 i;
11611 
11612  for (i = 0; i < n/2; i++)
11613  target[i] = be16_to_cpu(source[i]);
11614 }
11615 
11616 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
11617 do { \
11618  u32 len = be32_to_cpu(fw_hdr->arr.len); \
11619  bp->arr = kmalloc(len, GFP_KERNEL); \
11620  if (!bp->arr) \
11621  goto lbl; \
11622  func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
11623  (u8 *)bp->arr, len); \
11624 } while (0)
11625 
11626 static int bnx2x_init_firmware(struct bnx2x *bp)
11627 {
11628  const char *fw_file_name;
11629  struct bnx2x_fw_file_hdr *fw_hdr;
11630  int rc;
11631 
11632  if (bp->firmware)
11633  return 0;
11634 
11635  if (CHIP_IS_E1(bp))
11636  fw_file_name = FW_FILE_NAME_E1;
11637  else if (CHIP_IS_E1H(bp))
11638  fw_file_name = FW_FILE_NAME_E1H;
11639  else if (!CHIP_IS_E1x(bp))
11640  fw_file_name = FW_FILE_NAME_E2;
11641  else {
11642  BNX2X_ERR("Unsupported chip revision\n");
11643  return -EINVAL;
11644  }
11645  BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
11646 
11647  rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
11648  if (rc) {
11649  BNX2X_ERR("Can't load firmware file %s\n",
11650  fw_file_name);
11651  goto request_firmware_exit;
11652  }
11653 
11654  rc = bnx2x_check_firmware(bp);
11655  if (rc) {
11656  BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
11657  goto request_firmware_exit;
11658  }
11659 
11660  fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
11661 
11662  /* Initialize the pointers to the init arrays */
11663  /* Blob */
11664  BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
11665 
11666  /* Opcodes */
11667  BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
11668 
11669  /* Offsets */
11670  BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
11671  be16_to_cpu_n);
11672 
11673  /* STORMs firmware */
11674  INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11675  be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
11676  INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
11677  be32_to_cpu(fw_hdr->tsem_pram_data.offset);
11678  INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11679  be32_to_cpu(fw_hdr->usem_int_table_data.offset);
11680  INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
11681  be32_to_cpu(fw_hdr->usem_pram_data.offset);
11682  INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11683  be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
11684  INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
11685  be32_to_cpu(fw_hdr->xsem_pram_data.offset);
11686  INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11687  be32_to_cpu(fw_hdr->csem_int_table_data.offset);
11688  INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
11689  be32_to_cpu(fw_hdr->csem_pram_data.offset);
11690  /* IRO */
11691  BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
11692 
11693  return 0;
11694 
11695 iro_alloc_err:
11696  kfree(bp->init_ops_offsets);
11697 init_offsets_alloc_err:
11698  kfree(bp->init_ops);
11699 init_ops_alloc_err:
11700  kfree(bp->init_data);
11701 request_firmware_exit:
11703  bp->firmware = NULL;
11704 
11705  return rc;
11706 }
11707 
11708 static void bnx2x_release_firmware(struct bnx2x *bp)
11709 {
11710  kfree(bp->init_ops_offsets);
11711  kfree(bp->init_ops);
11712  kfree(bp->init_data);
11714  bp->firmware = NULL;
11715 }
11716 
11717 
11718 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
11719  .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
11720  .init_hw_cmn = bnx2x_init_hw_common,
11721  .init_hw_port = bnx2x_init_hw_port,
11722  .init_hw_func = bnx2x_init_hw_func,
11723 
11724  .reset_hw_cmn = bnx2x_reset_common,
11725  .reset_hw_port = bnx2x_reset_port,
11726  .reset_hw_func = bnx2x_reset_func,
11727 
11728  .gunzip_init = bnx2x_gunzip_init,
11729  .gunzip_end = bnx2x_gunzip_end,
11730 
11731  .init_fw = bnx2x_init_firmware,
11732  .release_fw = bnx2x_release_firmware,
11733 };
11734 
11735 void bnx2x__init_func_obj(struct bnx2x *bp)
11736 {
11737  /* Prepare DMAE related driver resources */
11738  bnx2x_setup_dmae(bp);
11739 
11740  bnx2x_init_func_obj(bp, &bp->func_obj,
11741  bnx2x_sp(bp, func_rdata),
11742  bnx2x_sp_mapping(bp, func_rdata),
11743  bnx2x_sp(bp, func_afex_rdata),
11744  bnx2x_sp_mapping(bp, func_afex_rdata),
11745  &bnx2x_func_sp_drv);
11746 }
11747 
11748 /* must be called after sriov-enable */
11749 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
11750 {
11751  int cid_count = BNX2X_L2_MAX_CID(bp);
11752 
11753 #ifdef BCM_CNIC
11754  cid_count += CNIC_CID_MAX;
11755 #endif
11756  return roundup(cid_count, QM_CID_ROUND);
11757 }
11758 
11765 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
11766 {
11767  int pos;
11768  u16 control;
11769 
11770  pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
11771 
11772  /*
11773  * If MSI-X is not supported - return number of SBs needed to support
11774  * one fast path queue: one FP queue + SB for CNIC
11775  */
11776  if (!pos)
11777  return 1 + CNIC_PRESENT;
11778 
11779  /*
11780  * The value in the PCI configuration space is the index of the last
11781  * entry, namely one less than the actual size of the table, which is
11782  * exactly what we want to return from this function: number of all SBs
11783  * without the default SB.
11784  */
11785  pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
11786  return control & PCI_MSIX_FLAGS_QSIZE;
11787 }
11788 
11789 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
11790  const struct pci_device_id *ent)
11791 {
11792  struct net_device *dev = NULL;
11793  struct bnx2x *bp;
11794  int pcie_width, pcie_speed;
11795  int rc, max_non_def_sbs;
11796  int rx_count, tx_count, rss_count, doorbell_size;
11797  /*
11798  * An estimated maximum supported CoS number according to the chip
11799  * version.
11800  * We will try to roughly estimate the maximum number of CoSes this chip
11801  * may support in order to minimize the memory allocated for Tx
11802  * netdev_queue's. This number will be accurately calculated during the
11803  * initialization of bp->max_cos based on the chip versions AND chip
11804  * revision in the bnx2x_init_bp().
11805  */
11806  u8 max_cos_est = 0;
11807 
11808  switch (ent->driver_data) {
11809  case BCM57710:
11810  case BCM57711:
11811  case BCM57711E:
11812  max_cos_est = BNX2X_MULTI_TX_COS_E1X;
11813  break;
11814 
11815  case BCM57712:
11816  case BCM57712_MF:
11817  max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
11818  break;
11819 
11820  case BCM57800:
11821  case BCM57800_MF:
11822  case BCM57810:
11823  case BCM57810_MF:
11824  case BCM57840_O:
11825  case BCM57840_4_10:
11826  case BCM57840_2_20:
11827  case BCM57840_MFO:
11828  case BCM57840_MF:
11829  case BCM57811:
11830  case BCM57811_MF:
11831  max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
11832  break;
11833 
11834  default:
11835  pr_err("Unknown board_type (%ld), aborting\n",
11836  ent->driver_data);
11837  return -ENODEV;
11838  }
11839 
11840  max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
11841 
11842  WARN_ON(!max_non_def_sbs);
11843 
11844  /* Maximum number of RSS queues: one IGU SB goes to CNIC */
11845  rss_count = max_non_def_sbs - CNIC_PRESENT;
11846 
11847  /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
11848  rx_count = rss_count + FCOE_PRESENT;
11849 
11850  /*
11851  * Maximum number of netdev Tx queues:
11852  * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
11853  */
11854  tx_count = rss_count * max_cos_est + FCOE_PRESENT;
11855 
11856  /* dev zeroed in init_etherdev */
11857  dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
11858  if (!dev)
11859  return -ENOMEM;
11860 
11861  bp = netdev_priv(dev);
11862 
11863  bp->igu_sb_cnt = max_non_def_sbs;
11864  bp->msg_enable = debug;
11865  pci_set_drvdata(pdev, dev);
11866 
11867  rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
11868  if (rc < 0) {
11869  free_netdev(dev);
11870  return rc;
11871  }
11872 
11873  BNX2X_DEV_INFO("max_non_def_sbs %d\n", max_non_def_sbs);
11874 
11875  BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
11876  tx_count, rx_count);
11877 
11878  rc = bnx2x_init_bp(bp);
11879  if (rc)
11880  goto init_one_exit;
11881 
11882  /*
11883  * Map doorbels here as we need the real value of bp->max_cos which
11884  * is initialized in bnx2x_init_bp().
11885  */
11886  doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
11887  if (doorbell_size > pci_resource_len(pdev, 2)) {
11888  dev_err(&bp->pdev->dev,
11889  "Cannot map doorbells, bar size too small, aborting\n");
11890  rc = -ENOMEM;
11891  goto init_one_exit;
11892  }
11894  doorbell_size);
11895  if (!bp->doorbells) {
11896  dev_err(&bp->pdev->dev,
11897  "Cannot map doorbell space, aborting\n");
11898  rc = -ENOMEM;
11899  goto init_one_exit;
11900  }
11901 
11902  /* calc qm_cid_count */
11903  bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
11904 
11905 #ifdef BCM_CNIC
11906  /* disable FCOE L2 queue for E1x */
11907  if (CHIP_IS_E1x(bp))
11908  bp->flags |= NO_FCOE_FLAG;
11909  /* disable FCOE for 57840 device, until FW supports it */
11910  switch (ent->driver_data) {
11911  case BCM57840_O:
11912  case BCM57840_4_10:
11913  case BCM57840_2_20:
11914  case BCM57840_MFO:
11915  case BCM57840_MF:
11916  bp->flags |= NO_FCOE_FLAG;
11917  }
11918 #endif
11919 
11920 
11921  /* Set bp->num_queues for MSI-X mode*/
11923 
11924  /* Configure interrupt mode: try to enable MSI-X/MSI if
11925  * needed.
11926  */
11927  bnx2x_set_int_mode(bp);
11928 
11929  rc = register_netdev(dev);
11930  if (rc) {
11931  dev_err(&pdev->dev, "Cannot register net device\n");
11932  goto init_one_exit;
11933  }
11934 
11935 #ifdef BCM_CNIC
11936  if (!NO_FCOE(bp)) {
11937  /* Add storage MAC address */
11938  rtnl_lock();
11939  dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11940  rtnl_unlock();
11941  }
11942 #endif
11943 
11944  bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
11945 
11947  "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
11948  board_info[ent->driver_data].name,
11949  (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
11950  pcie_width,
11951  ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
11952  (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
11953  "5GHz (Gen2)" : "2.5GHz",
11954  dev->base_addr, bp->pdev->irq, dev->dev_addr);
11955 
11956  return 0;
11957 
11958 init_one_exit:
11959  if (bp->regview)
11960  iounmap(bp->regview);
11961 
11962  if (bp->doorbells)
11963  iounmap(bp->doorbells);
11964 
11965  free_netdev(dev);
11966 
11967  if (atomic_read(&pdev->enable_cnt) == 1)
11968  pci_release_regions(pdev);
11969 
11970  pci_disable_device(pdev);
11971  pci_set_drvdata(pdev, NULL);
11972 
11973  return rc;
11974 }
11975 
11976 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
11977 {
11978  struct net_device *dev = pci_get_drvdata(pdev);
11979  struct bnx2x *bp;
11980 
11981  if (!dev) {
11982  dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
11983  return;
11984  }
11985  bp = netdev_priv(dev);
11986 
11987 #ifdef BCM_CNIC
11988  /* Delete storage MAC address */
11989  if (!NO_FCOE(bp)) {
11990  rtnl_lock();
11991  dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11992  rtnl_unlock();
11993  }
11994 #endif
11995 
11996 #ifdef BCM_DCBNL
11997  /* Delete app tlvs from dcbnl */
11998  bnx2x_dcbnl_update_applist(bp, true);
11999 #endif
12000 
12001  unregister_netdev(dev);
12002 
12003  /* Power on: we can't let PCI layer write to us while we are in D3 */
12005 
12006  /* Disable MSI/MSI-X */
12007  bnx2x_disable_msi(bp);
12008 
12009  /* Power off */
12011 
12012  /* Make sure RESET task is not scheduled before continuing */
12014 
12015  if (bp->regview)
12016  iounmap(bp->regview);
12017 
12018  if (bp->doorbells)
12019  iounmap(bp->doorbells);
12020 
12021  bnx2x_release_firmware(bp);
12022 
12023  bnx2x_free_mem_bp(bp);
12024 
12025  free_netdev(dev);
12026 
12027  if (atomic_read(&pdev->enable_cnt) == 1)
12028  pci_release_regions(pdev);
12029 
12030  pci_disable_device(pdev);
12031  pci_set_drvdata(pdev, NULL);
12032 }
12033 
12034 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12035 {
12036  int i;
12037 
12038  bp->state = BNX2X_STATE_ERROR;
12039 
12041 
12042 #ifdef BCM_CNIC
12043  bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12044 #endif
12045  /* Stop Tx */
12046  bnx2x_tx_disable(bp);
12047 
12048  bnx2x_netif_stop(bp, 0);
12049  /* Delete all NAPI objects */
12050  bnx2x_del_all_napi(bp);
12051 
12052  del_timer_sync(&bp->timer);
12053 
12055 
12056  /* Release IRQs */
12057  bnx2x_free_irq(bp);
12058 
12059  /* Free SKBs, SGEs, TPA pool and driver internals */
12060  bnx2x_free_skbs(bp);
12061 
12062  for_each_rx_queue(bp, i)
12063  bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
12064 
12065  bnx2x_free_mem(bp);
12066 
12067  bp->state = BNX2X_STATE_CLOSED;
12068 
12069  netif_carrier_off(bp->dev);
12070 
12071  return 0;
12072 }
12073 
12074 static void bnx2x_eeh_recover(struct bnx2x *bp)
12075 {
12076  u32 val;
12077 
12078  mutex_init(&bp->port.phy_mutex);
12079 
12080 
12081  val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12084  BNX2X_ERR("BAD MCP validity signature\n");
12085 }
12086 
12095 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12097 {
12098  struct net_device *dev = pci_get_drvdata(pdev);
12099  struct bnx2x *bp = netdev_priv(dev);
12100 
12101  rtnl_lock();
12102 
12103  netif_device_detach(dev);
12104 
12105  if (state == pci_channel_io_perm_failure) {
12106  rtnl_unlock();
12108  }
12109 
12110  if (netif_running(dev))
12111  bnx2x_eeh_nic_unload(bp);
12112 
12113  pci_disable_device(pdev);
12114 
12115  rtnl_unlock();
12116 
12117  /* Request a slot reset */
12119 }
12120 
12127 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12128 {
12129  struct net_device *dev = pci_get_drvdata(pdev);
12130  struct bnx2x *bp = netdev_priv(dev);
12131 
12132  rtnl_lock();
12133 
12134  if (pci_enable_device(pdev)) {
12135  dev_err(&pdev->dev,
12136  "Cannot re-enable PCI device after reset\n");
12137  rtnl_unlock();
12139  }
12140 
12141  pci_set_master(pdev);
12142  pci_restore_state(pdev);
12143 
12144  if (netif_running(dev))
12146 
12147  rtnl_unlock();
12148 
12149  return PCI_ERS_RESULT_RECOVERED;
12150 }
12151 
12159 static void bnx2x_io_resume(struct pci_dev *pdev)
12160 {
12161  struct net_device *dev = pci_get_drvdata(pdev);
12162  struct bnx2x *bp = netdev_priv(dev);
12163 
12164  if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
12165  netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
12166  return;
12167  }
12168 
12169  rtnl_lock();
12170 
12171  bnx2x_eeh_recover(bp);
12172 
12173  if (netif_running(dev))
12175 
12176  netif_device_attach(dev);
12177 
12178  rtnl_unlock();
12179 }
12180 
12181 static const struct pci_error_handlers bnx2x_err_handler = {
12182  .error_detected = bnx2x_io_error_detected,
12183  .slot_reset = bnx2x_io_slot_reset,
12184  .resume = bnx2x_io_resume,
12185 };
12186 
12187 static struct pci_driver bnx2x_pci_driver = {
12188  .name = DRV_MODULE_NAME,
12189  .id_table = bnx2x_pci_tbl,
12190  .probe = bnx2x_init_one,
12191  .remove = __devexit_p(bnx2x_remove_one),
12192  .suspend = bnx2x_suspend,
12193  .resume = bnx2x_resume,
12194  .err_handler = &bnx2x_err_handler,
12195 };
12196 
12197 static int __init bnx2x_init(void)
12198 {
12199  int ret;
12200 
12201  pr_info("%s", version);
12202 
12203  bnx2x_wq = create_singlethread_workqueue("bnx2x");
12204  if (bnx2x_wq == NULL) {
12205  pr_err("Cannot create workqueue\n");
12206  return -ENOMEM;
12207  }
12208 
12209  ret = pci_register_driver(&bnx2x_pci_driver);
12210  if (ret) {
12211  pr_err("Cannot register driver\n");
12212  destroy_workqueue(bnx2x_wq);
12213  }
12214  return ret;
12215 }
12216 
12217 static void __exit bnx2x_cleanup(void)
12218 {
12219  struct list_head *pos, *q;
12220  pci_unregister_driver(&bnx2x_pci_driver);
12221 
12222  destroy_workqueue(bnx2x_wq);
12223 
12224  /* Free globablly allocated resources */
12225  list_for_each_safe(pos, q, &bnx2x_prev_list) {
12226  struct bnx2x_prev_path_list *tmp =
12227  list_entry(pos, struct bnx2x_prev_path_list, list);
12228  list_del(pos);
12229  kfree(tmp);
12230  }
12231 }
12232 
12234 {
12235  REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12236 }
12237 
12238 module_init(bnx2x_init);
12239 module_exit(bnx2x_cleanup);
12240 
12241 #ifdef BCM_CNIC
12242 
12251 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
12252 {
12253  unsigned long ramrod_flags = 0;
12254 
12255  __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12256  return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12257  &bp->iscsi_l2_mac_obj, true,
12258  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12259 }
12260 
12261 /* count denotes the number of new completions we have seen */
12262 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12263 {
12264  struct eth_spe *spe;
12265  int cxt_index, cxt_offset;
12266 
12267 #ifdef BNX2X_STOP_ON_ERROR
12268  if (unlikely(bp->panic))
12269  return;
12270 #endif
12271 
12272  spin_lock_bh(&bp->spq_lock);
12273  BUG_ON(bp->cnic_spq_pending < count);
12274  bp->cnic_spq_pending -= count;
12275 
12276 
12277  for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12278  u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12279  & SPE_HDR_CONN_TYPE) >>
12281  u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12282  >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
12283 
12284  /* Set validation for iSCSI L2 client before sending SETUP
12285  * ramrod
12286  */
12287  if (type == ETH_CONNECTION_TYPE) {
12288  if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
12289  cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
12290  ILT_PAGE_CIDS;
12291  cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
12292  (cxt_index * ILT_PAGE_CIDS);
12294  &bp->context[cxt_index].
12295  vcxt[cxt_offset].eth,
12296  BNX2X_ISCSI_ETH_CID(bp));
12297  }
12298  }
12299 
12300  /*
12301  * There may be not more than 8 L2, not more than 8 L5 SPEs
12302  * and in the air. We also check that number of outstanding
12303  * COMMON ramrods is not more than the EQ and SPQ can
12304  * accommodate.
12305  */
12306  if (type == ETH_CONNECTION_TYPE) {
12307  if (!atomic_read(&bp->cq_spq_left))
12308  break;
12309  else
12310  atomic_dec(&bp->cq_spq_left);
12311  } else if (type == NONE_CONNECTION_TYPE) {
12312  if (!atomic_read(&bp->eq_spq_left))
12313  break;
12314  else
12315  atomic_dec(&bp->eq_spq_left);
12316  } else if ((type == ISCSI_CONNECTION_TYPE) ||
12317  (type == FCOE_CONNECTION_TYPE)) {
12318  if (bp->cnic_spq_pending >=
12319  bp->cnic_eth_dev.max_kwqe_pending)
12320  break;
12321  else
12322  bp->cnic_spq_pending++;
12323  } else {
12324  BNX2X_ERR("Unknown SPE type: %d\n", type);
12325  bnx2x_panic();
12326  break;
12327  }
12328 
12329  spe = bnx2x_sp_get_next(bp);
12330  *spe = *bp->cnic_kwq_cons;
12331 
12332  DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
12333  bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
12334 
12335  if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
12336  bp->cnic_kwq_cons = bp->cnic_kwq;
12337  else
12338  bp->cnic_kwq_cons++;
12339  }
12340  bnx2x_sp_prod_update(bp);
12341  spin_unlock_bh(&bp->spq_lock);
12342 }
12343 
12344 static int bnx2x_cnic_sp_queue(struct net_device *dev,
12345  struct kwqe_16 *kwqes[], u32 count)
12346 {
12347  struct bnx2x *bp = netdev_priv(dev);
12348  int i;
12349 
12350 #ifdef BNX2X_STOP_ON_ERROR
12351  if (unlikely(bp->panic)) {
12352  BNX2X_ERR("Can't post to SP queue while panic\n");
12353  return -EIO;
12354  }
12355 #endif
12356 
12357  if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
12359  BNX2X_ERR("Handling parity error recovery. Try again later\n");
12360  return -EAGAIN;
12361  }
12362 
12363  spin_lock_bh(&bp->spq_lock);
12364 
12365  for (i = 0; i < count; i++) {
12366  struct eth_spe *spe = (struct eth_spe *)kwqes[i];
12367 
12368  if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
12369  break;
12370 
12371  *bp->cnic_kwq_prod = *spe;
12372 
12373  bp->cnic_kwq_pending++;
12374 
12375  DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
12376  spe->hdr.conn_and_cmd_data, spe->hdr.type,
12377  spe->data.update_data_addr.hi,
12378  spe->data.update_data_addr.lo,
12379  bp->cnic_kwq_pending);
12380 
12381  if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
12382  bp->cnic_kwq_prod = bp->cnic_kwq;
12383  else
12384  bp->cnic_kwq_prod++;
12385  }
12386 
12387  spin_unlock_bh(&bp->spq_lock);
12388 
12389  if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
12390  bnx2x_cnic_sp_post(bp, 0);
12391 
12392  return i;
12393 }
12394 
12395 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12396 {
12397  struct cnic_ops *c_ops;
12398  int rc = 0;
12399 
12400  mutex_lock(&bp->cnic_mutex);
12401  c_ops = rcu_dereference_protected(bp->cnic_ops,
12402  lockdep_is_held(&bp->cnic_mutex));
12403  if (c_ops)
12404  rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12405  mutex_unlock(&bp->cnic_mutex);
12406 
12407  return rc;
12408 }
12409 
12410 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12411 {
12412  struct cnic_ops *c_ops;
12413  int rc = 0;
12414 
12415  rcu_read_lock();
12416  c_ops = rcu_dereference(bp->cnic_ops);
12417  if (c_ops)
12418  rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12419  rcu_read_unlock();
12420 
12421  return rc;
12422 }
12423 
12424 /*
12425  * for commands that have no data
12426  */
12427 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
12428 {
12429  struct cnic_ctl_info ctl = {0};
12430 
12431  ctl.cmd = cmd;
12432 
12433  return bnx2x_cnic_ctl_send(bp, &ctl);
12434 }
12435 
12436 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
12437 {
12438  struct cnic_ctl_info ctl = {0};
12439 
12440  /* first we tell CNIC and only then we count this as a completion */
12442  ctl.data.comp.cid = cid;
12443  ctl.data.comp.error = err;
12444 
12445  bnx2x_cnic_ctl_send_bh(bp, &ctl);
12446  bnx2x_cnic_sp_post(bp, 0);
12447 }
12448 
12449 
12450 /* Called with netif_addr_lock_bh() taken.
12451  * Sets an rx_mode config for an iSCSI ETH client.
12452  * Doesn't block.
12453  * Completion should be checked outside.
12454  */
12455 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
12456 {
12457  unsigned long accept_flags = 0, ramrod_flags = 0;
12458  u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
12460 
12461  if (start) {
12462  /* Start accepting on iSCSI L2 ring. Accept all multicasts
12463  * because it's the only way for UIO Queue to accept
12464  * multicasts (in non-promiscuous mode only one Queue per
12465  * function will receive multicast packets (leading in our
12466  * case).
12467  */
12468  __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
12469  __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
12470  __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
12471  __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
12472 
12473  /* Clear STOP_PENDING bit if START is requested */
12475 
12476  sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
12477  } else
12478  /* Clear START_PENDING bit if STOP is requested */
12480 
12482  set_bit(sched_state, &bp->sp_state);
12483  else {
12484  __set_bit(RAMROD_RX, &ramrod_flags);
12485  bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
12486  ramrod_flags);
12487  }
12488 }
12489 
12490 
12491 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
12492 {
12493  struct bnx2x *bp = netdev_priv(dev);
12494  int rc = 0;
12495 
12496  switch (ctl->cmd) {
12497  case DRV_CTL_CTXTBL_WR_CMD: {
12498  u32 index = ctl->data.io.offset;
12499  dma_addr_t addr = ctl->data.io.dma_addr;
12500 
12501  bnx2x_ilt_wr(bp, index, addr);
12502  break;
12503  }
12504 
12506  int count = ctl->data.credit.credit_count;
12507 
12508  bnx2x_cnic_sp_post(bp, count);
12509  break;
12510  }
12511 
12512  /* rtnl_lock is held. */
12513  case DRV_CTL_START_L2_CMD: {
12514  struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12515  unsigned long sp_bits = 0;
12516 
12517  /* Configure the iSCSI classification object */
12518  bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
12519  cp->iscsi_l2_client_id,
12520  cp->iscsi_l2_cid, BP_FUNC(bp),
12521  bnx2x_sp(bp, mac_rdata),
12522  bnx2x_sp_mapping(bp, mac_rdata),
12525  &bp->macs_pool);
12526 
12527  /* Set iSCSI MAC address */
12528  rc = bnx2x_set_iscsi_eth_mac_addr(bp);
12529  if (rc)
12530  break;
12531 
12532  mmiowb();
12533  barrier();
12534 
12535  /* Start accepting on iSCSI L2 ring */
12536 
12537  netif_addr_lock_bh(dev);
12538  bnx2x_set_iscsi_eth_rx_mode(bp, true);
12539  netif_addr_unlock_bh(dev);
12540 
12541  /* bits to wait on */
12544 
12545  if (!bnx2x_wait_sp_comp(bp, sp_bits))
12546  BNX2X_ERR("rx_mode completion timed out!\n");
12547 
12548  break;
12549  }
12550 
12551  /* rtnl_lock is held. */
12552  case DRV_CTL_STOP_L2_CMD: {
12553  unsigned long sp_bits = 0;
12554 
12555  /* Stop accepting on iSCSI L2 ring */
12556  netif_addr_lock_bh(dev);
12557  bnx2x_set_iscsi_eth_rx_mode(bp, false);
12558  netif_addr_unlock_bh(dev);
12559 
12560  /* bits to wait on */
12563 
12564  if (!bnx2x_wait_sp_comp(bp, sp_bits))
12565  BNX2X_ERR("rx_mode completion timed out!\n");
12566 
12567  mmiowb();
12568  barrier();
12569 
12570  /* Unset iSCSI L2 MAC */
12571  rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
12572  BNX2X_ISCSI_ETH_MAC, true);
12573  break;
12574  }
12576  int count = ctl->data.credit.credit_count;
12577 
12579  atomic_add(count, &bp->cq_spq_left);
12581  break;
12582  }
12583  case DRV_CTL_ULP_REGISTER_CMD: {
12584  int ulp_type = ctl->data.register_data.ulp_type;
12585 
12586  if (CHIP_IS_E3(bp)) {
12587  int idx = BP_FW_MB_IDX(bp);
12588  u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
12589  int path = BP_PATH(bp);
12590  int port = BP_PORT(bp);
12591  int i;
12592  u32 scratch_offset;
12593  u32 *host_addr;
12594 
12595  /* first write capability to shmem2 */
12596  if (ulp_type == CNIC_ULP_ISCSI)
12598  else if (ulp_type == CNIC_ULP_FCOE)
12600  SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
12601 
12602  if ((ulp_type != CNIC_ULP_FCOE) ||
12603  (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
12604  (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
12605  break;
12606 
12607  /* if reached here - should write fcoe capabilities */
12608  scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
12609  if (!scratch_offset)
12610  break;
12611  scratch_offset += offsetof(struct glob_ncsi_oem_data,
12612  fcoe_features[path][port]);
12613  host_addr = (u32 *) &(ctl->data.register_data.
12614  fcoe_features);
12615  for (i = 0; i < sizeof(struct fcoe_capabilities);
12616  i += 4)
12617  REG_WR(bp, scratch_offset + i,
12618  *(host_addr + i/4));
12619  }
12620  break;
12621  }
12622 
12624  int ulp_type = ctl->data.ulp_type;
12625 
12626  if (CHIP_IS_E3(bp)) {
12627  int idx = BP_FW_MB_IDX(bp);
12628  u32 cap;
12629 
12630  cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
12631  if (ulp_type == CNIC_ULP_ISCSI)
12633  else if (ulp_type == CNIC_ULP_FCOE)
12635  SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
12636  }
12637  break;
12638  }
12639 
12640  default:
12641  BNX2X_ERR("unknown command %x\n", ctl->cmd);
12642  rc = -EINVAL;
12643  }
12644 
12645  return rc;
12646 }
12647 
12648 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
12649 {
12650  struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12651 
12652  if (bp->flags & USING_MSIX_FLAG) {
12654  cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
12655  cp->irq_arr[0].vector = bp->msix_table[1].vector;
12656  } else {
12658  cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
12659  }
12660  if (!CHIP_IS_E1x(bp))
12661  cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
12662  else
12663  cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
12664 
12665  cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
12666  cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
12667  cp->irq_arr[1].status_blk = bp->def_status_blk;
12668  cp->irq_arr[1].status_blk_num = DEF_SB_ID;
12669  cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
12670 
12671  cp->num_irq = 2;
12672 }
12673 
12674 void bnx2x_setup_cnic_info(struct bnx2x *bp)
12675 {
12676  struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12677 
12678 
12679  cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
12680  bnx2x_cid_ilt_lines(bp);
12681  cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
12684 
12685  if (NO_ISCSI_OOO(bp))
12687 }
12688 
12689 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
12690  void *data)
12691 {
12692  struct bnx2x *bp = netdev_priv(dev);
12693  struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12694 
12695  if (ops == NULL) {
12696  BNX2X_ERR("NULL ops received\n");
12697  return -EINVAL;
12698  }
12699 
12700  bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
12701  if (!bp->cnic_kwq)
12702  return -ENOMEM;
12703 
12704  bp->cnic_kwq_cons = bp->cnic_kwq;
12705  bp->cnic_kwq_prod = bp->cnic_kwq;
12706  bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
12707 
12708  bp->cnic_spq_pending = 0;
12709  bp->cnic_kwq_pending = 0;
12710 
12711  bp->cnic_data = data;
12712 
12713  cp->num_irq = 0;
12715  cp->iro_arr = bp->iro_arr;
12716 
12717  bnx2x_setup_cnic_irq_info(bp);
12718 
12719  rcu_assign_pointer(bp->cnic_ops, ops);
12720 
12721  return 0;
12722 }
12723 
12724 static int bnx2x_unregister_cnic(struct net_device *dev)
12725 {
12726  struct bnx2x *bp = netdev_priv(dev);
12727  struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12728 
12729  mutex_lock(&bp->cnic_mutex);
12730  cp->drv_state = 0;
12731  RCU_INIT_POINTER(bp->cnic_ops, NULL);
12732  mutex_unlock(&bp->cnic_mutex);
12733  synchronize_rcu();
12734  kfree(bp->cnic_kwq);
12735  bp->cnic_kwq = NULL;
12736 
12737  return 0;
12738 }
12739 
12740 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
12741 {
12742  struct bnx2x *bp = netdev_priv(dev);
12743  struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12744 
12745  /* If both iSCSI and FCoE are disabled - return NULL in
12746  * order to indicate CNIC that it should not try to work
12747  * with this device.
12748  */
12749  if (NO_ISCSI(bp) && NO_FCOE(bp))
12750  return NULL;
12751 
12752  cp->drv_owner = THIS_MODULE;
12753  cp->chip_id = CHIP_ID(bp);
12754  cp->pdev = bp->pdev;
12755  cp->io_base = bp->regview;
12756  cp->io_base2 = bp->doorbells;
12757  cp->max_kwqe_pending = 8;
12759  cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
12760  bnx2x_cid_ilt_lines(bp);
12761  cp->ctx_tbl_len = CNIC_ILT_LINES;
12762  cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
12763  cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
12764  cp->drv_ctl = bnx2x_drv_ctl;
12765  cp->drv_register_cnic = bnx2x_register_cnic;
12766  cp->drv_unregister_cnic = bnx2x_unregister_cnic;
12768  cp->iscsi_l2_client_id =
12769  bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
12771 
12772  if (NO_ISCSI_OOO(bp))
12774 
12775  if (NO_ISCSI(bp))
12777 
12778  if (NO_FCOE(bp))
12780 
12782  "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
12783  cp->ctx_blk_size,
12784  cp->ctx_tbl_offset,
12785  cp->ctx_tbl_len,
12786  cp->starting_cid);
12787  return cp;
12788 }
12790 
12791 #endif /* BCM_CNIC */
12792