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main.c
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1 /*
2  *
3  * Broadcom B43legacy wireless driver
4  *
5  * Copyright (c) 2005 Martin Langer <[email protected]>
6  * Copyright (c) 2005-2008 Stefano Brivio <[email protected]>
7  * Copyright (c) 2005, 2006 Michael Buesch <[email protected]>
8  * Copyright (c) 2005 Danny van Dyk <[email protected]>
9  * Copyright (c) 2005 Andreas Jaggi <[email protected]>
10  * Copyright (c) 2007 Larry Finger <[email protected]>
11  *
12  * Some parts of the code in this file are derived from the ipw2200
13  * driver Copyright(c) 2003 - 2004 Intel Corporation.
14 
15  * This program is free software; you can redistribute it and/or modify
16  * it under the terms of the GNU General Public License as published by
17  * the Free Software Foundation; either version 2 of the License, or
18  * (at your option) any later version.
19  *
20  * This program is distributed in the hope that it will be useful,
21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23  * GNU General Public License for more details.
24  *
25  * You should have received a copy of the GNU General Public License
26  * along with this program; see the file COPYING. If not, write to
27  * the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
28  * Boston, MA 02110-1301, USA.
29  *
30  */
31 
32 #include <linux/delay.h>
33 #include <linux/init.h>
34 #include <linux/module.h>
35 #include <linux/if_arp.h>
36 #include <linux/etherdevice.h>
37 #include <linux/firmware.h>
38 #include <linux/workqueue.h>
39 #include <linux/sched.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/slab.h>
43 #include <net/dst.h>
44 #include <asm/unaligned.h>
45 
46 #include "b43legacy.h"
47 #include "main.h"
48 #include "debugfs.h"
49 #include "phy.h"
50 #include "dma.h"
51 #include "pio.h"
52 #include "sysfs.h"
53 #include "xmit.h"
54 #include "radio.h"
55 
56 
57 MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
62 
63 MODULE_FIRMWARE("b43legacy/ucode2.fw");
64 MODULE_FIRMWARE("b43legacy/ucode4.fw");
65 
66 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
67 static int modparam_pio;
68 module_param_named(pio, modparam_pio, int, 0444);
69 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
70 #elif defined(CONFIG_B43LEGACY_DMA)
71 # define modparam_pio 0
72 #elif defined(CONFIG_B43LEGACY_PIO)
73 # define modparam_pio 1
74 #endif
75 
76 static int modparam_bad_frames_preempt;
77 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
78 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
79  " Preemption");
80 
81 static char modparam_fwpostfix[16];
82 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
83 MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
84 
85 /* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
86 static const struct ssb_device_id b43legacy_ssb_tbl[] = {
87  SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
88  SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
89  SSB_DEVTABLE_END
90 };
91 MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
92 
93 
94 /* Channel and ratetables are shared for all devices.
95  * They can't be const, because ieee80211 puts some precalculated
96  * data in there. This data is the same for all devices, so we don't
97  * get concurrency issues */
98 #define RATETAB_ENT(_rateid, _flags) \
99  { \
100  .bitrate = B43legacy_RATE_TO_100KBPS(_rateid), \
101  .hw_value = (_rateid), \
102  .flags = (_flags), \
103  }
104 /*
105  * NOTE: When changing this, sync with xmit.c's
106  * b43legacy_plcp_get_bitrate_idx_* functions!
107  */
108 static struct ieee80211_rate __b43legacy_ratetable[] = {
109  RATETAB_ENT(B43legacy_CCK_RATE_1MB, 0),
110  RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
111  RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
112  RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
113  RATETAB_ENT(B43legacy_OFDM_RATE_6MB, 0),
114  RATETAB_ENT(B43legacy_OFDM_RATE_9MB, 0),
115  RATETAB_ENT(B43legacy_OFDM_RATE_12MB, 0),
116  RATETAB_ENT(B43legacy_OFDM_RATE_18MB, 0),
117  RATETAB_ENT(B43legacy_OFDM_RATE_24MB, 0),
118  RATETAB_ENT(B43legacy_OFDM_RATE_36MB, 0),
119  RATETAB_ENT(B43legacy_OFDM_RATE_48MB, 0),
120  RATETAB_ENT(B43legacy_OFDM_RATE_54MB, 0),
121 };
122 #define b43legacy_b_ratetable (__b43legacy_ratetable + 0)
123 #define b43legacy_b_ratetable_size 4
124 #define b43legacy_g_ratetable (__b43legacy_ratetable + 0)
125 #define b43legacy_g_ratetable_size 12
126 
127 #define CHANTAB_ENT(_chanid, _freq) \
128  { \
129  .center_freq = (_freq), \
130  .hw_value = (_chanid), \
131  }
132 static struct ieee80211_channel b43legacy_bg_chantable[] = {
133  CHANTAB_ENT(1, 2412),
134  CHANTAB_ENT(2, 2417),
135  CHANTAB_ENT(3, 2422),
136  CHANTAB_ENT(4, 2427),
137  CHANTAB_ENT(5, 2432),
138  CHANTAB_ENT(6, 2437),
139  CHANTAB_ENT(7, 2442),
140  CHANTAB_ENT(8, 2447),
141  CHANTAB_ENT(9, 2452),
142  CHANTAB_ENT(10, 2457),
143  CHANTAB_ENT(11, 2462),
144  CHANTAB_ENT(12, 2467),
145  CHANTAB_ENT(13, 2472),
146  CHANTAB_ENT(14, 2484),
147 };
148 
149 static struct ieee80211_supported_band b43legacy_band_2GHz_BPHY = {
150  .channels = b43legacy_bg_chantable,
151  .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
152  .bitrates = b43legacy_b_ratetable,
153  .n_bitrates = b43legacy_b_ratetable_size,
154 };
155 
156 static struct ieee80211_supported_band b43legacy_band_2GHz_GPHY = {
157  .channels = b43legacy_bg_chantable,
158  .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
159  .bitrates = b43legacy_g_ratetable,
160  .n_bitrates = b43legacy_g_ratetable_size,
161 };
162 
163 static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
164 static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
165 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
166 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
167 
168 
169 static int b43legacy_ratelimit(struct b43legacy_wl *wl)
170 {
171  if (!wl || !wl->current_dev)
172  return 1;
173  if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
174  return 1;
175  /* We are up and running.
176  * Ratelimit the messages to avoid DoS over the net. */
177  return net_ratelimit();
178 }
179 
180 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
181 {
182  struct va_format vaf;
183  va_list args;
184 
185  if (!b43legacy_ratelimit(wl))
186  return;
187 
188  va_start(args, fmt);
189 
190  vaf.fmt = fmt;
191  vaf.va = &args;
192 
193  printk(KERN_INFO "b43legacy-%s: %pV",
194  (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
195 
196  va_end(args);
197 }
198 
199 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
200 {
201  struct va_format vaf;
202  va_list args;
203 
204  if (!b43legacy_ratelimit(wl))
205  return;
206 
207  va_start(args, fmt);
208 
209  vaf.fmt = fmt;
210  vaf.va = &args;
211 
212  printk(KERN_ERR "b43legacy-%s ERROR: %pV",
213  (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
214 
215  va_end(args);
216 }
217 
218 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
219 {
220  struct va_format vaf;
221  va_list args;
222 
223  if (!b43legacy_ratelimit(wl))
224  return;
225 
226  va_start(args, fmt);
227 
228  vaf.fmt = fmt;
229  vaf.va = &args;
230 
231  printk(KERN_WARNING "b43legacy-%s warning: %pV",
232  (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
233 
234  va_end(args);
235 }
236 
237 #if B43legacy_DEBUG
238 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
239 {
240  struct va_format vaf;
241  va_list args;
242 
243  va_start(args, fmt);
244 
245  vaf.fmt = fmt;
246  vaf.va = &args;
247 
248  printk(KERN_DEBUG "b43legacy-%s debug: %pV",
249  (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
250 
251  va_end(args);
252 }
253 #endif /* DEBUG */
254 
255 static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
256  u32 val)
257 {
258  u32 status;
259 
260  B43legacy_WARN_ON(offset % 4 != 0);
261 
262  status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
263  if (status & B43legacy_MACCTL_BE)
264  val = swab32(val);
265 
266  b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
267  mmiowb();
268  b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
269 }
270 
271 static inline
272 void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
273  u16 routing, u16 offset)
274 {
275  u32 control;
276 
277  /* "offset" is the WORD offset. */
278 
279  control = routing;
280  control <<= 16;
281  control |= offset;
282  b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
283 }
284 
285 u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
286  u16 routing, u16 offset)
287 {
288  u32 ret;
289 
290  if (routing == B43legacy_SHM_SHARED) {
291  B43legacy_WARN_ON((offset & 0x0001) != 0);
292  if (offset & 0x0003) {
293  /* Unaligned access */
294  b43legacy_shm_control_word(dev, routing, offset >> 2);
295  ret = b43legacy_read16(dev,
296  B43legacy_MMIO_SHM_DATA_UNALIGNED);
297  ret <<= 16;
298  b43legacy_shm_control_word(dev, routing,
299  (offset >> 2) + 1);
300  ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
301 
302  return ret;
303  }
304  offset >>= 2;
305  }
306  b43legacy_shm_control_word(dev, routing, offset);
307  ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
308 
309  return ret;
310 }
311 
312 u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
313  u16 routing, u16 offset)
314 {
315  u16 ret;
316 
317  if (routing == B43legacy_SHM_SHARED) {
318  B43legacy_WARN_ON((offset & 0x0001) != 0);
319  if (offset & 0x0003) {
320  /* Unaligned access */
321  b43legacy_shm_control_word(dev, routing, offset >> 2);
322  ret = b43legacy_read16(dev,
323  B43legacy_MMIO_SHM_DATA_UNALIGNED);
324 
325  return ret;
326  }
327  offset >>= 2;
328  }
329  b43legacy_shm_control_word(dev, routing, offset);
330  ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
331 
332  return ret;
333 }
334 
335 void b43legacy_shm_write32(struct b43legacy_wldev *dev,
336  u16 routing, u16 offset,
337  u32 value)
338 {
339  if (routing == B43legacy_SHM_SHARED) {
340  B43legacy_WARN_ON((offset & 0x0001) != 0);
341  if (offset & 0x0003) {
342  /* Unaligned access */
343  b43legacy_shm_control_word(dev, routing, offset >> 2);
344  mmiowb();
345  b43legacy_write16(dev,
346  B43legacy_MMIO_SHM_DATA_UNALIGNED,
347  (value >> 16) & 0xffff);
348  mmiowb();
349  b43legacy_shm_control_word(dev, routing,
350  (offset >> 2) + 1);
351  mmiowb();
352  b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
353  value & 0xffff);
354  return;
355  }
356  offset >>= 2;
357  }
358  b43legacy_shm_control_word(dev, routing, offset);
359  mmiowb();
360  b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
361 }
362 
363 void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
364  u16 value)
365 {
366  if (routing == B43legacy_SHM_SHARED) {
367  B43legacy_WARN_ON((offset & 0x0001) != 0);
368  if (offset & 0x0003) {
369  /* Unaligned access */
370  b43legacy_shm_control_word(dev, routing, offset >> 2);
371  mmiowb();
372  b43legacy_write16(dev,
373  B43legacy_MMIO_SHM_DATA_UNALIGNED,
374  value);
375  return;
376  }
377  offset >>= 2;
378  }
379  b43legacy_shm_control_word(dev, routing, offset);
380  mmiowb();
381  b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
382 }
383 
384 /* Read HostFlags */
385 u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
386 {
387  u32 ret;
388 
389  ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
390  B43legacy_SHM_SH_HOSTFHI);
391  ret <<= 16;
392  ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
393  B43legacy_SHM_SH_HOSTFLO);
394 
395  return ret;
396 }
397 
398 /* Write HostFlags */
399 void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
400 {
401  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
402  B43legacy_SHM_SH_HOSTFLO,
403  (value & 0x0000FFFF));
404  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
405  B43legacy_SHM_SH_HOSTFHI,
406  ((value & 0xFFFF0000) >> 16));
407 }
408 
409 void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
410 {
411  /* We need to be careful. As we read the TSF from multiple
412  * registers, we should take care of register overflows.
413  * In theory, the whole tsf read process should be atomic.
414  * We try to be atomic here, by restaring the read process,
415  * if any of the high registers changed (overflew).
416  */
417  if (dev->dev->id.revision >= 3) {
418  u32 low;
419  u32 high;
420  u32 high2;
421 
422  do {
423  high = b43legacy_read32(dev,
424  B43legacy_MMIO_REV3PLUS_TSF_HIGH);
425  low = b43legacy_read32(dev,
426  B43legacy_MMIO_REV3PLUS_TSF_LOW);
427  high2 = b43legacy_read32(dev,
428  B43legacy_MMIO_REV3PLUS_TSF_HIGH);
429  } while (unlikely(high != high2));
430 
431  *tsf = high;
432  *tsf <<= 32;
433  *tsf |= low;
434  } else {
435  u64 tmp;
436  u16 v0;
437  u16 v1;
438  u16 v2;
439  u16 v3;
440  u16 test1;
441  u16 test2;
442  u16 test3;
443 
444  do {
445  v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
446  v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
447  v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
448  v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
449 
450  test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
451  test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
452  test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
453  } while (v3 != test3 || v2 != test2 || v1 != test1);
454 
455  *tsf = v3;
456  *tsf <<= 48;
457  tmp = v2;
458  tmp <<= 32;
459  *tsf |= tmp;
460  tmp = v1;
461  tmp <<= 16;
462  *tsf |= tmp;
463  *tsf |= v0;
464  }
465 }
466 
467 static void b43legacy_time_lock(struct b43legacy_wldev *dev)
468 {
469  u32 status;
470 
471  status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
472  status |= B43legacy_MACCTL_TBTTHOLD;
473  b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
474  mmiowb();
475 }
476 
477 static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
478 {
479  u32 status;
480 
481  status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
482  status &= ~B43legacy_MACCTL_TBTTHOLD;
483  b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
484 }
485 
486 static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
487 {
488  /* Be careful with the in-progress timer.
489  * First zero out the low register, so we have a full
490  * register-overflow duration to complete the operation.
491  */
492  if (dev->dev->id.revision >= 3) {
493  u32 lo = (tsf & 0x00000000FFFFFFFFULL);
494  u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
495 
496  b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
497  mmiowb();
498  b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
499  hi);
500  mmiowb();
501  b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
502  lo);
503  } else {
504  u16 v0 = (tsf & 0x000000000000FFFFULL);
505  u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
506  u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
507  u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
508 
509  b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
510  mmiowb();
511  b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
512  mmiowb();
513  b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
514  mmiowb();
515  b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
516  mmiowb();
517  b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
518  }
519 }
520 
521 void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
522 {
523  b43legacy_time_lock(dev);
524  b43legacy_tsf_write_locked(dev, tsf);
525  b43legacy_time_unlock(dev);
526 }
527 
528 static
529 void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
530  u16 offset, const u8 *mac)
531 {
532  static const u8 zero_addr[ETH_ALEN] = { 0 };
533  u16 data;
534 
535  if (!mac)
536  mac = zero_addr;
537 
538  offset |= 0x0020;
539  b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
540 
541  data = mac[0];
542  data |= mac[1] << 8;
543  b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
544  data = mac[2];
545  data |= mac[3] << 8;
546  b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
547  data = mac[4];
548  data |= mac[5] << 8;
549  b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
550 }
551 
552 static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
553 {
554  static const u8 zero_addr[ETH_ALEN] = { 0 };
555  const u8 *mac = dev->wl->mac_addr;
556  const u8 *bssid = dev->wl->bssid;
557  u8 mac_bssid[ETH_ALEN * 2];
558  int i;
559  u32 tmp;
560 
561  if (!bssid)
562  bssid = zero_addr;
563  if (!mac)
564  mac = zero_addr;
565 
566  b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
567 
568  memcpy(mac_bssid, mac, ETH_ALEN);
569  memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
570 
571  /* Write our MAC address and BSSID to template ram */
572  for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
573  tmp = (u32)(mac_bssid[i + 0]);
574  tmp |= (u32)(mac_bssid[i + 1]) << 8;
575  tmp |= (u32)(mac_bssid[i + 2]) << 16;
576  tmp |= (u32)(mac_bssid[i + 3]) << 24;
577  b43legacy_ram_write(dev, 0x20 + i, tmp);
578  b43legacy_ram_write(dev, 0x78 + i, tmp);
579  b43legacy_ram_write(dev, 0x478 + i, tmp);
580  }
581 }
582 
583 static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
584 {
585  b43legacy_write_mac_bssid_templates(dev);
586  b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
587  dev->wl->mac_addr);
588 }
589 
590 static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
591  u16 slot_time)
592 {
593  /* slot_time is in usec. */
594  if (dev->phy.type != B43legacy_PHYTYPE_G)
595  return;
596  b43legacy_write16(dev, 0x684, 510 + slot_time);
597  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
598  slot_time);
599 }
600 
601 static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
602 {
603  b43legacy_set_slot_time(dev, 9);
604 }
605 
606 static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
607 {
608  b43legacy_set_slot_time(dev, 20);
609 }
610 
611 /* Synchronize IRQ top- and bottom-half.
612  * IRQs must be masked before calling this.
613  * This must not be called with the irq_lock held.
614  */
615 static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
616 {
617  synchronize_irq(dev->dev->irq);
618  tasklet_kill(&dev->isr_tasklet);
619 }
620 
621 /* DummyTransmission function, as documented on
622  * http://bcm-specs.sipsolutions.net/DummyTransmission
623  */
624 void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
625 {
626  struct b43legacy_phy *phy = &dev->phy;
627  unsigned int i;
628  unsigned int max_loop;
629  u16 value;
630  u32 buffer[5] = {
631  0x00000000,
632  0x00D40000,
633  0x00000000,
634  0x01000000,
635  0x00000000,
636  };
637 
638  switch (phy->type) {
639  case B43legacy_PHYTYPE_B:
640  case B43legacy_PHYTYPE_G:
641  max_loop = 0xFA;
642  buffer[0] = 0x000B846E;
643  break;
644  default:
645  B43legacy_BUG_ON(1);
646  return;
647  }
648 
649  for (i = 0; i < 5; i++)
650  b43legacy_ram_write(dev, i * 4, buffer[i]);
651 
652  /* dummy read follows */
653  b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
654 
655  b43legacy_write16(dev, 0x0568, 0x0000);
656  b43legacy_write16(dev, 0x07C0, 0x0000);
657  b43legacy_write16(dev, 0x050C, 0x0000);
658  b43legacy_write16(dev, 0x0508, 0x0000);
659  b43legacy_write16(dev, 0x050A, 0x0000);
660  b43legacy_write16(dev, 0x054C, 0x0000);
661  b43legacy_write16(dev, 0x056A, 0x0014);
662  b43legacy_write16(dev, 0x0568, 0x0826);
663  b43legacy_write16(dev, 0x0500, 0x0000);
664  b43legacy_write16(dev, 0x0502, 0x0030);
665 
666  if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
667  b43legacy_radio_write16(dev, 0x0051, 0x0017);
668  for (i = 0x00; i < max_loop; i++) {
669  value = b43legacy_read16(dev, 0x050E);
670  if (value & 0x0080)
671  break;
672  udelay(10);
673  }
674  for (i = 0x00; i < 0x0A; i++) {
675  value = b43legacy_read16(dev, 0x050E);
676  if (value & 0x0400)
677  break;
678  udelay(10);
679  }
680  for (i = 0x00; i < 0x0A; i++) {
681  value = b43legacy_read16(dev, 0x0690);
682  if (!(value & 0x0100))
683  break;
684  udelay(10);
685  }
686  if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
687  b43legacy_radio_write16(dev, 0x0051, 0x0037);
688 }
689 
690 /* Turn the Analog ON/OFF */
691 static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
692 {
693  b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
694 }
695 
696 void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
697 {
698  u32 tmslow;
699  u32 macctl;
700 
701  flags |= B43legacy_TMSLOW_PHYCLKEN;
702  flags |= B43legacy_TMSLOW_PHYRESET;
703  ssb_device_enable(dev->dev, flags);
704  msleep(2); /* Wait for the PLL to turn on. */
705 
706  /* Now take the PHY out of Reset again */
707  tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
708  tmslow |= SSB_TMSLOW_FGC;
709  tmslow &= ~B43legacy_TMSLOW_PHYRESET;
710  ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
711  ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
712  msleep(1);
713  tmslow &= ~SSB_TMSLOW_FGC;
714  ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
715  ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
716  msleep(1);
717 
718  /* Turn Analog ON */
719  b43legacy_switch_analog(dev, 1);
720 
721  macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
722  macctl &= ~B43legacy_MACCTL_GMODE;
723  if (flags & B43legacy_TMSLOW_GMODE) {
724  macctl |= B43legacy_MACCTL_GMODE;
725  dev->phy.gmode = true;
726  } else
727  dev->phy.gmode = false;
728  macctl |= B43legacy_MACCTL_IHR_ENABLED;
729  b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
730 }
731 
732 static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
733 {
734  u32 v0;
735  u32 v1;
736  u16 tmp;
737  struct b43legacy_txstatus stat;
738 
739  while (1) {
740  v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
741  if (!(v0 & 0x00000001))
742  break;
743  v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
744 
745  stat.cookie = (v0 >> 16);
746  stat.seq = (v1 & 0x0000FFFF);
747  stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
748  tmp = (v0 & 0x0000FFFF);
749  stat.frame_count = ((tmp & 0xF000) >> 12);
750  stat.rts_count = ((tmp & 0x0F00) >> 8);
751  stat.supp_reason = ((tmp & 0x001C) >> 2);
752  stat.pm_indicated = !!(tmp & 0x0080);
753  stat.intermediate = !!(tmp & 0x0040);
754  stat.for_ampdu = !!(tmp & 0x0020);
755  stat.acked = !!(tmp & 0x0002);
756 
757  b43legacy_handle_txstatus(dev, &stat);
758  }
759 }
760 
761 static void drain_txstatus_queue(struct b43legacy_wldev *dev)
762 {
763  u32 dummy;
764 
765  if (dev->dev->id.revision < 5)
766  return;
767  /* Read all entries from the microcode TXstatus FIFO
768  * and throw them away.
769  */
770  while (1) {
771  dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
772  if (!(dummy & 0x00000001))
773  break;
774  dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
775  }
776 }
777 
778 static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
779 {
780  u32 val = 0;
781 
782  val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
783  val <<= 16;
784  val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
785 
786  return val;
787 }
788 
789 static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
790 {
791  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
792  (jssi & 0x0000FFFF));
793  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
794  (jssi & 0xFFFF0000) >> 16);
795 }
796 
797 static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
798 {
799  b43legacy_jssi_write(dev, 0x7F7F7F7F);
800  b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
801  b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
802  | B43legacy_MACCMD_BGNOISE);
803  B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
804  dev->phy.channel);
805 }
806 
807 static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
808 {
809  /* Top half of Link Quality calculation. */
810 
811  if (dev->noisecalc.calculation_running)
812  return;
813  dev->noisecalc.channel_at_start = dev->phy.channel;
814  dev->noisecalc.calculation_running = true;
815  dev->noisecalc.nr_samples = 0;
816 
817  b43legacy_generate_noise_sample(dev);
818 }
819 
820 static void handle_irq_noise(struct b43legacy_wldev *dev)
821 {
822  struct b43legacy_phy *phy = &dev->phy;
823  u16 tmp;
824  u8 noise[4];
825  u8 i;
826  u8 j;
827  s32 average;
828 
829  /* Bottom half of Link Quality calculation. */
830 
831  B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
832  if (dev->noisecalc.channel_at_start != phy->channel)
833  goto drop_calculation;
834  *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
835  if (noise[0] == 0x7F || noise[1] == 0x7F ||
836  noise[2] == 0x7F || noise[3] == 0x7F)
837  goto generate_new;
838 
839  /* Get the noise samples. */
840  B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
841  i = dev->noisecalc.nr_samples;
842  noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
843  noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
844  noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
845  noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
846  dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
847  dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
848  dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
849  dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
850  dev->noisecalc.nr_samples++;
851  if (dev->noisecalc.nr_samples == 8) {
852  /* Calculate the Link Quality by the noise samples. */
853  average = 0;
854  for (i = 0; i < 8; i++) {
855  for (j = 0; j < 4; j++)
856  average += dev->noisecalc.samples[i][j];
857  }
858  average /= (8 * 4);
859  average *= 125;
860  average += 64;
861  average /= 128;
862  tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
863  0x40C);
864  tmp = (tmp / 128) & 0x1F;
865  if (tmp >= 8)
866  average += 2;
867  else
868  average -= 25;
869  if (tmp == 8)
870  average -= 72;
871  else
872  average -= 48;
873 
874  dev->stats.link_noise = average;
875 drop_calculation:
876  dev->noisecalc.calculation_running = false;
877  return;
878  }
879 generate_new:
880  b43legacy_generate_noise_sample(dev);
881 }
882 
883 static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
884 {
885  if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
886  /* TODO: PS TBTT */
887  } else {
888  if (1/*FIXME: the last PSpoll frame was sent successfully */)
889  b43legacy_power_saving_ctl_bits(dev, -1, -1);
890  }
891  if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
892  dev->dfq_valid = true;
893 }
894 
895 static void handle_irq_atim_end(struct b43legacy_wldev *dev)
896 {
897  if (dev->dfq_valid) {
898  b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
899  b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
900  | B43legacy_MACCMD_DFQ_VALID);
901  dev->dfq_valid = false;
902  }
903 }
904 
905 static void handle_irq_pmq(struct b43legacy_wldev *dev)
906 {
907  u32 tmp;
908 
909  /* TODO: AP mode. */
910 
911  while (1) {
912  tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
913  if (!(tmp & 0x00000008))
914  break;
915  }
916  /* 16bit write is odd, but correct. */
917  b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
918 }
919 
920 static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
921  const u8 *data, u16 size,
922  u16 ram_offset,
923  u16 shm_size_offset, u8 rate)
924 {
925  u32 i;
926  u32 tmp;
927  struct b43legacy_plcp_hdr4 plcp;
928 
929  plcp.data = 0;
930  b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
931  b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
932  ram_offset += sizeof(u32);
933  /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
934  * So leave the first two bytes of the next write blank.
935  */
936  tmp = (u32)(data[0]) << 16;
937  tmp |= (u32)(data[1]) << 24;
938  b43legacy_ram_write(dev, ram_offset, tmp);
939  ram_offset += sizeof(u32);
940  for (i = 2; i < size; i += sizeof(u32)) {
941  tmp = (u32)(data[i + 0]);
942  if (i + 1 < size)
943  tmp |= (u32)(data[i + 1]) << 8;
944  if (i + 2 < size)
945  tmp |= (u32)(data[i + 2]) << 16;
946  if (i + 3 < size)
947  tmp |= (u32)(data[i + 3]) << 24;
948  b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
949  }
950  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
951  size + sizeof(struct b43legacy_plcp_hdr6));
952 }
953 
954 /* Convert a b43legacy antenna number value to the PHY TX control value. */
955 static u16 b43legacy_antenna_to_phyctl(int antenna)
956 {
957  switch (antenna) {
958  case B43legacy_ANTENNA0:
959  return B43legacy_TX4_PHY_ANT0;
960  case B43legacy_ANTENNA1:
961  return B43legacy_TX4_PHY_ANT1;
962  }
963  return B43legacy_TX4_PHY_ANTLAST;
964 }
965 
966 static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
967  u16 ram_offset,
968  u16 shm_size_offset)
969 {
970 
971  unsigned int i, len, variable_len;
972  const struct ieee80211_mgmt *bcn;
973  const u8 *ie;
974  bool tim_found = false;
975  unsigned int rate;
976  u16 ctl;
977  int antenna;
978  struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
979 
980  bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
981  len = min((size_t)dev->wl->current_beacon->len,
982  0x200 - sizeof(struct b43legacy_plcp_hdr6));
983  rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
984 
985  b43legacy_write_template_common(dev, (const u8 *)bcn, len, ram_offset,
986  shm_size_offset, rate);
987 
988  /* Write the PHY TX control parameters. */
989  antenna = B43legacy_ANTENNA_DEFAULT;
990  antenna = b43legacy_antenna_to_phyctl(antenna);
991  ctl = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
992  B43legacy_SHM_SH_BEACPHYCTL);
993  /* We can't send beacons with short preamble. Would get PHY errors. */
994  ctl &= ~B43legacy_TX4_PHY_SHORTPRMBL;
995  ctl &= ~B43legacy_TX4_PHY_ANT;
996  ctl &= ~B43legacy_TX4_PHY_ENC;
997  ctl |= antenna;
998  ctl |= B43legacy_TX4_PHY_ENC_CCK;
999  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1000  B43legacy_SHM_SH_BEACPHYCTL, ctl);
1001 
1002  /* Find the position of the TIM and the DTIM_period value
1003  * and write them to SHM. */
1004  ie = bcn->u.beacon.variable;
1005  variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1006  for (i = 0; i < variable_len - 2; ) {
1007  uint8_t ie_id, ie_len;
1008 
1009  ie_id = ie[i];
1010  ie_len = ie[i + 1];
1011  if (ie_id == 5) {
1012  u16 tim_position;
1013  u16 dtim_period;
1014  /* This is the TIM Information Element */
1015 
1016  /* Check whether the ie_len is in the beacon data range. */
1017  if (variable_len < ie_len + 2 + i)
1018  break;
1019  /* A valid TIM is at least 4 bytes long. */
1020  if (ie_len < 4)
1021  break;
1022  tim_found = true;
1023 
1024  tim_position = sizeof(struct b43legacy_plcp_hdr6);
1025  tim_position += offsetof(struct ieee80211_mgmt,
1026  u.beacon.variable);
1027  tim_position += i;
1028 
1029  dtim_period = ie[i + 3];
1030 
1031  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1032  B43legacy_SHM_SH_TIMPOS, tim_position);
1033  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1034  B43legacy_SHM_SH_DTIMP, dtim_period);
1035  break;
1036  }
1037  i += ie_len + 2;
1038  }
1039  if (!tim_found) {
1040  b43legacywarn(dev->wl, "Did not find a valid TIM IE in the "
1041  "beacon template packet. AP or IBSS operation "
1042  "may be broken.\n");
1043  } else
1044  b43legacydbg(dev->wl, "Updated beacon template\n");
1045 }
1046 
1047 static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
1048  u16 shm_offset, u16 size,
1049  struct ieee80211_rate *rate)
1050 {
1051  struct b43legacy_plcp_hdr4 plcp;
1052  u32 tmp;
1053  __le16 dur;
1054 
1055  plcp.data = 0;
1056  b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1057  dur = ieee80211_generic_frame_duration(dev->wl->hw,
1058  dev->wl->vif,
1059  IEEE80211_BAND_2GHZ,
1060  size,
1061  rate);
1062  /* Write PLCP in two parts and timing for packet transfer */
1063  tmp = le32_to_cpu(plcp.data);
1064  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
1065  tmp & 0xFFFF);
1066  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
1067  tmp >> 16);
1068  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
1069  le16_to_cpu(dur));
1070 }
1071 
1072 /* Instead of using custom probe response template, this function
1073  * just patches custom beacon template by:
1074  * 1) Changing packet type
1075  * 2) Patching duration field
1076  * 3) Stripping TIM
1077  */
1078 static const u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
1079  u16 *dest_size,
1080  struct ieee80211_rate *rate)
1081 {
1082  const u8 *src_data;
1083  u8 *dest_data;
1084  u16 src_size, elem_size, src_pos, dest_pos;
1085  __le16 dur;
1086  struct ieee80211_hdr *hdr;
1087  size_t ie_start;
1088 
1089  src_size = dev->wl->current_beacon->len;
1090  src_data = (const u8 *)dev->wl->current_beacon->data;
1091 
1092  /* Get the start offset of the variable IEs in the packet. */
1093  ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1094  B43legacy_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt,
1095  u.beacon.variable));
1096 
1097  if (B43legacy_WARN_ON(src_size < ie_start))
1098  return NULL;
1099 
1100  dest_data = kmalloc(src_size, GFP_ATOMIC);
1101  if (unlikely(!dest_data))
1102  return NULL;
1103 
1104  /* Copy the static data and all Information Elements, except the TIM. */
1105  memcpy(dest_data, src_data, ie_start);
1106  src_pos = ie_start;
1107  dest_pos = ie_start;
1108  for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1109  elem_size = src_data[src_pos + 1] + 2;
1110  if (src_data[src_pos] == 5) {
1111  /* This is the TIM. */
1112  continue;
1113  }
1114  memcpy(dest_data + dest_pos, src_data + src_pos, elem_size);
1115  dest_pos += elem_size;
1116  }
1117  *dest_size = dest_pos;
1118  hdr = (struct ieee80211_hdr *)dest_data;
1119 
1120  /* Set the frame control. */
1121  hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1122  IEEE80211_STYPE_PROBE_RESP);
1123  dur = ieee80211_generic_frame_duration(dev->wl->hw,
1124  dev->wl->vif,
1125  IEEE80211_BAND_2GHZ,
1126  *dest_size,
1127  rate);
1128  hdr->duration_id = dur;
1129 
1130  return dest_data;
1131 }
1132 
1133 static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
1134  u16 ram_offset,
1135  u16 shm_size_offset,
1136  struct ieee80211_rate *rate)
1137 {
1138  const u8 *probe_resp_data;
1139  u16 size;
1140 
1141  size = dev->wl->current_beacon->len;
1142  probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
1143  if (unlikely(!probe_resp_data))
1144  return;
1145 
1146  /* Looks like PLCP headers plus packet timings are stored for
1147  * all possible basic rates
1148  */
1149  b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
1150  &b43legacy_b_ratetable[0]);
1151  b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
1152  &b43legacy_b_ratetable[1]);
1153  b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
1154  &b43legacy_b_ratetable[2]);
1155  b43legacy_write_probe_resp_plcp(dev, 0x350, size,
1156  &b43legacy_b_ratetable[3]);
1157 
1158  size = min((size_t)size,
1159  0x200 - sizeof(struct b43legacy_plcp_hdr6));
1160  b43legacy_write_template_common(dev, probe_resp_data,
1161  size, ram_offset,
1162  shm_size_offset, rate->hw_value);
1163  kfree(probe_resp_data);
1164 }
1165 
1166 static void b43legacy_upload_beacon0(struct b43legacy_wldev *dev)
1167 {
1168  struct b43legacy_wl *wl = dev->wl;
1169 
1170  if (wl->beacon0_uploaded)
1171  return;
1172  b43legacy_write_beacon_template(dev, 0x68, 0x18);
1173  /* FIXME: Probe resp upload doesn't really belong here,
1174  * but we don't use that feature anyway. */
1175  b43legacy_write_probe_resp_template(dev, 0x268, 0x4A,
1176  &__b43legacy_ratetable[3]);
1177  wl->beacon0_uploaded = true;
1178 }
1179 
1180 static void b43legacy_upload_beacon1(struct b43legacy_wldev *dev)
1181 {
1182  struct b43legacy_wl *wl = dev->wl;
1183 
1184  if (wl->beacon1_uploaded)
1185  return;
1186  b43legacy_write_beacon_template(dev, 0x468, 0x1A);
1187  wl->beacon1_uploaded = true;
1188 }
1189 
1190 static void handle_irq_beacon(struct b43legacy_wldev *dev)
1191 {
1192  struct b43legacy_wl *wl = dev->wl;
1193  u32 cmd, beacon0_valid, beacon1_valid;
1194 
1195  if (!b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
1196  return;
1197 
1198  /* This is the bottom half of the asynchronous beacon update. */
1199 
1200  /* Ignore interrupt in the future. */
1201  dev->irq_mask &= ~B43legacy_IRQ_BEACON;
1202 
1203  cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1204  beacon0_valid = (cmd & B43legacy_MACCMD_BEACON0_VALID);
1205  beacon1_valid = (cmd & B43legacy_MACCMD_BEACON1_VALID);
1206 
1207  /* Schedule interrupt manually, if busy. */
1208  if (beacon0_valid && beacon1_valid) {
1209  b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, B43legacy_IRQ_BEACON);
1210  dev->irq_mask |= B43legacy_IRQ_BEACON;
1211  return;
1212  }
1213 
1214  if (unlikely(wl->beacon_templates_virgin)) {
1215  /* We never uploaded a beacon before.
1216  * Upload both templates now, but only mark one valid. */
1217  wl->beacon_templates_virgin = false;
1218  b43legacy_upload_beacon0(dev);
1219  b43legacy_upload_beacon1(dev);
1220  cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1221  cmd |= B43legacy_MACCMD_BEACON0_VALID;
1222  b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1223  } else {
1224  if (!beacon0_valid) {
1225  b43legacy_upload_beacon0(dev);
1226  cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1227  cmd |= B43legacy_MACCMD_BEACON0_VALID;
1228  b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1229  } else if (!beacon1_valid) {
1230  b43legacy_upload_beacon1(dev);
1231  cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1232  cmd |= B43legacy_MACCMD_BEACON1_VALID;
1233  b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1234  }
1235  }
1236 }
1237 
1238 static void b43legacy_beacon_update_trigger_work(struct work_struct *work)
1239 {
1240  struct b43legacy_wl *wl = container_of(work, struct b43legacy_wl,
1241  beacon_update_trigger);
1242  struct b43legacy_wldev *dev;
1243 
1244  mutex_lock(&wl->mutex);
1245  dev = wl->current_dev;
1246  if (likely(dev && (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED))) {
1247  spin_lock_irq(&wl->irq_lock);
1248  /* Update beacon right away or defer to IRQ. */
1249  handle_irq_beacon(dev);
1250  /* The handler might have updated the IRQ mask. */
1251  b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1252  dev->irq_mask);
1253  mmiowb();
1254  spin_unlock_irq(&wl->irq_lock);
1255  }
1256  mutex_unlock(&wl->mutex);
1257 }
1258 
1259 /* Asynchronously update the packet templates in template RAM.
1260  * Locking: Requires wl->irq_lock to be locked. */
1261 static void b43legacy_update_templates(struct b43legacy_wl *wl)
1262 {
1263  struct sk_buff *beacon;
1264  /* This is the top half of the ansynchronous beacon update. The bottom
1265  * half is the beacon IRQ. Beacon update must be asynchronous to avoid
1266  * sending an invalid beacon. This can happen for example, if the
1267  * firmware transmits a beacon while we are updating it. */
1268 
1269  /* We could modify the existing beacon and set the aid bit in the TIM
1270  * field, but that would probably require resizing and moving of data
1271  * within the beacon template. Simply request a new beacon and let
1272  * mac80211 do the hard work. */
1273  beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1274  if (unlikely(!beacon))
1275  return;
1276 
1277  if (wl->current_beacon)
1278  dev_kfree_skb_any(wl->current_beacon);
1279  wl->current_beacon = beacon;
1280  wl->beacon0_uploaded = false;
1281  wl->beacon1_uploaded = false;
1282  ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1283 }
1284 
1285 static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
1286  u16 beacon_int)
1287 {
1288  b43legacy_time_lock(dev);
1289  if (dev->dev->id.revision >= 3) {
1290  b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_REP,
1291  (beacon_int << 16));
1292  b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_START,
1293  (beacon_int << 10));
1294  } else {
1295  b43legacy_write16(dev, 0x606, (beacon_int >> 6));
1296  b43legacy_write16(dev, 0x610, beacon_int);
1297  }
1298  b43legacy_time_unlock(dev);
1299  b43legacydbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1300 }
1301 
1302 static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
1303 {
1304 }
1305 
1306 /* Interrupt handler bottom-half */
1307 static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
1308 {
1309  u32 reason;
1310  u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1311  u32 merged_dma_reason = 0;
1312  int i;
1313  unsigned long flags;
1314 
1315  spin_lock_irqsave(&dev->wl->irq_lock, flags);
1316 
1317  B43legacy_WARN_ON(b43legacy_status(dev) <
1318  B43legacy_STAT_INITIALIZED);
1319 
1320  reason = dev->irq_reason;
1321  for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1322  dma_reason[i] = dev->dma_reason[i];
1323  merged_dma_reason |= dma_reason[i];
1324  }
1325 
1326  if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
1327  b43legacyerr(dev->wl, "MAC transmission error\n");
1328 
1329  if (unlikely(reason & B43legacy_IRQ_PHY_TXERR)) {
1330  b43legacyerr(dev->wl, "PHY transmission error\n");
1331  rmb();
1332  if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1333  b43legacyerr(dev->wl, "Too many PHY TX errors, "
1334  "restarting the controller\n");
1335  b43legacy_controller_restart(dev, "PHY TX errors");
1336  }
1337  }
1338 
1339  if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
1340  B43legacy_DMAIRQ_NONFATALMASK))) {
1341  if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
1342  b43legacyerr(dev->wl, "Fatal DMA error: "
1343  "0x%08X, 0x%08X, 0x%08X, "
1344  "0x%08X, 0x%08X, 0x%08X\n",
1345  dma_reason[0], dma_reason[1],
1346  dma_reason[2], dma_reason[3],
1347  dma_reason[4], dma_reason[5]);
1348  b43legacy_controller_restart(dev, "DMA error");
1349  mmiowb();
1350  spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1351  return;
1352  }
1353  if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
1354  b43legacyerr(dev->wl, "DMA error: "
1355  "0x%08X, 0x%08X, 0x%08X, "
1356  "0x%08X, 0x%08X, 0x%08X\n",
1357  dma_reason[0], dma_reason[1],
1358  dma_reason[2], dma_reason[3],
1359  dma_reason[4], dma_reason[5]);
1360  }
1361 
1362  if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
1363  handle_irq_ucode_debug(dev);
1364  if (reason & B43legacy_IRQ_TBTT_INDI)
1365  handle_irq_tbtt_indication(dev);
1366  if (reason & B43legacy_IRQ_ATIM_END)
1367  handle_irq_atim_end(dev);
1368  if (reason & B43legacy_IRQ_BEACON)
1369  handle_irq_beacon(dev);
1370  if (reason & B43legacy_IRQ_PMQ)
1371  handle_irq_pmq(dev);
1372  if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
1373  ;/*TODO*/
1374  if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
1375  handle_irq_noise(dev);
1376 
1377  /* Check the DMA reason registers for received data. */
1378  if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
1379  if (b43legacy_using_pio(dev))
1380  b43legacy_pio_rx(dev->pio.queue0);
1381  else
1382  b43legacy_dma_rx(dev->dma.rx_ring0);
1383  }
1384  B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
1385  B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
1386  if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
1387  if (b43legacy_using_pio(dev))
1388  b43legacy_pio_rx(dev->pio.queue3);
1389  else
1390  b43legacy_dma_rx(dev->dma.rx_ring3);
1391  }
1392  B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
1393  B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
1394 
1395  if (reason & B43legacy_IRQ_TX_OK)
1396  handle_irq_transmit_status(dev);
1397 
1398  b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1399  mmiowb();
1400  spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1401 }
1402 
1403 static void pio_irq_workaround(struct b43legacy_wldev *dev,
1404  u16 base, int queueidx)
1405 {
1406  u16 rxctl;
1407 
1408  rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
1409  if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
1410  dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
1411  else
1412  dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
1413 }
1414 
1415 static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
1416 {
1417  if (b43legacy_using_pio(dev) &&
1418  (dev->dev->id.revision < 3) &&
1419  (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
1420  /* Apply a PIO specific workaround to the dma_reasons */
1421  pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
1422  pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
1423  pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
1424  pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
1425  }
1426 
1427  b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
1428 
1429  b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
1430  dev->dma_reason[0]);
1431  b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
1432  dev->dma_reason[1]);
1433  b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
1434  dev->dma_reason[2]);
1435  b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
1436  dev->dma_reason[3]);
1437  b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
1438  dev->dma_reason[4]);
1439  b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
1440  dev->dma_reason[5]);
1441 }
1442 
1443 /* Interrupt handler top-half */
1444 static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
1445 {
1446  irqreturn_t ret = IRQ_NONE;
1447  struct b43legacy_wldev *dev = dev_id;
1448  u32 reason;
1449 
1450  B43legacy_WARN_ON(!dev);
1451 
1452  spin_lock(&dev->wl->irq_lock);
1453 
1454  if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
1455  /* This can only happen on shared IRQ lines. */
1456  goto out;
1457  reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1458  if (reason == 0xffffffff) /* shared IRQ */
1459  goto out;
1460  ret = IRQ_HANDLED;
1461  reason &= dev->irq_mask;
1462  if (!reason)
1463  goto out;
1464 
1465  dev->dma_reason[0] = b43legacy_read32(dev,
1466  B43legacy_MMIO_DMA0_REASON)
1467  & 0x0001DC00;
1468  dev->dma_reason[1] = b43legacy_read32(dev,
1469  B43legacy_MMIO_DMA1_REASON)
1470  & 0x0000DC00;
1471  dev->dma_reason[2] = b43legacy_read32(dev,
1472  B43legacy_MMIO_DMA2_REASON)
1473  & 0x0000DC00;
1474  dev->dma_reason[3] = b43legacy_read32(dev,
1475  B43legacy_MMIO_DMA3_REASON)
1476  & 0x0001DC00;
1477  dev->dma_reason[4] = b43legacy_read32(dev,
1478  B43legacy_MMIO_DMA4_REASON)
1479  & 0x0000DC00;
1480  dev->dma_reason[5] = b43legacy_read32(dev,
1481  B43legacy_MMIO_DMA5_REASON)
1482  & 0x0000DC00;
1483 
1484  b43legacy_interrupt_ack(dev, reason);
1485  /* Disable all IRQs. They are enabled again in the bottom half. */
1486  b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1487  /* Save the reason code and call our bottom half. */
1488  dev->irq_reason = reason;
1489  tasklet_schedule(&dev->isr_tasklet);
1490 out:
1491  mmiowb();
1492  spin_unlock(&dev->wl->irq_lock);
1493 
1494  return ret;
1495 }
1496 
1497 static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
1498 {
1499  release_firmware(dev->fw.ucode);
1500  dev->fw.ucode = NULL;
1501  release_firmware(dev->fw.pcm);
1502  dev->fw.pcm = NULL;
1503  release_firmware(dev->fw.initvals);
1504  dev->fw.initvals = NULL;
1505  release_firmware(dev->fw.initvals_band);
1506  dev->fw.initvals_band = NULL;
1507 }
1508 
1509 static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
1510 {
1511  b43legacyerr(wl, "You must go to http://wireless.kernel.org/en/users/"
1512  "Drivers/b43#devicefirmware "
1513  "and download the correct firmware (version 3).\n");
1514 }
1515 
1516 static int do_request_fw(struct b43legacy_wldev *dev,
1517  const char *name,
1518  const struct firmware **fw)
1519 {
1520  char path[sizeof(modparam_fwpostfix) + 32];
1521  struct b43legacy_fw_header *hdr;
1522  u32 size;
1523  int err;
1524 
1525  if (!name)
1526  return 0;
1527 
1528  snprintf(path, ARRAY_SIZE(path),
1529  "b43legacy%s/%s.fw",
1530  modparam_fwpostfix, name);
1531  err = request_firmware(fw, path, dev->dev->dev);
1532  if (err) {
1533  b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
1534  "or load failed.\n", path);
1535  return err;
1536  }
1537  if ((*fw)->size < sizeof(struct b43legacy_fw_header))
1538  goto err_format;
1539  hdr = (struct b43legacy_fw_header *)((*fw)->data);
1540  switch (hdr->type) {
1541  case B43legacy_FW_TYPE_UCODE:
1542  case B43legacy_FW_TYPE_PCM:
1543  size = be32_to_cpu(hdr->size);
1544  if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
1545  goto err_format;
1546  /* fallthrough */
1547  case B43legacy_FW_TYPE_IV:
1548  if (hdr->ver != 1)
1549  goto err_format;
1550  break;
1551  default:
1552  goto err_format;
1553  }
1554 
1555  return err;
1556 
1557 err_format:
1558  b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
1559  return -EPROTO;
1560 }
1561 
1562 static int b43legacy_one_core_attach(struct ssb_device *dev,
1563  struct b43legacy_wl *wl);
1564 static void b43legacy_one_core_detach(struct ssb_device *dev);
1565 
1566 static void b43legacy_request_firmware(struct work_struct *work)
1567 {
1568  struct b43legacy_wl *wl = container_of(work,
1569  struct b43legacy_wl, firmware_load);
1570  struct b43legacy_wldev *dev = wl->current_dev;
1571  struct b43legacy_firmware *fw = &dev->fw;
1572  const u8 rev = dev->dev->id.revision;
1573  const char *filename;
1574  int err;
1575 
1576  if (!fw->ucode) {
1577  if (rev == 2)
1578  filename = "ucode2";
1579  else if (rev == 4)
1580  filename = "ucode4";
1581  else
1582  filename = "ucode5";
1583  err = do_request_fw(dev, filename, &fw->ucode);
1584  if (err)
1585  goto err_load;
1586  }
1587  if (!fw->pcm) {
1588  if (rev < 5)
1589  filename = "pcm4";
1590  else
1591  filename = "pcm5";
1592  err = do_request_fw(dev, filename, &fw->pcm);
1593  if (err)
1594  goto err_load;
1595  }
1596  if (!fw->initvals) {
1597  switch (dev->phy.type) {
1598  case B43legacy_PHYTYPE_B:
1599  case B43legacy_PHYTYPE_G:
1600  if ((rev >= 5) && (rev <= 10))
1601  filename = "b0g0initvals5";
1602  else if (rev == 2 || rev == 4)
1603  filename = "b0g0initvals2";
1604  else
1605  goto err_no_initvals;
1606  break;
1607  default:
1608  goto err_no_initvals;
1609  }
1610  err = do_request_fw(dev, filename, &fw->initvals);
1611  if (err)
1612  goto err_load;
1613  }
1614  if (!fw->initvals_band) {
1615  switch (dev->phy.type) {
1616  case B43legacy_PHYTYPE_B:
1617  case B43legacy_PHYTYPE_G:
1618  if ((rev >= 5) && (rev <= 10))
1619  filename = "b0g0bsinitvals5";
1620  else if (rev >= 11)
1621  filename = NULL;
1622  else if (rev == 2 || rev == 4)
1623  filename = NULL;
1624  else
1625  goto err_no_initvals;
1626  break;
1627  default:
1628  goto err_no_initvals;
1629  }
1630  err = do_request_fw(dev, filename, &fw->initvals_band);
1631  if (err)
1632  goto err_load;
1633  }
1634  err = ieee80211_register_hw(wl->hw);
1635  if (err)
1636  goto err_one_core_detach;
1637  return;
1638 
1639 err_one_core_detach:
1640  b43legacy_one_core_detach(dev->dev);
1641  goto error;
1642 
1643 err_load:
1644  b43legacy_print_fw_helptext(dev->wl);
1645  goto error;
1646 
1647 err_no_initvals:
1648  err = -ENODEV;
1649  b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
1650  "core rev %u\n", dev->phy.type, rev);
1651  goto error;
1652 
1653 error:
1654  b43legacy_release_firmware(dev);
1655  return;
1656 }
1657 
1658 static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
1659 {
1660  struct wiphy *wiphy = dev->wl->hw->wiphy;
1661  const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1662  const __be32 *data;
1663  unsigned int i;
1664  unsigned int len;
1665  u16 fwrev;
1666  u16 fwpatch;
1667  u16 fwdate;
1668  u16 fwtime;
1669  u32 tmp, macctl;
1670  int err = 0;
1671 
1672  /* Jump the microcode PSM to offset 0 */
1673  macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1674  B43legacy_WARN_ON(macctl & B43legacy_MACCTL_PSM_RUN);
1675  macctl |= B43legacy_MACCTL_PSM_JMP0;
1676  b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1677  /* Zero out all microcode PSM registers and shared memory. */
1678  for (i = 0; i < 64; i++)
1679  b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, i, 0);
1680  for (i = 0; i < 4096; i += 2)
1681  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, i, 0);
1682 
1683  /* Upload Microcode. */
1684  data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1685  len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1686  b43legacy_shm_control_word(dev,
1687  B43legacy_SHM_UCODE |
1688  B43legacy_SHM_AUTOINC_W,
1689  0x0000);
1690  for (i = 0; i < len; i++) {
1691  b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1692  be32_to_cpu(data[i]));
1693  udelay(10);
1694  }
1695 
1696  if (dev->fw.pcm) {
1697  /* Upload PCM data. */
1698  data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1699  len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1700  b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
1701  b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
1702  /* No need for autoinc bit in SHM_HW */
1703  b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
1704  for (i = 0; i < len; i++) {
1705  b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1706  be32_to_cpu(data[i]));
1707  udelay(10);
1708  }
1709  }
1710 
1711  b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1712  B43legacy_IRQ_ALL);
1713 
1714  /* Start the microcode PSM */
1715  macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1716  macctl &= ~B43legacy_MACCTL_PSM_JMP0;
1717  macctl |= B43legacy_MACCTL_PSM_RUN;
1718  b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1719 
1720  /* Wait for the microcode to load and respond */
1721  i = 0;
1722  while (1) {
1723  tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1724  if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
1725  break;
1726  i++;
1727  if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
1728  b43legacyerr(dev->wl, "Microcode not responding\n");
1729  b43legacy_print_fw_helptext(dev->wl);
1730  err = -ENODEV;
1731  goto error;
1732  }
1733  msleep_interruptible(50);
1734  if (signal_pending(current)) {
1735  err = -EINTR;
1736  goto error;
1737  }
1738  }
1739  /* dummy read follows */
1740  b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1741 
1742  /* Get and check the revisions. */
1743  fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1744  B43legacy_SHM_SH_UCODEREV);
1745  fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1746  B43legacy_SHM_SH_UCODEPATCH);
1747  fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1748  B43legacy_SHM_SH_UCODEDATE);
1749  fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1750  B43legacy_SHM_SH_UCODETIME);
1751 
1752  if (fwrev > 0x128) {
1753  b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
1754  " Only firmware from binary drivers version 3.x"
1755  " is supported. You must change your firmware"
1756  " files.\n");
1757  b43legacy_print_fw_helptext(dev->wl);
1758  err = -EOPNOTSUPP;
1759  goto error;
1760  }
1761  b43legacyinfo(dev->wl, "Loading firmware version 0x%X, patch level %u "
1762  "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
1763  (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1764  (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F,
1765  fwtime & 0x1F);
1766 
1767  dev->fw.rev = fwrev;
1768  dev->fw.patch = fwpatch;
1769 
1770  snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
1771  dev->fw.rev, dev->fw.patch);
1772  wiphy->hw_version = dev->dev->id.coreid;
1773 
1774  return 0;
1775 
1776 error:
1777  macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1778  macctl &= ~B43legacy_MACCTL_PSM_RUN;
1779  macctl |= B43legacy_MACCTL_PSM_JMP0;
1780  b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1781 
1782  return err;
1783 }
1784 
1785 static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
1786  const struct b43legacy_iv *ivals,
1787  size_t count,
1788  size_t array_size)
1789 {
1790  const struct b43legacy_iv *iv;
1791  u16 offset;
1792  size_t i;
1793  bool bit32;
1794 
1795  BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
1796  iv = ivals;
1797  for (i = 0; i < count; i++) {
1798  if (array_size < sizeof(iv->offset_size))
1799  goto err_format;
1800  array_size -= sizeof(iv->offset_size);
1801  offset = be16_to_cpu(iv->offset_size);
1802  bit32 = !!(offset & B43legacy_IV_32BIT);
1803  offset &= B43legacy_IV_OFFSET_MASK;
1804  if (offset >= 0x1000)
1805  goto err_format;
1806  if (bit32) {
1807  u32 value;
1808 
1809  if (array_size < sizeof(iv->data.d32))
1810  goto err_format;
1811  array_size -= sizeof(iv->data.d32);
1812 
1813  value = get_unaligned_be32(&iv->data.d32);
1814  b43legacy_write32(dev, offset, value);
1815 
1816  iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1817  sizeof(__be16) +
1818  sizeof(__be32));
1819  } else {
1820  u16 value;
1821 
1822  if (array_size < sizeof(iv->data.d16))
1823  goto err_format;
1824  array_size -= sizeof(iv->data.d16);
1825 
1826  value = be16_to_cpu(iv->data.d16);
1827  b43legacy_write16(dev, offset, value);
1828 
1829  iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1830  sizeof(__be16) +
1831  sizeof(__be16));
1832  }
1833  }
1834  if (array_size)
1835  goto err_format;
1836 
1837  return 0;
1838 
1839 err_format:
1840  b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
1841  b43legacy_print_fw_helptext(dev->wl);
1842 
1843  return -EPROTO;
1844 }
1845 
1846 static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
1847 {
1848  const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1849  const struct b43legacy_fw_header *hdr;
1850  struct b43legacy_firmware *fw = &dev->fw;
1851  const struct b43legacy_iv *ivals;
1852  size_t count;
1853  int err;
1854 
1855  hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
1856  ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
1857  count = be32_to_cpu(hdr->size);
1858  err = b43legacy_write_initvals(dev, ivals, count,
1859  fw->initvals->size - hdr_len);
1860  if (err)
1861  goto out;
1862  if (fw->initvals_band) {
1863  hdr = (const struct b43legacy_fw_header *)
1864  (fw->initvals_band->data);
1865  ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
1866  + hdr_len);
1867  count = be32_to_cpu(hdr->size);
1868  err = b43legacy_write_initvals(dev, ivals, count,
1869  fw->initvals_band->size - hdr_len);
1870  if (err)
1871  goto out;
1872  }
1873 out:
1874 
1875  return err;
1876 }
1877 
1878 /* Initialize the GPIOs
1879  * http://bcm-specs.sipsolutions.net/GPIO
1880  */
1881 static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
1882 {
1883  struct ssb_bus *bus = dev->dev->bus;
1884  struct ssb_device *gpiodev, *pcidev = NULL;
1885  u32 mask;
1886  u32 set;
1887 
1888  b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1889  b43legacy_read32(dev,
1890  B43legacy_MMIO_MACCTL)
1891  & 0xFFFF3FFF);
1892 
1893  b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1894  b43legacy_read16(dev,
1895  B43legacy_MMIO_GPIO_MASK)
1896  | 0x000F);
1897 
1898  mask = 0x0000001F;
1899  set = 0x0000000F;
1900  if (dev->dev->bus->chip_id == 0x4301) {
1901  mask |= 0x0060;
1902  set |= 0x0060;
1903  }
1904  if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
1905  b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1906  b43legacy_read16(dev,
1907  B43legacy_MMIO_GPIO_MASK)
1908  | 0x0200);
1909  mask |= 0x0200;
1910  set |= 0x0200;
1911  }
1912  if (dev->dev->id.revision >= 2)
1913  mask |= 0x0010; /* FIXME: This is redundant. */
1914 
1915 #ifdef CONFIG_SSB_DRIVER_PCICORE
1916  pcidev = bus->pcicore.dev;
1917 #endif
1918  gpiodev = bus->chipco.dev ? : pcidev;
1919  if (!gpiodev)
1920  return 0;
1921  ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
1922  (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
1923  & ~mask) | set);
1924 
1925  return 0;
1926 }
1927 
1928 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1929 static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
1930 {
1931  struct ssb_bus *bus = dev->dev->bus;
1932  struct ssb_device *gpiodev, *pcidev = NULL;
1933 
1934 #ifdef CONFIG_SSB_DRIVER_PCICORE
1935  pcidev = bus->pcicore.dev;
1936 #endif
1937  gpiodev = bus->chipco.dev ? : pcidev;
1938  if (!gpiodev)
1939  return;
1940  ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
1941 }
1942 
1943 /* http://bcm-specs.sipsolutions.net/EnableMac */
1944 void b43legacy_mac_enable(struct b43legacy_wldev *dev)
1945 {
1946  dev->mac_suspended--;
1947  B43legacy_WARN_ON(dev->mac_suspended < 0);
1948  B43legacy_WARN_ON(irqs_disabled());
1949  if (dev->mac_suspended == 0) {
1950  b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1951  b43legacy_read32(dev,
1952  B43legacy_MMIO_MACCTL)
1953  | B43legacy_MACCTL_ENABLED);
1954  b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1955  B43legacy_IRQ_MAC_SUSPENDED);
1956  /* the next two are dummy reads */
1957  b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1958  b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1959  b43legacy_power_saving_ctl_bits(dev, -1, -1);
1960 
1961  /* Re-enable IRQs. */
1962  spin_lock_irq(&dev->wl->irq_lock);
1963  b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1964  dev->irq_mask);
1965  spin_unlock_irq(&dev->wl->irq_lock);
1966  }
1967 }
1968 
1969 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1970 void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
1971 {
1972  int i;
1973  u32 tmp;
1974 
1975  might_sleep();
1976  B43legacy_WARN_ON(irqs_disabled());
1977  B43legacy_WARN_ON(dev->mac_suspended < 0);
1978 
1979  if (dev->mac_suspended == 0) {
1980  /* Mask IRQs before suspending MAC. Otherwise
1981  * the MAC stays busy and won't suspend. */
1982  spin_lock_irq(&dev->wl->irq_lock);
1983  b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1984  spin_unlock_irq(&dev->wl->irq_lock);
1985  b43legacy_synchronize_irq(dev);
1986 
1987  b43legacy_power_saving_ctl_bits(dev, -1, 1);
1988  b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1989  b43legacy_read32(dev,
1990  B43legacy_MMIO_MACCTL)
1991  & ~B43legacy_MACCTL_ENABLED);
1992  b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1993  for (i = 40; i; i--) {
1994  tmp = b43legacy_read32(dev,
1995  B43legacy_MMIO_GEN_IRQ_REASON);
1996  if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
1997  goto out;
1998  msleep(1);
1999  }
2000  b43legacyerr(dev->wl, "MAC suspend failed\n");
2001  }
2002 out:
2003  dev->mac_suspended++;
2004 }
2005 
2006 static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
2007 {
2008  struct b43legacy_wl *wl = dev->wl;
2009  u32 ctl;
2010  u16 cfp_pretbtt;
2011 
2012  ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2013  /* Reset status to STA infrastructure mode. */
2014  ctl &= ~B43legacy_MACCTL_AP;
2015  ctl &= ~B43legacy_MACCTL_KEEP_CTL;
2016  ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
2017  ctl &= ~B43legacy_MACCTL_KEEP_BAD;
2018  ctl &= ~B43legacy_MACCTL_PROMISC;
2019  ctl &= ~B43legacy_MACCTL_BEACPROMISC;
2020  ctl |= B43legacy_MACCTL_INFRA;
2021 
2022  if (b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
2023  ctl |= B43legacy_MACCTL_AP;
2024  else if (b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC))
2025  ctl &= ~B43legacy_MACCTL_INFRA;
2026 
2027  if (wl->filter_flags & FIF_CONTROL)
2028  ctl |= B43legacy_MACCTL_KEEP_CTL;
2029  if (wl->filter_flags & FIF_FCSFAIL)
2030  ctl |= B43legacy_MACCTL_KEEP_BAD;
2031  if (wl->filter_flags & FIF_PLCPFAIL)
2032  ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
2033  if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2034  ctl |= B43legacy_MACCTL_PROMISC;
2035  if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2036  ctl |= B43legacy_MACCTL_BEACPROMISC;
2037 
2038  /* Workaround: On old hardware the HW-MAC-address-filter
2039  * doesn't work properly, so always run promisc in filter
2040  * it in software. */
2041  if (dev->dev->id.revision <= 4)
2042  ctl |= B43legacy_MACCTL_PROMISC;
2043 
2044  b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
2045 
2046  cfp_pretbtt = 2;
2047  if ((ctl & B43legacy_MACCTL_INFRA) &&
2048  !(ctl & B43legacy_MACCTL_AP)) {
2049  if (dev->dev->bus->chip_id == 0x4306 &&
2050  dev->dev->bus->chip_rev == 3)
2051  cfp_pretbtt = 100;
2052  else
2053  cfp_pretbtt = 50;
2054  }
2055  b43legacy_write16(dev, 0x612, cfp_pretbtt);
2056 }
2057 
2058 static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
2059  u16 rate,
2060  int is_ofdm)
2061 {
2062  u16 offset;
2063 
2064  if (is_ofdm) {
2065  offset = 0x480;
2066  offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2067  } else {
2068  offset = 0x4C0;
2069  offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2070  }
2071  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
2072  b43legacy_shm_read16(dev,
2073  B43legacy_SHM_SHARED, offset));
2074 }
2075 
2076 static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
2077 {
2078  switch (dev->phy.type) {
2079  case B43legacy_PHYTYPE_G:
2080  b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
2081  b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
2082  b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
2083  b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
2084  b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
2085  b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
2086  b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
2087  /* fallthrough */
2088  case B43legacy_PHYTYPE_B:
2089  b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
2090  b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
2091  b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
2092  b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
2093  break;
2094  default:
2095  B43legacy_BUG_ON(1);
2096  }
2097 }
2098 
2099 /* Set the TX-Antenna for management frames sent by firmware. */
2100 static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
2101  int antenna)
2102 {
2103  u16 ant = 0;
2104  u16 tmp;
2105 
2106  switch (antenna) {
2107  case B43legacy_ANTENNA0:
2108  ant |= B43legacy_TX4_PHY_ANT0;
2109  break;
2110  case B43legacy_ANTENNA1:
2111  ant |= B43legacy_TX4_PHY_ANT1;
2112  break;
2113  case B43legacy_ANTENNA_AUTO:
2114  ant |= B43legacy_TX4_PHY_ANTLAST;
2115  break;
2116  default:
2117  B43legacy_BUG_ON(1);
2118  }
2119 
2120  /* FIXME We also need to set the other flags of the PHY control
2121  * field somewhere. */
2122 
2123  /* For Beacons */
2124  tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2125  B43legacy_SHM_SH_BEACPHYCTL);
2126  tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2127  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2128  B43legacy_SHM_SH_BEACPHYCTL, tmp);
2129  /* For ACK/CTS */
2130  tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2131  B43legacy_SHM_SH_ACKCTSPHYCTL);
2132  tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2133  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2134  B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
2135  /* For Probe Resposes */
2136  tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2137  B43legacy_SHM_SH_PRPHYCTL);
2138  tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2139  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2140  B43legacy_SHM_SH_PRPHYCTL, tmp);
2141 }
2142 
2143 /* This is the opposite of b43legacy_chip_init() */
2144 static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
2145 {
2146  b43legacy_radio_turn_off(dev, 1);
2147  b43legacy_gpio_cleanup(dev);
2148  /* firmware is released later */
2149 }
2150 
2151 /* Initialize the chip
2152  * http://bcm-specs.sipsolutions.net/ChipInit
2153  */
2154 static int b43legacy_chip_init(struct b43legacy_wldev *dev)
2155 {
2156  struct b43legacy_phy *phy = &dev->phy;
2157  int err;
2158  int tmp;
2159  u32 value32, macctl;
2160  u16 value16;
2161 
2162  /* Initialize the MAC control */
2163  macctl = B43legacy_MACCTL_IHR_ENABLED | B43legacy_MACCTL_SHM_ENABLED;
2164  if (dev->phy.gmode)
2165  macctl |= B43legacy_MACCTL_GMODE;
2166  macctl |= B43legacy_MACCTL_INFRA;
2167  b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
2168 
2169  err = b43legacy_upload_microcode(dev);
2170  if (err)
2171  goto out; /* firmware is released later */
2172 
2173  err = b43legacy_gpio_init(dev);
2174  if (err)
2175  goto out; /* firmware is released later */
2176 
2177  err = b43legacy_upload_initvals(dev);
2178  if (err)
2179  goto err_gpio_clean;
2180  b43legacy_radio_turn_on(dev);
2181 
2182  b43legacy_write16(dev, 0x03E6, 0x0000);
2183  err = b43legacy_phy_init(dev);
2184  if (err)
2185  goto err_radio_off;
2186 
2187  /* Select initial Interference Mitigation. */
2188  tmp = phy->interfmode;
2189  phy->interfmode = B43legacy_INTERFMODE_NONE;
2190  b43legacy_radio_set_interference_mitigation(dev, tmp);
2191 
2192  b43legacy_phy_set_antenna_diversity(dev);
2193  b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
2194 
2195  if (phy->type == B43legacy_PHYTYPE_B) {
2196  value16 = b43legacy_read16(dev, 0x005E);
2197  value16 |= 0x0004;
2198  b43legacy_write16(dev, 0x005E, value16);
2199  }
2200  b43legacy_write32(dev, 0x0100, 0x01000000);
2201  if (dev->dev->id.revision < 5)
2202  b43legacy_write32(dev, 0x010C, 0x01000000);
2203 
2204  value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2205  value32 &= ~B43legacy_MACCTL_INFRA;
2206  b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2207  value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2208  value32 |= B43legacy_MACCTL_INFRA;
2209  b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2210 
2211  if (b43legacy_using_pio(dev)) {
2212  b43legacy_write32(dev, 0x0210, 0x00000100);
2213  b43legacy_write32(dev, 0x0230, 0x00000100);
2214  b43legacy_write32(dev, 0x0250, 0x00000100);
2215  b43legacy_write32(dev, 0x0270, 0x00000100);
2216  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
2217  0x0000);
2218  }
2219 
2220  /* Probe Response Timeout value */
2221  /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2222  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
2223 
2224  /* Initially set the wireless operation mode. */
2225  b43legacy_adjust_opmode(dev);
2226 
2227  if (dev->dev->id.revision < 3) {
2228  b43legacy_write16(dev, 0x060E, 0x0000);
2229  b43legacy_write16(dev, 0x0610, 0x8000);
2230  b43legacy_write16(dev, 0x0604, 0x0000);
2231  b43legacy_write16(dev, 0x0606, 0x0200);
2232  } else {
2233  b43legacy_write32(dev, 0x0188, 0x80000000);
2234  b43legacy_write32(dev, 0x018C, 0x02000000);
2235  }
2236  b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
2237  b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2238  b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2239  b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2240  b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2241  b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2242  b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2243 
2244  value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2245  value32 |= B43legacy_TMSLOW_MACPHYCLKEN;
2246  ssb_write32(dev->dev, SSB_TMSLOW, value32);
2247 
2248  b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
2249  dev->dev->bus->chipco.fast_pwrup_delay);
2250 
2251  /* PHY TX errors counter. */
2252  atomic_set(&phy->txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2253 
2254  B43legacy_WARN_ON(err != 0);
2255  b43legacydbg(dev->wl, "Chip initialized\n");
2256 out:
2257  return err;
2258 
2259 err_radio_off:
2260  b43legacy_radio_turn_off(dev, 1);
2261 err_gpio_clean:
2262  b43legacy_gpio_cleanup(dev);
2263  goto out;
2264 }
2265 
2266 static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
2267 {
2268  struct b43legacy_phy *phy = &dev->phy;
2269 
2270  if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
2271  return;
2272 
2273  b43legacy_mac_suspend(dev);
2274  b43legacy_phy_lo_g_measure(dev);
2275  b43legacy_mac_enable(dev);
2276 }
2277 
2278 static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
2279 {
2280  b43legacy_phy_lo_mark_all_unused(dev);
2281  if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
2282  b43legacy_mac_suspend(dev);
2283  b43legacy_calc_nrssi_slope(dev);
2284  b43legacy_mac_enable(dev);
2285  }
2286 }
2287 
2288 static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
2289 {
2290  /* Update device statistics. */
2291  b43legacy_calculate_link_quality(dev);
2292 }
2293 
2294 static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
2295 {
2296  b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
2297 
2298  atomic_set(&dev->phy.txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2299  wmb();
2300 }
2301 
2302 static void do_periodic_work(struct b43legacy_wldev *dev)
2303 {
2304  unsigned int state;
2305 
2306  state = dev->periodic_state;
2307  if (state % 8 == 0)
2308  b43legacy_periodic_every120sec(dev);
2309  if (state % 4 == 0)
2310  b43legacy_periodic_every60sec(dev);
2311  if (state % 2 == 0)
2312  b43legacy_periodic_every30sec(dev);
2313  b43legacy_periodic_every15sec(dev);
2314 }
2315 
2316 /* Periodic work locking policy:
2317  * The whole periodic work handler is protected by
2318  * wl->mutex. If another lock is needed somewhere in the
2319  * pwork callchain, it's acquired in-place, where it's needed.
2320  */
2321 static void b43legacy_periodic_work_handler(struct work_struct *work)
2322 {
2323  struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
2324  periodic_work.work);
2325  struct b43legacy_wl *wl = dev->wl;
2326  unsigned long delay;
2327 
2328  mutex_lock(&wl->mutex);
2329 
2330  if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
2331  goto out;
2332  if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
2333  goto out_requeue;
2334 
2335  do_periodic_work(dev);
2336 
2337  dev->periodic_state++;
2338 out_requeue:
2339  if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
2340  delay = msecs_to_jiffies(50);
2341  else
2342  delay = round_jiffies_relative(HZ * 15);
2343  ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
2344 out:
2345  mutex_unlock(&wl->mutex);
2346 }
2347 
2348 static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
2349 {
2350  struct delayed_work *work = &dev->periodic_work;
2351 
2352  dev->periodic_state = 0;
2353  INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
2354  ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
2355 }
2356 
2357 /* Validate access to the chip (SHM) */
2358 static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
2359 {
2360  u32 value;
2361  u32 shm_backup;
2362 
2363  shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
2364  b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
2365  if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2366  0xAA5555AA)
2367  goto error;
2368  b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
2369  if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2370  0x55AAAA55)
2371  goto error;
2372  b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
2373 
2374  value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2375  if ((value | B43legacy_MACCTL_GMODE) !=
2376  (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
2377  goto error;
2378 
2379  value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
2380  if (value)
2381  goto error;
2382 
2383  return 0;
2384 error:
2385  b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
2386  return -ENODEV;
2387 }
2388 
2389 static void b43legacy_security_init(struct b43legacy_wldev *dev)
2390 {
2391  dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2392  B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2393  dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2394  0x0056);
2395  /* KTP is a word address, but we address SHM bytewise.
2396  * So multiply by two.
2397  */
2398  dev->ktp *= 2;
2399  if (dev->dev->id.revision >= 5)
2400  /* Number of RCMTA address slots */
2401  b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
2402  dev->max_nr_keys - 8);
2403 }
2404 
2405 #ifdef CONFIG_B43LEGACY_HWRNG
2406 static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
2407 {
2408  struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
2409  unsigned long flags;
2410 
2411  /* Don't take wl->mutex here, as it could deadlock with
2412  * hwrng internal locking. It's not needed to take
2413  * wl->mutex here, anyway. */
2414 
2415  spin_lock_irqsave(&wl->irq_lock, flags);
2416  *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
2417  spin_unlock_irqrestore(&wl->irq_lock, flags);
2418 
2419  return (sizeof(u16));
2420 }
2421 #endif
2422 
2423 static void b43legacy_rng_exit(struct b43legacy_wl *wl)
2424 {
2425 #ifdef CONFIG_B43LEGACY_HWRNG
2426  if (wl->rng_initialized)
2427  hwrng_unregister(&wl->rng);
2428 #endif
2429 }
2430 
2431 static int b43legacy_rng_init(struct b43legacy_wl *wl)
2432 {
2433  int err = 0;
2434 
2435 #ifdef CONFIG_B43LEGACY_HWRNG
2436  snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2437  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2438  wl->rng.name = wl->rng_name;
2439  wl->rng.data_read = b43legacy_rng_read;
2440  wl->rng.priv = (unsigned long)wl;
2441  wl->rng_initialized = 1;
2442  err = hwrng_register(&wl->rng);
2443  if (err) {
2444  wl->rng_initialized = 0;
2445  b43legacyerr(wl, "Failed to register the random "
2446  "number generator (%d)\n", err);
2447  }
2448 
2449 #endif
2450  return err;
2451 }
2452 
2453 static void b43legacy_tx_work(struct work_struct *work)
2454 {
2455  struct b43legacy_wl *wl = container_of(work, struct b43legacy_wl,
2456  tx_work);
2457  struct b43legacy_wldev *dev;
2458  struct sk_buff *skb;
2459  int queue_num;
2460  int err = 0;
2461 
2462  mutex_lock(&wl->mutex);
2463  dev = wl->current_dev;
2464  if (unlikely(!dev || b43legacy_status(dev) < B43legacy_STAT_STARTED)) {
2465  mutex_unlock(&wl->mutex);
2466  return;
2467  }
2468 
2469  for (queue_num = 0; queue_num < B43legacy_QOS_QUEUE_NUM; queue_num++) {
2470  while (skb_queue_len(&wl->tx_queue[queue_num])) {
2471  skb = skb_dequeue(&wl->tx_queue[queue_num]);
2472  if (b43legacy_using_pio(dev))
2473  err = b43legacy_pio_tx(dev, skb);
2474  else
2475  err = b43legacy_dma_tx(dev, skb);
2476  if (err == -ENOSPC) {
2477  wl->tx_queue_stopped[queue_num] = 1;
2478  ieee80211_stop_queue(wl->hw, queue_num);
2479  skb_queue_head(&wl->tx_queue[queue_num], skb);
2480  break;
2481  }
2482  if (unlikely(err))
2483  dev_kfree_skb(skb); /* Drop it */
2484  err = 0;
2485  }
2486 
2487  if (!err)
2488  wl->tx_queue_stopped[queue_num] = 0;
2489  }
2490 
2491  mutex_unlock(&wl->mutex);
2492 }
2493 
2494 static void b43legacy_op_tx(struct ieee80211_hw *hw,
2495  struct ieee80211_tx_control *control,
2496  struct sk_buff *skb)
2497 {
2498  struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2499 
2500  if (unlikely(skb->len < 2 + 2 + 6)) {
2501  /* Too short, this can't be a valid frame. */
2502  dev_kfree_skb_any(skb);
2503  return;
2504  }
2505  B43legacy_WARN_ON(skb_shinfo(skb)->nr_frags);
2506 
2507  skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
2508  if (!wl->tx_queue_stopped[skb->queue_mapping])
2509  ieee80211_queue_work(wl->hw, &wl->tx_work);
2510  else
2511  ieee80211_stop_queue(wl->hw, skb->queue_mapping);
2512 }
2513 
2514 static int b43legacy_op_conf_tx(struct ieee80211_hw *hw,
2515  struct ieee80211_vif *vif, u16 queue,
2516  const struct ieee80211_tx_queue_params *params)
2517 {
2518  return 0;
2519 }
2520 
2521 static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
2522  struct ieee80211_low_level_stats *stats)
2523 {
2524  struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2525  unsigned long flags;
2526 
2527  spin_lock_irqsave(&wl->irq_lock, flags);
2528  memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2529  spin_unlock_irqrestore(&wl->irq_lock, flags);
2530 
2531  return 0;
2532 }
2533 
2534 static const char *phymode_to_string(unsigned int phymode)
2535 {
2536  switch (phymode) {
2537  case B43legacy_PHYMODE_B:
2538  return "B";
2539  case B43legacy_PHYMODE_G:
2540  return "G";
2541  default:
2542  B43legacy_BUG_ON(1);
2543  }
2544  return "";
2545 }
2546 
2547 static int find_wldev_for_phymode(struct b43legacy_wl *wl,
2548  unsigned int phymode,
2549  struct b43legacy_wldev **dev,
2550  bool *gmode)
2551 {
2552  struct b43legacy_wldev *d;
2553 
2554  list_for_each_entry(d, &wl->devlist, list) {
2555  if (d->phy.possible_phymodes & phymode) {
2556  /* Ok, this device supports the PHY-mode.
2557  * Set the gmode bit. */
2558  *gmode = true;
2559  *dev = d;
2560 
2561  return 0;
2562  }
2563  }
2564 
2565  return -ESRCH;
2566 }
2567 
2568 static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
2569 {
2570  struct ssb_device *sdev = dev->dev;
2571  u32 tmslow;
2572 
2573  tmslow = ssb_read32(sdev, SSB_TMSLOW);
2574  tmslow &= ~B43legacy_TMSLOW_GMODE;
2575  tmslow |= B43legacy_TMSLOW_PHYRESET;
2576  tmslow |= SSB_TMSLOW_FGC;
2577  ssb_write32(sdev, SSB_TMSLOW, tmslow);
2578  msleep(1);
2579 
2580  tmslow = ssb_read32(sdev, SSB_TMSLOW);
2581  tmslow &= ~SSB_TMSLOW_FGC;
2582  tmslow |= B43legacy_TMSLOW_PHYRESET;
2583  ssb_write32(sdev, SSB_TMSLOW, tmslow);
2584  msleep(1);
2585 }
2586 
2587 /* Expects wl->mutex locked */
2588 static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
2589  unsigned int new_mode)
2590 {
2591  struct b43legacy_wldev *uninitialized_var(up_dev);
2592  struct b43legacy_wldev *down_dev;
2593  int err;
2594  bool gmode = false;
2595  int prev_status;
2596 
2597  err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2598  if (err) {
2599  b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
2600  phymode_to_string(new_mode));
2601  return err;
2602  }
2603  if ((up_dev == wl->current_dev) &&
2604  (!!wl->current_dev->phy.gmode == !!gmode))
2605  /* This device is already running. */
2606  return 0;
2607  b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2608  phymode_to_string(new_mode));
2609  down_dev = wl->current_dev;
2610 
2611  prev_status = b43legacy_status(down_dev);
2612  /* Shutdown the currently running core. */
2613  if (prev_status >= B43legacy_STAT_STARTED)
2614  b43legacy_wireless_core_stop(down_dev);
2615  if (prev_status >= B43legacy_STAT_INITIALIZED)
2616  b43legacy_wireless_core_exit(down_dev);
2617 
2618  if (down_dev != up_dev)
2619  /* We switch to a different core, so we put PHY into
2620  * RESET on the old core. */
2621  b43legacy_put_phy_into_reset(down_dev);
2622 
2623  /* Now start the new core. */
2624  up_dev->phy.gmode = gmode;
2625  if (prev_status >= B43legacy_STAT_INITIALIZED) {
2626  err = b43legacy_wireless_core_init(up_dev);
2627  if (err) {
2628  b43legacyerr(wl, "Fatal: Could not initialize device"
2629  " for newly selected %s-PHY mode\n",
2630  phymode_to_string(new_mode));
2631  goto init_failure;
2632  }
2633  }
2634  if (prev_status >= B43legacy_STAT_STARTED) {
2635  err = b43legacy_wireless_core_start(up_dev);
2636  if (err) {
2637  b43legacyerr(wl, "Fatal: Could not start device for "
2638  "newly selected %s-PHY mode\n",
2639  phymode_to_string(new_mode));
2640  b43legacy_wireless_core_exit(up_dev);
2641  goto init_failure;
2642  }
2643  }
2644  B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
2645 
2646  b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
2647 
2648  wl->current_dev = up_dev;
2649 
2650  return 0;
2651 init_failure:
2652  /* Whoops, failed to init the new core. No core is operating now. */
2653  wl->current_dev = NULL;
2654  return err;
2655 }
2656 
2657 /* Write the short and long frame retry limit values. */
2658 static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
2659  unsigned int short_retry,
2660  unsigned int long_retry)
2661 {
2662  /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
2663  * the chip-internal counter. */
2664  short_retry = min(short_retry, (unsigned int)0xF);
2665  long_retry = min(long_retry, (unsigned int)0xF);
2666 
2667  b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
2668  b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
2669 }
2670 
2671 static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
2672  u32 changed)
2673 {
2674  struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2675  struct b43legacy_wldev *dev;
2676  struct b43legacy_phy *phy;
2677  struct ieee80211_conf *conf = &hw->conf;
2678  unsigned long flags;
2679  unsigned int new_phymode = 0xFFFF;
2680  int antenna_tx;
2681  int err = 0;
2682 
2683  antenna_tx = B43legacy_ANTENNA_DEFAULT;
2684 
2685  mutex_lock(&wl->mutex);
2686  dev = wl->current_dev;
2687  phy = &dev->phy;
2688 
2689  if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2690  b43legacy_set_retry_limits(dev,
2691  conf->short_frame_max_tx_count,
2692  conf->long_frame_max_tx_count);
2693  changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
2694  if (!changed)
2695  goto out_unlock_mutex;
2696 
2697  /* Switch the PHY mode (if necessary). */
2698  switch (conf->channel->band) {
2699  case IEEE80211_BAND_2GHZ:
2700  if (phy->type == B43legacy_PHYTYPE_B)
2701  new_phymode = B43legacy_PHYMODE_B;
2702  else
2703  new_phymode = B43legacy_PHYMODE_G;
2704  break;
2705  default:
2706  B43legacy_WARN_ON(1);
2707  }
2708  err = b43legacy_switch_phymode(wl, new_phymode);
2709  if (err)
2710  goto out_unlock_mutex;
2711 
2712  /* Disable IRQs while reconfiguring the device.
2713  * This makes it possible to drop the spinlock throughout
2714  * the reconfiguration process. */
2715  spin_lock_irqsave(&wl->irq_lock, flags);
2716  if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2717  spin_unlock_irqrestore(&wl->irq_lock, flags);
2718  goto out_unlock_mutex;
2719  }
2720  b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2721  spin_unlock_irqrestore(&wl->irq_lock, flags);
2722  b43legacy_synchronize_irq(dev);
2723 
2724  /* Switch to the requested channel.
2725  * The firmware takes care of races with the TX handler. */
2726  if (conf->channel->hw_value != phy->channel)
2727  b43legacy_radio_selectchannel(dev, conf->channel->hw_value, 0);
2728 
2729  dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
2730 
2731  /* Adjust the desired TX power level. */
2732  if (conf->power_level != 0) {
2733  if (conf->power_level != phy->power_level) {
2734  phy->power_level = conf->power_level;
2735  b43legacy_phy_xmitpower(dev);
2736  }
2737  }
2738 
2739  /* Antennas for RX and management frame TX. */
2740  b43legacy_mgmtframe_txantenna(dev, antenna_tx);
2741 
2742  if (wl->radio_enabled != phy->radio_on) {
2743  if (wl->radio_enabled) {
2744  b43legacy_radio_turn_on(dev);
2745  b43legacyinfo(dev->wl, "Radio turned on by software\n");
2746  if (!dev->radio_hw_enable)
2747  b43legacyinfo(dev->wl, "The hardware RF-kill"
2748  " button still turns the radio"
2749  " physically off. Press the"
2750  " button to turn it on.\n");
2751  } else {
2752  b43legacy_radio_turn_off(dev, 0);
2753  b43legacyinfo(dev->wl, "Radio turned off by"
2754  " software\n");
2755  }
2756  }
2757 
2758  spin_lock_irqsave(&wl->irq_lock, flags);
2759  b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2760  mmiowb();
2761  spin_unlock_irqrestore(&wl->irq_lock, flags);
2762 out_unlock_mutex:
2763  mutex_unlock(&wl->mutex);
2764 
2765  return err;
2766 }
2767 
2768 static void b43legacy_update_basic_rates(struct b43legacy_wldev *dev, u32 brates)
2769 {
2770  struct ieee80211_supported_band *sband =
2771  dev->wl->hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2772  struct ieee80211_rate *rate;
2773  int i;
2774  u16 basic, direct, offset, basic_offset, rateptr;
2775 
2776  for (i = 0; i < sband->n_bitrates; i++) {
2777  rate = &sband->bitrates[i];
2778 
2779  if (b43legacy_is_cck_rate(rate->hw_value)) {
2780  direct = B43legacy_SHM_SH_CCKDIRECT;
2781  basic = B43legacy_SHM_SH_CCKBASIC;
2782  offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2783  offset &= 0xF;
2784  } else {
2785  direct = B43legacy_SHM_SH_OFDMDIRECT;
2786  basic = B43legacy_SHM_SH_OFDMBASIC;
2787  offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2788  offset &= 0xF;
2789  }
2790 
2791  rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
2792 
2793  if (b43legacy_is_cck_rate(rate->hw_value)) {
2794  basic_offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2795  basic_offset &= 0xF;
2796  } else {
2797  basic_offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2798  basic_offset &= 0xF;
2799  }
2800 
2801  /*
2802  * Get the pointer that we need to point to
2803  * from the direct map
2804  */
2805  rateptr = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2806  direct + 2 * basic_offset);
2807  /* and write it to the basic map */
2808  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2809  basic + 2 * offset, rateptr);
2810  }
2811 }
2812 
2813 static void b43legacy_op_bss_info_changed(struct ieee80211_hw *hw,
2814  struct ieee80211_vif *vif,
2815  struct ieee80211_bss_conf *conf,
2816  u32 changed)
2817 {
2818  struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2819  struct b43legacy_wldev *dev;
2820  unsigned long flags;
2821 
2822  mutex_lock(&wl->mutex);
2823  B43legacy_WARN_ON(wl->vif != vif);
2824 
2825  dev = wl->current_dev;
2826 
2827  /* Disable IRQs while reconfiguring the device.
2828  * This makes it possible to drop the spinlock throughout
2829  * the reconfiguration process. */
2830  spin_lock_irqsave(&wl->irq_lock, flags);
2831  if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2832  spin_unlock_irqrestore(&wl->irq_lock, flags);
2833  goto out_unlock_mutex;
2834  }
2835  b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2836 
2837  if (changed & BSS_CHANGED_BSSID) {
2838  b43legacy_synchronize_irq(dev);
2839 
2840  if (conf->bssid)
2841  memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2842  else
2843  memset(wl->bssid, 0, ETH_ALEN);
2844  }
2845 
2846  if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
2847  if (changed & BSS_CHANGED_BEACON &&
2848  (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2849  b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2850  b43legacy_update_templates(wl);
2851 
2852  if (changed & BSS_CHANGED_BSSID)
2853  b43legacy_write_mac_bssid_templates(dev);
2854  }
2855  spin_unlock_irqrestore(&wl->irq_lock, flags);
2856 
2857  b43legacy_mac_suspend(dev);
2858 
2859  if (changed & BSS_CHANGED_BEACON_INT &&
2860  (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2861  b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2862  b43legacy_set_beacon_int(dev, conf->beacon_int);
2863 
2864  if (changed & BSS_CHANGED_BASIC_RATES)
2865  b43legacy_update_basic_rates(dev, conf->basic_rates);
2866 
2867  if (changed & BSS_CHANGED_ERP_SLOT) {
2868  if (conf->use_short_slot)
2869  b43legacy_short_slot_timing_enable(dev);
2870  else
2871  b43legacy_short_slot_timing_disable(dev);
2872  }
2873 
2874  b43legacy_mac_enable(dev);
2875 
2876  spin_lock_irqsave(&wl->irq_lock, flags);
2877  b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2878  /* XXX: why? */
2879  mmiowb();
2880  spin_unlock_irqrestore(&wl->irq_lock, flags);
2881  out_unlock_mutex:
2882  mutex_unlock(&wl->mutex);
2883 }
2884 
2885 static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
2886  unsigned int changed,
2887  unsigned int *fflags,u64 multicast)
2888 {
2889  struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2890  struct b43legacy_wldev *dev = wl->current_dev;
2891  unsigned long flags;
2892 
2893  if (!dev) {
2894  *fflags = 0;
2895  return;
2896  }
2897 
2898  spin_lock_irqsave(&wl->irq_lock, flags);
2899  *fflags &= FIF_PROMISC_IN_BSS |
2900  FIF_ALLMULTI |
2901  FIF_FCSFAIL |
2902  FIF_PLCPFAIL |
2903  FIF_CONTROL |
2904  FIF_OTHER_BSS |
2905  FIF_BCN_PRBRESP_PROMISC;
2906 
2907  changed &= FIF_PROMISC_IN_BSS |
2908  FIF_ALLMULTI |
2909  FIF_FCSFAIL |
2910  FIF_PLCPFAIL |
2911  FIF_CONTROL |
2912  FIF_OTHER_BSS |
2913  FIF_BCN_PRBRESP_PROMISC;
2914 
2915  wl->filter_flags = *fflags;
2916 
2917  if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
2918  b43legacy_adjust_opmode(dev);
2919  spin_unlock_irqrestore(&wl->irq_lock, flags);
2920 }
2921 
2922 /* Locking: wl->mutex */
2923 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
2924 {
2925  struct b43legacy_wl *wl = dev->wl;
2926  unsigned long flags;
2927  int queue_num;
2928 
2929  if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
2930  return;
2931 
2932  /* Disable and sync interrupts. We must do this before than
2933  * setting the status to INITIALIZED, as the interrupt handler
2934  * won't care about IRQs then. */
2935  spin_lock_irqsave(&wl->irq_lock, flags);
2936  b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2937  b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
2938  spin_unlock_irqrestore(&wl->irq_lock, flags);
2939  b43legacy_synchronize_irq(dev);
2940 
2941  b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
2942 
2943  mutex_unlock(&wl->mutex);
2944  /* Must unlock as it would otherwise deadlock. No races here.
2945  * Cancel the possibly running self-rearming periodic work. */
2946  cancel_delayed_work_sync(&dev->periodic_work);
2947  cancel_work_sync(&wl->tx_work);
2948  mutex_lock(&wl->mutex);
2949 
2950  /* Drain all TX queues. */
2951  for (queue_num = 0; queue_num < B43legacy_QOS_QUEUE_NUM; queue_num++) {
2952  while (skb_queue_len(&wl->tx_queue[queue_num]))
2953  dev_kfree_skb(skb_dequeue(&wl->tx_queue[queue_num]));
2954  }
2955 
2956 b43legacy_mac_suspend(dev);
2957  free_irq(dev->dev->irq, dev);
2958  b43legacydbg(wl, "Wireless interface stopped\n");
2959 }
2960 
2961 /* Locking: wl->mutex */
2962 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
2963 {
2964  int err;
2965 
2966  B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
2967 
2968  drain_txstatus_queue(dev);
2969  err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
2970  IRQF_SHARED, KBUILD_MODNAME, dev);
2971  if (err) {
2972  b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
2973  dev->dev->irq);
2974  goto out;
2975  }
2976  /* We are ready to run. */
2977  ieee80211_wake_queues(dev->wl->hw);
2978  b43legacy_set_status(dev, B43legacy_STAT_STARTED);
2979 
2980  /* Start data flow (TX/RX) */
2981  b43legacy_mac_enable(dev);
2982  b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2983 
2984  /* Start maintenance work */
2985  b43legacy_periodic_tasks_setup(dev);
2986 
2987  b43legacydbg(dev->wl, "Wireless interface started\n");
2988 out:
2989  return err;
2990 }
2991 
2992 /* Get PHY and RADIO versioning numbers */
2993 static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
2994 {
2995  struct b43legacy_phy *phy = &dev->phy;
2996  u32 tmp;
2997  u8 analog_type;
2998  u8 phy_type;
2999  u8 phy_rev;
3000  u16 radio_manuf;
3001  u16 radio_ver;
3002  u16 radio_rev;
3003  int unsupported = 0;
3004 
3005  /* Get PHY versioning */
3006  tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
3007  analog_type = (tmp & B43legacy_PHYVER_ANALOG)
3008  >> B43legacy_PHYVER_ANALOG_SHIFT;
3009  phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
3010  phy_rev = (tmp & B43legacy_PHYVER_VERSION);
3011  switch (phy_type) {
3012  case B43legacy_PHYTYPE_B:
3013  if (phy_rev != 2 && phy_rev != 4
3014  && phy_rev != 6 && phy_rev != 7)
3015  unsupported = 1;
3016  break;
3017  case B43legacy_PHYTYPE_G:
3018  if (phy_rev > 8)
3019  unsupported = 1;
3020  break;
3021  default:
3022  unsupported = 1;
3023  }
3024  if (unsupported) {
3025  b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
3026  "(Analog %u, Type %u, Revision %u)\n",
3027  analog_type, phy_type, phy_rev);
3028  return -EOPNOTSUPP;
3029  }
3030  b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3031  analog_type, phy_type, phy_rev);
3032 
3033 
3034  /* Get RADIO versioning */
3035  if (dev->dev->bus->chip_id == 0x4317) {
3036  if (dev->dev->bus->chip_rev == 0)
3037  tmp = 0x3205017F;
3038  else if (dev->dev->bus->chip_rev == 1)
3039  tmp = 0x4205017F;
3040  else
3041  tmp = 0x5205017F;
3042  } else {
3043  b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
3044  B43legacy_RADIOCTL_ID);
3045  tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
3046  tmp <<= 16;
3047  b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
3048  B43legacy_RADIOCTL_ID);
3049  tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
3050  }
3051  radio_manuf = (tmp & 0x00000FFF);
3052  radio_ver = (tmp & 0x0FFFF000) >> 12;
3053  radio_rev = (tmp & 0xF0000000) >> 28;
3054  switch (phy_type) {
3055  case B43legacy_PHYTYPE_B:
3056  if ((radio_ver & 0xFFF0) != 0x2050)
3057  unsupported = 1;
3058  break;
3059  case B43legacy_PHYTYPE_G:
3060  if (radio_ver != 0x2050)
3061  unsupported = 1;
3062  break;
3063  default:
3064  B43legacy_BUG_ON(1);
3065  }
3066  if (unsupported) {
3067  b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
3068  "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3069  radio_manuf, radio_ver, radio_rev);
3070  return -EOPNOTSUPP;
3071  }
3072  b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
3073  " Revision %u\n", radio_manuf, radio_ver, radio_rev);
3074 
3075 
3076  phy->radio_manuf = radio_manuf;
3077  phy->radio_ver = radio_ver;
3078  phy->radio_rev = radio_rev;
3079 
3080  phy->analog = analog_type;
3081  phy->type = phy_type;
3082  phy->rev = phy_rev;
3083 
3084  return 0;
3085 }
3086 
3087 static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
3088  struct b43legacy_phy *phy)
3089 {
3090  struct b43legacy_lopair *lo;
3091  int i;
3092 
3093  memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3094  memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3095 
3096  /* Assume the radio is enabled. If it's not enabled, the state will
3097  * immediately get fixed on the first periodic work run. */
3098  dev->radio_hw_enable = true;
3099 
3100  phy->savedpctlreg = 0xFFFF;
3101  phy->aci_enable = false;
3102  phy->aci_wlan_automatic = false;
3103  phy->aci_hw_rssi = false;
3104 
3105  lo = phy->_lo_pairs;
3106  if (lo)
3107  memset(lo, 0, sizeof(struct b43legacy_lopair) *
3108  B43legacy_LO_COUNT);
3109  phy->max_lb_gain = 0;
3110  phy->trsw_rx_gain = 0;
3111 
3112  /* Set default attenuation values. */
3113  phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3114  phy->rfatt = b43legacy_default_radio_attenuation(dev);
3115  phy->txctl1 = b43legacy_default_txctl1(dev);
3116  phy->txpwr_offset = 0;
3117 
3118  /* NRSSI */
3119  phy->nrssislope = 0;
3120  for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3121  phy->nrssi[i] = -1000;
3122  for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3123  phy->nrssi_lt[i] = i;
3124 
3125  phy->lofcal = 0xFFFF;
3126  phy->initval = 0xFFFF;
3127 
3128  phy->interfmode = B43legacy_INTERFMODE_NONE;
3129  phy->channel = 0xFF;
3130 }
3131 
3132 static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
3133 {
3134  /* Flags */
3135  dev->dfq_valid = false;
3136 
3137  /* Stats */
3138  memset(&dev->stats, 0, sizeof(dev->stats));
3139 
3140  setup_struct_phy_for_init(dev, &dev->phy);
3141 
3142  /* IRQ related flags */
3143  dev->irq_reason = 0;
3144  memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3145  dev->irq_mask = B43legacy_IRQ_MASKTEMPLATE;
3146 
3147  dev->mac_suspended = 1;
3148 
3149  /* Noise calculation context */
3150  memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3151 }
3152 
3153 static void b43legacy_set_synth_pu_delay(struct b43legacy_wldev *dev,
3154  bool idle) {
3155  u16 pu_delay = 1050;
3156 
3157  if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
3158  pu_delay = 500;
3159  if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3160  pu_delay = max(pu_delay, (u16)2400);
3161 
3162  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3163  B43legacy_SHM_SH_SPUWKUP, pu_delay);
3164 }
3165 
3166 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3167 static void b43legacy_set_pretbtt(struct b43legacy_wldev *dev)
3168 {
3169  u16 pretbtt;
3170 
3171  /* The time value is in microseconds. */
3172  if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
3173  pretbtt = 2;
3174  else
3175  pretbtt = 250;
3176  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3177  B43legacy_SHM_SH_PRETBTT, pretbtt);
3178  b43legacy_write16(dev, B43legacy_MMIO_TSF_CFP_PRETBTT, pretbtt);
3179 }
3180 
3181 /* Shutdown a wireless core */
3182 /* Locking: wl->mutex */
3183 static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev)
3184 {
3185  struct b43legacy_phy *phy = &dev->phy;
3186  u32 macctl;
3187 
3188  B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED);
3189  if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED)
3190  return;
3191  b43legacy_set_status(dev, B43legacy_STAT_UNINIT);
3192 
3193  /* Stop the microcode PSM. */
3194  macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
3195  macctl &= ~B43legacy_MACCTL_PSM_RUN;
3196  macctl |= B43legacy_MACCTL_PSM_JMP0;
3197  b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
3198 
3199  b43legacy_leds_exit(dev);
3200  b43legacy_rng_exit(dev->wl);
3201  b43legacy_pio_free(dev);
3202  b43legacy_dma_free(dev);
3203  b43legacy_chip_exit(dev);
3204  b43legacy_radio_turn_off(dev, 1);
3205  b43legacy_switch_analog(dev, 0);
3206  if (phy->dyn_tssi_tbl)
3207  kfree(phy->tssi2dbm);
3208  kfree(phy->lo_control);
3209  phy->lo_control = NULL;
3210  if (dev->wl->current_beacon) {
3211  dev_kfree_skb_any(dev->wl->current_beacon);
3212  dev->wl->current_beacon = NULL;
3213  }
3214 
3215  ssb_device_disable(dev->dev, 0);
3216  ssb_bus_may_powerdown(dev->dev->bus);
3217 }
3218 
3219 static void prepare_phy_data_for_init(struct b43legacy_wldev *dev)
3220 {
3221  struct b43legacy_phy *phy = &dev->phy;
3222  int i;
3223 
3224  /* Set default attenuation values. */
3225  phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3226  phy->rfatt = b43legacy_default_radio_attenuation(dev);
3227  phy->txctl1 = b43legacy_default_txctl1(dev);
3228  phy->txctl2 = 0xFFFF;
3229  phy->txpwr_offset = 0;
3230 
3231  /* NRSSI */
3232  phy->nrssislope = 0;
3233  for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3234  phy->nrssi[i] = -1000;
3235  for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3236  phy->nrssi_lt[i] = i;
3237 
3238  phy->lofcal = 0xFFFF;
3239  phy->initval = 0xFFFF;
3240 
3241  phy->aci_enable = false;
3242  phy->aci_wlan_automatic = false;
3243  phy->aci_hw_rssi = false;
3244 
3245  phy->antenna_diversity = 0xFFFF;
3246  memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3247  memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3248 
3249  /* Flags */
3250  phy->calibrated = 0;
3251 
3252  if (phy->_lo_pairs)
3253  memset(phy->_lo_pairs, 0,
3254  sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT);
3255  memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
3256 }
3257 
3258 /* Initialize a wireless core */
3259 static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev)
3260 {
3261  struct b43legacy_wl *wl = dev->wl;
3262  struct ssb_bus *bus = dev->dev->bus;
3263  struct b43legacy_phy *phy = &dev->phy;
3264  struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3265  int err;
3266  u32 hf;
3267  u32 tmp;
3268 
3269  B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3270 
3271  err = ssb_bus_powerup(bus, 0);
3272  if (err)
3273  goto out;
3274  if (!ssb_device_is_enabled(dev->dev)) {
3275  tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0;
3276  b43legacy_wireless_core_reset(dev, tmp);
3277  }
3278 
3279  if ((phy->type == B43legacy_PHYTYPE_B) ||
3280  (phy->type == B43legacy_PHYTYPE_G)) {
3281  phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair)
3282  * B43legacy_LO_COUNT,
3283  GFP_KERNEL);
3284  if (!phy->_lo_pairs)
3285  return -ENOMEM;
3286  }
3287  setup_struct_wldev_for_init(dev);
3288 
3289  err = b43legacy_phy_init_tssi2dbm_table(dev);
3290  if (err)
3291  goto err_kfree_lo_control;
3292 
3293  /* Enable IRQ routing to this device. */
3294  ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3295 
3296  prepare_phy_data_for_init(dev);
3297  b43legacy_phy_calibrate(dev);
3298  err = b43legacy_chip_init(dev);
3299  if (err)
3300  goto err_kfree_tssitbl;
3301  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3302  B43legacy_SHM_SH_WLCOREREV,
3303  dev->dev->id.revision);
3304  hf = b43legacy_hf_read(dev);
3305  if (phy->type == B43legacy_PHYTYPE_G) {
3306  hf |= B43legacy_HF_SYMW;
3307  if (phy->rev == 1)
3308  hf |= B43legacy_HF_GDCW;
3309  if (sprom->boardflags_lo & B43legacy_BFL_PACTRL)
3310  hf |= B43legacy_HF_OFDMPABOOST;
3311  } else if (phy->type == B43legacy_PHYTYPE_B) {
3312  hf |= B43legacy_HF_SYMW;
3313  if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3314  hf &= ~B43legacy_HF_GDCW;
3315  }
3316  b43legacy_hf_write(dev, hf);
3317 
3318  b43legacy_set_retry_limits(dev,
3319  B43legacy_DEFAULT_SHORT_RETRY_LIMIT,
3320  B43legacy_DEFAULT_LONG_RETRY_LIMIT);
3321 
3322  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3323  0x0044, 3);
3324  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3325  0x0046, 2);
3326 
3327  /* Disable sending probe responses from firmware.
3328  * Setting the MaxTime to one usec will always trigger
3329  * a timeout, so we never send any probe resp.
3330  * A timeout of zero is infinite. */
3331  b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3332  B43legacy_SHM_SH_PRMAXTIME, 1);
3333 
3334  b43legacy_rate_memory_init(dev);
3335 
3336  /* Minimum Contention Window */
3337  if (phy->type == B43legacy_PHYTYPE_B)
3338  b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3339  0x0003, 31);
3340  else
3341  b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3342  0x0003, 15);
3343  /* Maximum Contention Window */
3344  b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3345  0x0004, 1023);
3346 
3347  do {
3348  if (b43legacy_using_pio(dev))
3349  err = b43legacy_pio_init(dev);
3350  else {
3351  err = b43legacy_dma_init(dev);
3352  if (!err)
3353  b43legacy_qos_init(dev);
3354  }
3355  } while (err == -EAGAIN);
3356  if (err)
3357  goto err_chip_exit;
3358 
3359  b43legacy_set_synth_pu_delay(dev, 1);
3360 
3361  ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3362  b43legacy_upload_card_macaddress(dev);
3363  b43legacy_security_init(dev);
3364  b43legacy_rng_init(wl);
3365 
3366  ieee80211_wake_queues(dev->wl->hw);
3367  b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
3368 
3369  b43legacy_leds_init(dev);
3370 out:
3371  return err;
3372 
3373 err_chip_exit:
3374  b43legacy_chip_exit(dev);
3375 err_kfree_tssitbl:
3376  if (phy->dyn_tssi_tbl)
3377  kfree(phy->tssi2dbm);
3378 err_kfree_lo_control:
3379  kfree(phy->lo_control);
3380  phy->lo_control = NULL;
3381  ssb_bus_may_powerdown(bus);
3382  B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3383  return err;
3384 }
3385 
3386 static int b43legacy_op_add_interface(struct ieee80211_hw *hw,
3387  struct ieee80211_vif *vif)
3388 {
3389  struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3390  struct b43legacy_wldev *dev;
3391  unsigned long flags;
3392  int err = -EOPNOTSUPP;
3393 
3394  /* TODO: allow WDS/AP devices to coexist */
3395 
3396  if (vif->type != NL80211_IFTYPE_AP &&
3397  vif->type != NL80211_IFTYPE_STATION &&
3398  vif->type != NL80211_IFTYPE_WDS &&
3399  vif->type != NL80211_IFTYPE_ADHOC)
3400  return -EOPNOTSUPP;
3401 
3402  mutex_lock(&wl->mutex);
3403  if (wl->operating)
3404  goto out_mutex_unlock;
3405 
3406  b43legacydbg(wl, "Adding Interface type %d\n", vif->type);
3407 
3408  dev = wl->current_dev;
3409  wl->operating = true;
3410  wl->vif = vif;
3411  wl->if_type = vif->type;
3412  memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
3413 
3414  spin_lock_irqsave(&wl->irq_lock, flags);
3415  b43legacy_adjust_opmode(dev);
3416  b43legacy_set_pretbtt(dev);
3417  b43legacy_set_synth_pu_delay(dev, 0);
3418  b43legacy_upload_card_macaddress(dev);
3419  spin_unlock_irqrestore(&wl->irq_lock, flags);
3420 
3421  err = 0;
3422  out_mutex_unlock:
3423  mutex_unlock(&wl->mutex);
3424 
3425  return err;
3426 }
3427 
3428 static void b43legacy_op_remove_interface(struct ieee80211_hw *hw,
3429  struct ieee80211_vif *vif)
3430 {
3431  struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3432  struct b43legacy_wldev *dev = wl->current_dev;
3433  unsigned long flags;
3434 
3435  b43legacydbg(wl, "Removing Interface type %d\n", vif->type);
3436 
3437  mutex_lock(&wl->mutex);
3438 
3439  B43legacy_WARN_ON(!wl->operating);
3440  B43legacy_WARN_ON(wl->vif != vif);
3441  wl->vif = NULL;
3442 
3443  wl->operating = false;
3444 
3445  spin_lock_irqsave(&wl->irq_lock, flags);
3446  b43legacy_adjust_opmode(dev);
3447  memset(wl->mac_addr, 0, ETH_ALEN);
3448  b43legacy_upload_card_macaddress(dev);
3449  spin_unlock_irqrestore(&wl->irq_lock, flags);
3450 
3451  mutex_unlock(&wl->mutex);
3452 }
3453 
3454 static int b43legacy_op_start(struct ieee80211_hw *hw)
3455 {
3456  struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3457  struct b43legacy_wldev *dev = wl->current_dev;
3458  int did_init = 0;
3459  int err = 0;
3460 
3461  /* Kill all old instance specific information to make sure
3462  * the card won't use it in the short timeframe between start
3463  * and mac80211 reconfiguring it. */
3464  memset(wl->bssid, 0, ETH_ALEN);
3465  memset(wl->mac_addr, 0, ETH_ALEN);
3466  wl->filter_flags = 0;
3467  wl->beacon0_uploaded = false;
3468  wl->beacon1_uploaded = false;
3469  wl->beacon_templates_virgin = true;
3470  wl->radio_enabled = true;
3471 
3472  mutex_lock(&wl->mutex);
3473 
3474  if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) {
3475  err = b43legacy_wireless_core_init(dev);
3476  if (err)
3477  goto out_mutex_unlock;
3478  did_init = 1;
3479  }
3480 
3481  if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
3482  err = b43legacy_wireless_core_start(dev);
3483  if (err) {
3484  if (did_init)
3485  b43legacy_wireless_core_exit(dev);
3486  goto out_mutex_unlock;
3487  }
3488  }
3489 
3490  wiphy_rfkill_start_polling(hw->wiphy);
3491 
3492 out_mutex_unlock:
3493  mutex_unlock(&wl->mutex);
3494 
3495  return err;
3496 }
3497 
3498 static void b43legacy_op_stop(struct ieee80211_hw *hw)
3499 {
3500  struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3501  struct b43legacy_wldev *dev = wl->current_dev;
3502 
3503  cancel_work_sync(&(wl->beacon_update_trigger));
3504 
3505  mutex_lock(&wl->mutex);
3506  if (b43legacy_status(dev) >= B43legacy_STAT_STARTED)
3507  b43legacy_wireless_core_stop(dev);
3508  b43legacy_wireless_core_exit(dev);
3509  wl->radio_enabled = false;
3510  mutex_unlock(&wl->mutex);
3511 }
3512 
3513 static int b43legacy_op_beacon_set_tim(struct ieee80211_hw *hw,
3514  struct ieee80211_sta *sta, bool set)
3515 {
3516  struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3517  unsigned long flags;
3518 
3519  spin_lock_irqsave(&wl->irq_lock, flags);
3520  b43legacy_update_templates(wl);
3521  spin_unlock_irqrestore(&wl->irq_lock, flags);
3522 
3523  return 0;
3524 }
3525 
3526 static int b43legacy_op_get_survey(struct ieee80211_hw *hw, int idx,
3527  struct survey_info *survey)
3528 {
3529  struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3530  struct b43legacy_wldev *dev = wl->current_dev;
3531  struct ieee80211_conf *conf = &hw->conf;
3532 
3533  if (idx != 0)
3534  return -ENOENT;
3535 
3536  survey->channel = conf->channel;
3537  survey->filled = SURVEY_INFO_NOISE_DBM;
3538  survey->noise = dev->stats.link_noise;
3539 
3540  return 0;
3541 }
3542 
3543 static const struct ieee80211_ops b43legacy_hw_ops = {
3544  .tx = b43legacy_op_tx,
3545  .conf_tx = b43legacy_op_conf_tx,
3546  .add_interface = b43legacy_op_add_interface,
3547  .remove_interface = b43legacy_op_remove_interface,
3548  .config = b43legacy_op_dev_config,
3549  .bss_info_changed = b43legacy_op_bss_info_changed,
3550  .configure_filter = b43legacy_op_configure_filter,
3551  .get_stats = b43legacy_op_get_stats,
3552  .start = b43legacy_op_start,
3553  .stop = b43legacy_op_stop,
3554  .set_tim = b43legacy_op_beacon_set_tim,
3555  .get_survey = b43legacy_op_get_survey,
3556  .rfkill_poll = b43legacy_rfkill_poll,
3557 };
3558 
3559 /* Hard-reset the chip. Do not call this directly.
3560  * Use b43legacy_controller_restart()
3561  */
3562 static void b43legacy_chip_reset(struct work_struct *work)
3563 {
3564  struct b43legacy_wldev *dev =
3565  container_of(work, struct b43legacy_wldev, restart_work);
3566  struct b43legacy_wl *wl = dev->wl;
3567  int err = 0;
3568  int prev_status;
3569 
3570  mutex_lock(&wl->mutex);
3571 
3572  prev_status = b43legacy_status(dev);
3573  /* Bring the device down... */
3574  if (prev_status >= B43legacy_STAT_STARTED)
3575  b43legacy_wireless_core_stop(dev);
3576  if (prev_status >= B43legacy_STAT_INITIALIZED)
3577  b43legacy_wireless_core_exit(dev);
3578 
3579  /* ...and up again. */
3580  if (prev_status >= B43legacy_STAT_INITIALIZED) {
3581  err = b43legacy_wireless_core_init(dev);
3582  if (err)
3583  goto out;
3584  }
3585  if (prev_status >= B43legacy_STAT_STARTED) {
3586  err = b43legacy_wireless_core_start(dev);
3587  if (err) {
3588  b43legacy_wireless_core_exit(dev);
3589  goto out;
3590  }
3591  }
3592 out:
3593  if (err)
3594  wl->current_dev = NULL; /* Failed to init the dev. */
3595  mutex_unlock(&wl->mutex);
3596  if (err)
3597  b43legacyerr(wl, "Controller restart FAILED\n");
3598  else
3599  b43legacyinfo(wl, "Controller restarted\n");
3600 }
3601 
3602 static int b43legacy_setup_modes(struct b43legacy_wldev *dev,
3603  int have_bphy,
3604  int have_gphy)
3605 {
3606  struct ieee80211_hw *hw = dev->wl->hw;
3607  struct b43legacy_phy *phy = &dev->phy;
3608 
3609  phy->possible_phymodes = 0;
3610  if (have_bphy) {
3611  hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3612  &b43legacy_band_2GHz_BPHY;
3613  phy->possible_phymodes |= B43legacy_PHYMODE_B;
3614  }
3615 
3616  if (have_gphy) {
3617  hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3618  &b43legacy_band_2GHz_GPHY;
3619  phy->possible_phymodes |= B43legacy_PHYMODE_G;
3620  }
3621 
3622  return 0;
3623 }
3624 
3625 static void b43legacy_wireless_core_detach(struct b43legacy_wldev *dev)
3626 {
3627  /* We release firmware that late to not be required to re-request
3628  * is all the time when we reinit the core. */
3629  b43legacy_release_firmware(dev);
3630 }
3631 
3632 static int b43legacy_wireless_core_attach(struct b43legacy_wldev *dev)
3633 {
3634  struct b43legacy_wl *wl = dev->wl;
3635  struct ssb_bus *bus = dev->dev->bus;
3636  struct pci_dev *pdev = (bus->bustype == SSB_BUSTYPE_PCI) ? bus->host_pci : NULL;
3637  int err;
3638  int have_bphy = 0;
3639  int have_gphy = 0;
3640  u32 tmp;
3641 
3642  /* Do NOT do any device initialization here.
3643  * Do it in wireless_core_init() instead.
3644  * This function is for gathering basic information about the HW, only.
3645  * Also some structs may be set up here. But most likely you want to
3646  * have that in core_init(), too.
3647  */
3648 
3649  err = ssb_bus_powerup(bus, 0);
3650  if (err) {
3651  b43legacyerr(wl, "Bus powerup failed\n");
3652  goto out;
3653  }
3654  /* Get the PHY type. */
3655  if (dev->dev->id.revision >= 5) {
3656  u32 tmshigh;
3657 
3658  tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3659  have_gphy = !!(tmshigh & B43legacy_TMSHIGH_GPHY);
3660  if (!have_gphy)
3661  have_bphy = 1;
3662  } else if (dev->dev->id.revision == 4)
3663  have_gphy = 1;
3664  else
3665  have_bphy = 1;
3666 
3667  dev->phy.gmode = (have_gphy || have_bphy);
3668  dev->phy.radio_on = true;
3669  tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3670  b43legacy_wireless_core_reset(dev, tmp);
3671 
3672  err = b43legacy_phy_versioning(dev);
3673  if (err)
3674  goto err_powerdown;
3675  /* Check if this device supports multiband. */
3676  if (!pdev ||
3677  (pdev->device != 0x4312 &&
3678  pdev->device != 0x4319 &&
3679  pdev->device != 0x4324)) {
3680  /* No multiband support. */
3681  have_bphy = 0;
3682  have_gphy = 0;
3683  switch (dev->phy.type) {
3684  case B43legacy_PHYTYPE_B:
3685  have_bphy = 1;
3686  break;
3687  case B43legacy_PHYTYPE_G:
3688  have_gphy = 1;
3689  break;
3690  default:
3691  B43legacy_BUG_ON(1);
3692  }
3693  }
3694  dev->phy.gmode = (have_gphy || have_bphy);
3695  tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3696  b43legacy_wireless_core_reset(dev, tmp);
3697 
3698  err = b43legacy_validate_chipaccess(dev);
3699  if (err)
3700  goto err_powerdown;
3701  err = b43legacy_setup_modes(dev, have_bphy, have_gphy);
3702  if (err)
3703  goto err_powerdown;
3704 
3705  /* Now set some default "current_dev" */
3706  if (!wl->current_dev)
3707  wl->current_dev = dev;
3708  INIT_WORK(&dev->restart_work, b43legacy_chip_reset);
3709 
3710  b43legacy_radio_turn_off(dev, 1);
3711  b43legacy_switch_analog(dev, 0);
3712  ssb_device_disable(dev->dev, 0);
3713  ssb_bus_may_powerdown(bus);
3714 
3715 out:
3716  return err;
3717 
3718 err_powerdown:
3719  ssb_bus_may_powerdown(bus);
3720  return err;
3721 }
3722 
3723 static void b43legacy_one_core_detach(struct ssb_device *dev)
3724 {
3725  struct b43legacy_wldev *wldev;
3726  struct b43legacy_wl *wl;
3727 
3728  /* Do not cancel ieee80211-workqueue based work here.
3729  * See comment in b43legacy_remove(). */
3730 
3731  wldev = ssb_get_drvdata(dev);
3732  wl = wldev->wl;
3733  b43legacy_debugfs_remove_device(wldev);
3734  b43legacy_wireless_core_detach(wldev);
3735  list_del(&wldev->list);
3736  wl->nr_devs--;
3737  ssb_set_drvdata(dev, NULL);
3738  kfree(wldev);
3739 }
3740 
3741 static int b43legacy_one_core_attach(struct ssb_device *dev,
3742  struct b43legacy_wl *wl)
3743 {
3744  struct b43legacy_wldev *wldev;
3745  int err = -ENOMEM;
3746 
3747  wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3748  if (!wldev)
3749  goto out;
3750 
3751  wldev->dev = dev;
3752  wldev->wl = wl;
3753  b43legacy_set_status(wldev, B43legacy_STAT_UNINIT);
3754  wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3755  tasklet_init(&wldev->isr_tasklet,
3756  (void (*)(unsigned long))b43legacy_interrupt_tasklet,
3757  (unsigned long)wldev);
3758  if (modparam_pio)
3759  wldev->__using_pio = true;
3760  INIT_LIST_HEAD(&wldev->list);
3761 
3762  err = b43legacy_wireless_core_attach(wldev);
3763  if (err)
3764  goto err_kfree_wldev;
3765 
3766  list_add(&wldev->list, &wl->devlist);
3767  wl->nr_devs++;
3768  ssb_set_drvdata(dev, wldev);
3769  b43legacy_debugfs_add_device(wldev);
3770 out:
3771  return err;
3772 
3773 err_kfree_wldev:
3774  kfree(wldev);
3775  return err;
3776 }
3777 
3778 static void b43legacy_sprom_fixup(struct ssb_bus *bus)
3779 {
3780  /* boardflags workarounds */
3781  if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3782  bus->boardinfo.type == 0x4E &&
3783  bus->sprom.board_rev > 0x40)
3784  bus->sprom.boardflags_lo |= B43legacy_BFL_PACTRL;
3785 }
3786 
3787 static void b43legacy_wireless_exit(struct ssb_device *dev,
3788  struct b43legacy_wl *wl)
3789 {
3790  struct ieee80211_hw *hw = wl->hw;
3791 
3792  ssb_set_devtypedata(dev, NULL);
3793  ieee80211_free_hw(hw);
3794 }
3795 
3796 static int b43legacy_wireless_init(struct ssb_device *dev)
3797 {
3798  struct ssb_sprom *sprom = &dev->bus->sprom;
3799  struct ieee80211_hw *hw;
3800  struct b43legacy_wl *wl;
3801  int err = -ENOMEM;
3802  int queue_num;
3803 
3804  b43legacy_sprom_fixup(dev->bus);
3805 
3806  hw = ieee80211_alloc_hw(sizeof(*wl), &b43legacy_hw_ops);
3807  if (!hw) {
3808  b43legacyerr(NULL, "Could not allocate ieee80211 device\n");
3809  goto out;
3810  }
3811 
3812  /* fill hw info */
3813  hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
3814  IEEE80211_HW_SIGNAL_DBM;
3815  hw->wiphy->interface_modes =
3816  BIT(NL80211_IFTYPE_AP) |
3817  BIT(NL80211_IFTYPE_STATION) |
3818  BIT(NL80211_IFTYPE_WDS) |
3819  BIT(NL80211_IFTYPE_ADHOC);
3820  hw->queues = 1; /* FIXME: hardware has more queues */
3821  hw->max_rates = 2;
3822  SET_IEEE80211_DEV(hw, dev->dev);
3823  if (is_valid_ether_addr(sprom->et1mac))
3824  SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
3825  else
3826  SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
3827 
3828  /* Get and initialize struct b43legacy_wl */
3829  wl = hw_to_b43legacy_wl(hw);
3830  memset(wl, 0, sizeof(*wl));
3831  wl->hw = hw;
3832  spin_lock_init(&wl->irq_lock);
3833  spin_lock_init(&wl->leds_lock);
3834  mutex_init(&wl->mutex);
3835  INIT_LIST_HEAD(&wl->devlist);
3836  INIT_WORK(&wl->beacon_update_trigger, b43legacy_beacon_update_trigger_work);
3837  INIT_WORK(&wl->tx_work, b43legacy_tx_work);
3838 
3839  /* Initialize queues and flags. */
3840  for (queue_num = 0; queue_num < B43legacy_QOS_QUEUE_NUM; queue_num++) {
3841  skb_queue_head_init(&wl->tx_queue[queue_num]);
3842  wl->tx_queue_stopped[queue_num] = 0;
3843  }
3844 
3845  ssb_set_devtypedata(dev, wl);
3846  b43legacyinfo(wl, "Broadcom %04X WLAN found (core revision %u)\n",
3847  dev->bus->chip_id, dev->id.revision);
3848  err = 0;
3849 out:
3850  return err;
3851 }
3852 
3853 static int b43legacy_probe(struct ssb_device *dev,
3854  const struct ssb_device_id *id)
3855 {
3856  struct b43legacy_wl *wl;
3857  int err;
3858  int first = 0;
3859 
3860  wl = ssb_get_devtypedata(dev);
3861  if (!wl) {
3862  /* Probing the first core - setup common struct b43legacy_wl */
3863  first = 1;
3864  err = b43legacy_wireless_init(dev);
3865  if (err)
3866  goto out;
3867  wl = ssb_get_devtypedata(dev);
3868  B43legacy_WARN_ON(!wl);
3869  }
3870  err = b43legacy_one_core_attach(dev, wl);
3871  if (err)
3872  goto err_wireless_exit;
3873 
3874  /* setup and start work to load firmware */
3875  INIT_WORK(&wl->firmware_load, b43legacy_request_firmware);
3876  schedule_work(&wl->firmware_load);
3877 
3878 out:
3879  return err;
3880 
3881 err_wireless_exit:
3882  if (first)
3883  b43legacy_wireless_exit(dev, wl);
3884  return err;
3885 }
3886 
3887 static void b43legacy_remove(struct ssb_device *dev)
3888 {
3889  struct b43legacy_wl *wl = ssb_get_devtypedata(dev);
3890  struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3891 
3892  /* We must cancel any work here before unregistering from ieee80211,
3893  * as the ieee80211 unreg will destroy the workqueue. */
3894  cancel_work_sync(&wldev->restart_work);
3895  cancel_work_sync(&wl->firmware_load);
3896 
3897  B43legacy_WARN_ON(!wl);
3898  if (!wldev->fw.ucode)
3899  return; /* NULL if fw never loaded */
3900  if (wl->current_dev == wldev)
3901  ieee80211_unregister_hw(wl->hw);
3902 
3903  b43legacy_one_core_detach(dev);
3904 
3905  if (list_empty(&wl->devlist))
3906  /* Last core on the chip unregistered.
3907  * We can destroy common struct b43legacy_wl.
3908  */
3909  b43legacy_wireless_exit(dev, wl);
3910 }
3911 
3912 /* Perform a hardware reset. This can be called from any context. */
3913 void b43legacy_controller_restart(struct b43legacy_wldev *dev,
3914  const char *reason)
3915 {
3916  /* Must avoid requeueing, if we are in shutdown. */
3917  if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED)
3918  return;
3919  b43legacyinfo(dev->wl, "Controller RESET (%s) ...\n", reason);
3920  ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
3921 }
3922 
3923 #ifdef CONFIG_PM
3924 
3925 static int b43legacy_suspend(struct ssb_device *dev, pm_message_t state)
3926 {
3927  struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3928  struct b43legacy_wl *wl = wldev->wl;
3929 
3930  b43legacydbg(wl, "Suspending...\n");
3931 
3932  mutex_lock(&wl->mutex);
3933  wldev->suspend_init_status = b43legacy_status(wldev);
3934  if (wldev->suspend_init_status >= B43legacy_STAT_STARTED)
3935  b43legacy_wireless_core_stop(wldev);
3936  if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED)
3937  b43legacy_wireless_core_exit(wldev);
3938  mutex_unlock(&wl->mutex);
3939 
3940  b43legacydbg(wl, "Device suspended.\n");
3941 
3942  return 0;
3943 }
3944 
3945 static int b43legacy_resume(struct ssb_device *dev)
3946 {
3947  struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3948  struct b43legacy_wl *wl = wldev->wl;
3949  int err = 0;
3950 
3951  b43legacydbg(wl, "Resuming...\n");
3952 
3953  mutex_lock(&wl->mutex);
3954  if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED) {
3955  err = b43legacy_wireless_core_init(wldev);
3956  if (err) {
3957  b43legacyerr(wl, "Resume failed at core init\n");
3958  goto out;
3959  }
3960  }
3961  if (wldev->suspend_init_status >= B43legacy_STAT_STARTED) {
3962  err = b43legacy_wireless_core_start(wldev);
3963  if (err) {
3964  b43legacy_wireless_core_exit(wldev);
3965  b43legacyerr(wl, "Resume failed at core start\n");
3966  goto out;
3967  }
3968  }
3969 
3970  b43legacydbg(wl, "Device resumed.\n");
3971 out:
3972  mutex_unlock(&wl->mutex);
3973  return err;
3974 }
3975 
3976 #else /* CONFIG_PM */
3977 # define b43legacy_suspend NULL
3978 # define b43legacy_resume NULL
3979 #endif /* CONFIG_PM */
3980 
3981 static struct ssb_driver b43legacy_ssb_driver = {
3982  .name = KBUILD_MODNAME,
3983  .id_table = b43legacy_ssb_tbl,
3984  .probe = b43legacy_probe,
3985  .remove = b43legacy_remove,
3986  .suspend = b43legacy_suspend,
3987  .resume = b43legacy_resume,
3988 };
3989 
3990 static void b43legacy_print_driverinfo(void)
3991 {
3992  const char *feat_pci = "", *feat_leds = "",
3993  *feat_pio = "", *feat_dma = "";
3994 
3995 #ifdef CONFIG_B43LEGACY_PCI_AUTOSELECT
3996  feat_pci = "P";
3997 #endif
3998 #ifdef CONFIG_B43LEGACY_LEDS
3999  feat_leds = "L";
4000 #endif
4001 #ifdef CONFIG_B43LEGACY_PIO
4002  feat_pio = "I";
4003 #endif
4004 #ifdef CONFIG_B43LEGACY_DMA
4005  feat_dma = "D";
4006 #endif
4007  printk(KERN_INFO "Broadcom 43xx-legacy driver loaded "
4008  "[ Features: %s%s%s%s ]\n",
4009  feat_pci, feat_leds, feat_pio, feat_dma);
4010 }
4011 
4012 static int __init b43legacy_init(void)
4013 {
4014  int err;
4015 
4016  b43legacy_debugfs_init();
4017 
4018  err = ssb_driver_register(&b43legacy_ssb_driver);
4019  if (err)
4020  goto err_dfs_exit;
4021 
4022  b43legacy_print_driverinfo();
4023 
4024  return err;
4025 
4026 err_dfs_exit:
4027  b43legacy_debugfs_exit();
4028  return err;
4029 }
4030 
4031 static void __exit b43legacy_exit(void)
4032 {
4033  ssb_driver_unregister(&b43legacy_ssb_driver);
4034  b43legacy_debugfs_exit();
4035 }
4036 
4037 module_init(b43legacy_init)
4038 module_exit(b43legacy_exit)
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