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e1000_hw.c
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1 /*******************************************************************************
2 
3  Intel PRO/1000 Linux driver
4  Copyright(c) 1999 - 2006 Intel Corporation.
5 
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9 
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13  more details.
14 
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19  The full GNU General Public License is included in this distribution in
20  the file called "COPYING".
21 
22  Contact Information:
23  Linux NICS <[email protected]>
24  e1000-devel Mailing List <[email protected]>
25  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27  */
28 
29 /* e1000_hw.c
30  * Shared functions for accessing and configuring the MAC
31  */
32 
33 #include "e1000.h"
34 
35 static s32 e1000_check_downshift(struct e1000_hw *hw);
36 static s32 e1000_check_polarity(struct e1000_hw *hw,
37  e1000_rev_polarity *polarity);
38 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
39 static void e1000_clear_vfta(struct e1000_hw *hw);
40 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
41  bool link_up);
42 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
43 static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
44 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
45 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
46  u16 *max_length);
47 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
48 static s32 e1000_id_led_init(struct e1000_hw *hw);
49 static void e1000_init_rx_addrs(struct e1000_hw *hw);
50 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
51  struct e1000_phy_info *phy_info);
52 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
53  struct e1000_phy_info *phy_info);
54 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
55 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
56 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
57 static s32 e1000_set_phy_type(struct e1000_hw *hw);
58 static void e1000_phy_init_script(struct e1000_hw *hw);
59 static s32 e1000_setup_copper_link(struct e1000_hw *hw);
60 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
61 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
62 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
63 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
64 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
65 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
66 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);
67 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
68 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
69 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
70  u16 words, u16 *data);
71 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
72  u16 words, u16 *data);
73 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
74 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
75 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
76 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
77 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
78  u16 phy_data);
79 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
80  u16 *phy_data);
81 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
82 static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
83 static void e1000_release_eeprom(struct e1000_hw *hw);
84 static void e1000_standby_eeprom(struct e1000_hw *hw);
85 static s32 e1000_set_vco_speed(struct e1000_hw *hw);
86 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
87 static s32 e1000_set_phy_mode(struct e1000_hw *hw);
88 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
89  u16 *data);
90 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
91  u16 *data);
92 
93 /* IGP cable length table */
94 static const
95 u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {
96  5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
97  5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
98  25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
99  40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
100  60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
101  90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,
102  100,
103  100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
104  110, 110,
105  110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,
106  120, 120
107 };
108 
109 static DEFINE_SPINLOCK(e1000_eeprom_lock);
110 
115 static s32 e1000_set_phy_type(struct e1000_hw *hw)
116 {
117  e_dbg("e1000_set_phy_type");
118 
119  if (hw->mac_type == e1000_undefined)
120  return -E1000_ERR_PHY_TYPE;
121 
122  switch (hw->phy_id) {
123  case M88E1000_E_PHY_ID:
124  case M88E1000_I_PHY_ID:
125  case M88E1011_I_PHY_ID:
126  case M88E1111_I_PHY_ID:
127  case M88E1118_E_PHY_ID:
128  hw->phy_type = e1000_phy_m88;
129  break;
130  case IGP01E1000_I_PHY_ID:
131  if (hw->mac_type == e1000_82541 ||
132  hw->mac_type == e1000_82541_rev_2 ||
133  hw->mac_type == e1000_82547 ||
134  hw->mac_type == e1000_82547_rev_2)
135  hw->phy_type = e1000_phy_igp;
136  break;
137  case RTL8211B_PHY_ID:
138  hw->phy_type = e1000_phy_8211;
139  break;
140  case RTL8201N_PHY_ID:
141  hw->phy_type = e1000_phy_8201;
142  break;
143  default:
144  /* Should never have loaded on this device */
145  hw->phy_type = e1000_phy_undefined;
146  return -E1000_ERR_PHY_TYPE;
147  }
148 
149  return E1000_SUCCESS;
150 }
151 
156 static void e1000_phy_init_script(struct e1000_hw *hw)
157 {
158  u32 ret_val;
159  u16 phy_saved_data;
160 
161  e_dbg("e1000_phy_init_script");
162 
163  if (hw->phy_init_script) {
164  msleep(20);
165 
166  /* Save off the current value of register 0x2F5B to be restored at
167  * the end of this routine. */
168  ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
169 
170  /* Disabled the PHY transmitter */
171  e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
172  msleep(20);
173 
174  e1000_write_phy_reg(hw, 0x0000, 0x0140);
175  msleep(5);
176 
177  switch (hw->mac_type) {
178  case e1000_82541:
179  case e1000_82547:
180  e1000_write_phy_reg(hw, 0x1F95, 0x0001);
181  e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
182  e1000_write_phy_reg(hw, 0x1F79, 0x0018);
183  e1000_write_phy_reg(hw, 0x1F30, 0x1600);
184  e1000_write_phy_reg(hw, 0x1F31, 0x0014);
185  e1000_write_phy_reg(hw, 0x1F32, 0x161C);
186  e1000_write_phy_reg(hw, 0x1F94, 0x0003);
187  e1000_write_phy_reg(hw, 0x1F96, 0x003F);
188  e1000_write_phy_reg(hw, 0x2010, 0x0008);
189  break;
190 
191  case e1000_82541_rev_2:
192  case e1000_82547_rev_2:
193  e1000_write_phy_reg(hw, 0x1F73, 0x0099);
194  break;
195  default:
196  break;
197  }
198 
199  e1000_write_phy_reg(hw, 0x0000, 0x3300);
200  msleep(20);
201 
202  /* Now enable the transmitter */
203  e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
204 
205  if (hw->mac_type == e1000_82547) {
206  u16 fused, fine, coarse;
207 
208  /* Move to analog registers page */
209  e1000_read_phy_reg(hw,
210  IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
211  &fused);
212 
213  if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
214  e1000_read_phy_reg(hw,
215  IGP01E1000_ANALOG_FUSE_STATUS,
216  &fused);
217 
218  fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
219  coarse =
220  fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
221 
222  if (coarse >
223  IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
224  coarse -=
225  IGP01E1000_ANALOG_FUSE_COARSE_10;
226  fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
227  } else if (coarse ==
228  IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
229  fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
230 
231  fused =
232  (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
233  (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
234  (coarse &
235  IGP01E1000_ANALOG_FUSE_COARSE_MASK);
236 
237  e1000_write_phy_reg(hw,
238  IGP01E1000_ANALOG_FUSE_CONTROL,
239  fused);
240  e1000_write_phy_reg(hw,
241  IGP01E1000_ANALOG_FUSE_BYPASS,
242  IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
243  }
244  }
245  }
246 }
247 
252 s32 e1000_set_mac_type(struct e1000_hw *hw)
253 {
254  e_dbg("e1000_set_mac_type");
255 
256  switch (hw->device_id) {
257  case E1000_DEV_ID_82542:
258  switch (hw->revision_id) {
259  case E1000_82542_2_0_REV_ID:
260  hw->mac_type = e1000_82542_rev2_0;
261  break;
262  case E1000_82542_2_1_REV_ID:
263  hw->mac_type = e1000_82542_rev2_1;
264  break;
265  default:
266  /* Invalid 82542 revision ID */
267  return -E1000_ERR_MAC_TYPE;
268  }
269  break;
270  case E1000_DEV_ID_82543GC_FIBER:
271  case E1000_DEV_ID_82543GC_COPPER:
272  hw->mac_type = e1000_82543;
273  break;
274  case E1000_DEV_ID_82544EI_COPPER:
275  case E1000_DEV_ID_82544EI_FIBER:
276  case E1000_DEV_ID_82544GC_COPPER:
277  case E1000_DEV_ID_82544GC_LOM:
278  hw->mac_type = e1000_82544;
279  break;
280  case E1000_DEV_ID_82540EM:
281  case E1000_DEV_ID_82540EM_LOM:
282  case E1000_DEV_ID_82540EP:
283  case E1000_DEV_ID_82540EP_LOM:
284  case E1000_DEV_ID_82540EP_LP:
285  hw->mac_type = e1000_82540;
286  break;
287  case E1000_DEV_ID_82545EM_COPPER:
288  case E1000_DEV_ID_82545EM_FIBER:
289  hw->mac_type = e1000_82545;
290  break;
291  case E1000_DEV_ID_82545GM_COPPER:
292  case E1000_DEV_ID_82545GM_FIBER:
293  case E1000_DEV_ID_82545GM_SERDES:
294  hw->mac_type = e1000_82545_rev_3;
295  break;
296  case E1000_DEV_ID_82546EB_COPPER:
297  case E1000_DEV_ID_82546EB_FIBER:
298  case E1000_DEV_ID_82546EB_QUAD_COPPER:
299  hw->mac_type = e1000_82546;
300  break;
301  case E1000_DEV_ID_82546GB_COPPER:
302  case E1000_DEV_ID_82546GB_FIBER:
303  case E1000_DEV_ID_82546GB_SERDES:
304  case E1000_DEV_ID_82546GB_PCIE:
305  case E1000_DEV_ID_82546GB_QUAD_COPPER:
306  case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
307  hw->mac_type = e1000_82546_rev_3;
308  break;
309  case E1000_DEV_ID_82541EI:
310  case E1000_DEV_ID_82541EI_MOBILE:
311  case E1000_DEV_ID_82541ER_LOM:
312  hw->mac_type = e1000_82541;
313  break;
314  case E1000_DEV_ID_82541ER:
315  case E1000_DEV_ID_82541GI:
316  case E1000_DEV_ID_82541GI_LF:
317  case E1000_DEV_ID_82541GI_MOBILE:
318  hw->mac_type = e1000_82541_rev_2;
319  break;
320  case E1000_DEV_ID_82547EI:
321  case E1000_DEV_ID_82547EI_MOBILE:
322  hw->mac_type = e1000_82547;
323  break;
324  case E1000_DEV_ID_82547GI:
325  hw->mac_type = e1000_82547_rev_2;
326  break;
327  case E1000_DEV_ID_INTEL_CE4100_GBE:
328  hw->mac_type = e1000_ce4100;
329  break;
330  default:
331  /* Should never have loaded on this device */
332  return -E1000_ERR_MAC_TYPE;
333  }
334 
335  switch (hw->mac_type) {
336  case e1000_82541:
337  case e1000_82547:
338  case e1000_82541_rev_2:
339  case e1000_82547_rev_2:
340  hw->asf_firmware_present = true;
341  break;
342  default:
343  break;
344  }
345 
346  /* The 82543 chip does not count tx_carrier_errors properly in
347  * FD mode
348  */
349  if (hw->mac_type == e1000_82543)
350  hw->bad_tx_carr_stats_fd = true;
351 
352  if (hw->mac_type > e1000_82544)
353  hw->has_smbus = true;
354 
355  return E1000_SUCCESS;
356 }
357 
362 void e1000_set_media_type(struct e1000_hw *hw)
363 {
364  u32 status;
365 
366  e_dbg("e1000_set_media_type");
367 
368  if (hw->mac_type != e1000_82543) {
369  /* tbi_compatibility is only valid on 82543 */
370  hw->tbi_compatibility_en = false;
371  }
372 
373  switch (hw->device_id) {
374  case E1000_DEV_ID_82545GM_SERDES:
375  case E1000_DEV_ID_82546GB_SERDES:
376  hw->media_type = e1000_media_type_internal_serdes;
377  break;
378  default:
379  switch (hw->mac_type) {
380  case e1000_82542_rev2_0:
381  case e1000_82542_rev2_1:
382  hw->media_type = e1000_media_type_fiber;
383  break;
384  case e1000_ce4100:
385  hw->media_type = e1000_media_type_copper;
386  break;
387  default:
388  status = er32(STATUS);
389  if (status & E1000_STATUS_TBIMODE) {
390  hw->media_type = e1000_media_type_fiber;
391  /* tbi_compatibility not valid on fiber */
392  hw->tbi_compatibility_en = false;
393  } else {
394  hw->media_type = e1000_media_type_copper;
395  }
396  break;
397  }
398  }
399 }
400 
407 s32 e1000_reset_hw(struct e1000_hw *hw)
408 {
409  u32 ctrl;
410  u32 ctrl_ext;
411  u32 icr;
412  u32 manc;
413  u32 led_ctrl;
414  s32 ret_val;
415 
416  e_dbg("e1000_reset_hw");
417 
418  /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
419  if (hw->mac_type == e1000_82542_rev2_0) {
420  e_dbg("Disabling MWI on 82542 rev 2.0\n");
421  e1000_pci_clear_mwi(hw);
422  }
423 
424  /* Clear interrupt mask to stop board from generating interrupts */
425  e_dbg("Masking off all interrupts\n");
426  ew32(IMC, 0xffffffff);
427 
428  /* Disable the Transmit and Receive units. Then delay to allow
429  * any pending transactions to complete before we hit the MAC with
430  * the global reset.
431  */
432  ew32(RCTL, 0);
433  ew32(TCTL, E1000_TCTL_PSP);
434  E1000_WRITE_FLUSH();
435 
436  /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
437  hw->tbi_compatibility_on = false;
438 
439  /* Delay to allow any outstanding PCI transactions to complete before
440  * resetting the device
441  */
442  msleep(10);
443 
444  ctrl = er32(CTRL);
445 
446  /* Must reset the PHY before resetting the MAC */
447  if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
448  ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
449  E1000_WRITE_FLUSH();
450  msleep(5);
451  }
452 
453  /* Issue a global reset to the MAC. This will reset the chip's
454  * transmit, receive, DMA, and link units. It will not effect
455  * the current PCI configuration. The global reset bit is self-
456  * clearing, and should clear within a microsecond.
457  */
458  e_dbg("Issuing a global reset to MAC\n");
459 
460  switch (hw->mac_type) {
461  case e1000_82544:
462  case e1000_82540:
463  case e1000_82545:
464  case e1000_82546:
465  case e1000_82541:
466  case e1000_82541_rev_2:
467  /* These controllers can't ack the 64-bit write when issuing the
468  * reset, so use IO-mapping as a workaround to issue the reset */
469  E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
470  break;
471  case e1000_82545_rev_3:
472  case e1000_82546_rev_3:
473  /* Reset is performed on a shadow of the control register */
474  ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
475  break;
476  case e1000_ce4100:
477  default:
478  ew32(CTRL, (ctrl | E1000_CTRL_RST));
479  break;
480  }
481 
482  /* After MAC reset, force reload of EEPROM to restore power-on settings to
483  * device. Later controllers reload the EEPROM automatically, so just wait
484  * for reload to complete.
485  */
486  switch (hw->mac_type) {
487  case e1000_82542_rev2_0:
488  case e1000_82542_rev2_1:
489  case e1000_82543:
490  case e1000_82544:
491  /* Wait for reset to complete */
492  udelay(10);
493  ctrl_ext = er32(CTRL_EXT);
494  ctrl_ext |= E1000_CTRL_EXT_EE_RST;
495  ew32(CTRL_EXT, ctrl_ext);
496  E1000_WRITE_FLUSH();
497  /* Wait for EEPROM reload */
498  msleep(2);
499  break;
500  case e1000_82541:
501  case e1000_82541_rev_2:
502  case e1000_82547:
503  case e1000_82547_rev_2:
504  /* Wait for EEPROM reload */
505  msleep(20);
506  break;
507  default:
508  /* Auto read done will delay 5ms or poll based on mac type */
509  ret_val = e1000_get_auto_rd_done(hw);
510  if (ret_val)
511  return ret_val;
512  break;
513  }
514 
515  /* Disable HW ARPs on ASF enabled adapters */
516  if (hw->mac_type >= e1000_82540) {
517  manc = er32(MANC);
518  manc &= ~(E1000_MANC_ARP_EN);
519  ew32(MANC, manc);
520  }
521 
522  if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
523  e1000_phy_init_script(hw);
524 
525  /* Configure activity LED after PHY reset */
526  led_ctrl = er32(LEDCTL);
527  led_ctrl &= IGP_ACTIVITY_LED_MASK;
528  led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
529  ew32(LEDCTL, led_ctrl);
530  }
531 
532  /* Clear interrupt mask to stop board from generating interrupts */
533  e_dbg("Masking off all interrupts\n");
534  ew32(IMC, 0xffffffff);
535 
536  /* Clear any pending interrupt events. */
537  icr = er32(ICR);
538 
539  /* If MWI was previously enabled, reenable it. */
540  if (hw->mac_type == e1000_82542_rev2_0) {
541  if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
542  e1000_pci_set_mwi(hw);
543  }
544 
545  return E1000_SUCCESS;
546 }
547 
558 s32 e1000_init_hw(struct e1000_hw *hw)
559 {
560  u32 ctrl;
561  u32 i;
562  s32 ret_val;
563  u32 mta_size;
564  u32 ctrl_ext;
565 
566  e_dbg("e1000_init_hw");
567 
568  /* Initialize Identification LED */
569  ret_val = e1000_id_led_init(hw);
570  if (ret_val) {
571  e_dbg("Error Initializing Identification LED\n");
572  return ret_val;
573  }
574 
575  /* Set the media type and TBI compatibility */
576  e1000_set_media_type(hw);
577 
578  /* Disabling VLAN filtering. */
579  e_dbg("Initializing the IEEE VLAN\n");
580  if (hw->mac_type < e1000_82545_rev_3)
581  ew32(VET, 0);
582  e1000_clear_vfta(hw);
583 
584  /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
585  if (hw->mac_type == e1000_82542_rev2_0) {
586  e_dbg("Disabling MWI on 82542 rev 2.0\n");
587  e1000_pci_clear_mwi(hw);
588  ew32(RCTL, E1000_RCTL_RST);
589  E1000_WRITE_FLUSH();
590  msleep(5);
591  }
592 
593  /* Setup the receive address. This involves initializing all of the Receive
594  * Address Registers (RARs 0 - 15).
595  */
596  e1000_init_rx_addrs(hw);
597 
598  /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
599  if (hw->mac_type == e1000_82542_rev2_0) {
600  ew32(RCTL, 0);
601  E1000_WRITE_FLUSH();
602  msleep(1);
603  if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
604  e1000_pci_set_mwi(hw);
605  }
606 
607  /* Zero out the Multicast HASH table */
608  e_dbg("Zeroing the MTA\n");
609  mta_size = E1000_MC_TBL_SIZE;
610  for (i = 0; i < mta_size; i++) {
611  E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
612  /* use write flush to prevent Memory Write Block (MWB) from
613  * occurring when accessing our register space */
614  E1000_WRITE_FLUSH();
615  }
616 
617  /* Set the PCI priority bit correctly in the CTRL register. This
618  * determines if the adapter gives priority to receives, or if it
619  * gives equal priority to transmits and receives. Valid only on
620  * 82542 and 82543 silicon.
621  */
622  if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
623  ctrl = er32(CTRL);
624  ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
625  }
626 
627  switch (hw->mac_type) {
628  case e1000_82545_rev_3:
629  case e1000_82546_rev_3:
630  break;
631  default:
632  /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
633  if (hw->bus_type == e1000_bus_type_pcix
634  && e1000_pcix_get_mmrbc(hw) > 2048)
635  e1000_pcix_set_mmrbc(hw, 2048);
636  break;
637  }
638 
639  /* Call a subroutine to configure the link and setup flow control. */
640  ret_val = e1000_setup_link(hw);
641 
642  /* Set the transmit descriptor write-back policy */
643  if (hw->mac_type > e1000_82544) {
644  ctrl = er32(TXDCTL);
645  ctrl =
646  (ctrl & ~E1000_TXDCTL_WTHRESH) |
647  E1000_TXDCTL_FULL_TX_DESC_WB;
648  ew32(TXDCTL, ctrl);
649  }
650 
651  /* Clear all of the statistics registers (clear on read). It is
652  * important that we do this after we have tried to establish link
653  * because the symbol error count will increment wildly if there
654  * is no link.
655  */
656  e1000_clear_hw_cntrs(hw);
657 
658  if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
659  hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
660  ctrl_ext = er32(CTRL_EXT);
661  /* Relaxed ordering must be disabled to avoid a parity
662  * error crash in a PCI slot. */
663  ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
664  ew32(CTRL_EXT, ctrl_ext);
665  }
666 
667  return ret_val;
668 }
669 
674 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
675 {
676  u16 eeprom_data;
677  s32 ret_val;
678 
679  e_dbg("e1000_adjust_serdes_amplitude");
680 
681  if (hw->media_type != e1000_media_type_internal_serdes)
682  return E1000_SUCCESS;
683 
684  switch (hw->mac_type) {
685  case e1000_82545_rev_3:
686  case e1000_82546_rev_3:
687  break;
688  default:
689  return E1000_SUCCESS;
690  }
691 
692  ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
693  &eeprom_data);
694  if (ret_val) {
695  return ret_val;
696  }
697 
698  if (eeprom_data != EEPROM_RESERVED_WORD) {
699  /* Adjust SERDES output amplitude only. */
700  eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
701  ret_val =
702  e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
703  if (ret_val)
704  return ret_val;
705  }
706 
707  return E1000_SUCCESS;
708 }
709 
720 s32 e1000_setup_link(struct e1000_hw *hw)
721 {
722  u32 ctrl_ext;
723  s32 ret_val;
724  u16 eeprom_data;
725 
726  e_dbg("e1000_setup_link");
727 
728  /* Read and store word 0x0F of the EEPROM. This word contains bits
729  * that determine the hardware's default PAUSE (flow control) mode,
730  * a bit that determines whether the HW defaults to enabling or
731  * disabling auto-negotiation, and the direction of the
732  * SW defined pins. If there is no SW over-ride of the flow
733  * control setting, then the variable hw->fc will
734  * be initialized based on a value in the EEPROM.
735  */
736  if (hw->fc == E1000_FC_DEFAULT) {
737  ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
738  1, &eeprom_data);
739  if (ret_val) {
740  e_dbg("EEPROM Read Error\n");
741  return -E1000_ERR_EEPROM;
742  }
743  if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
744  hw->fc = E1000_FC_NONE;
745  else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
746  EEPROM_WORD0F_ASM_DIR)
747  hw->fc = E1000_FC_TX_PAUSE;
748  else
749  hw->fc = E1000_FC_FULL;
750  }
751 
752  /* We want to save off the original Flow Control configuration just
753  * in case we get disconnected and then reconnected into a different
754  * hub or switch with different Flow Control capabilities.
755  */
756  if (hw->mac_type == e1000_82542_rev2_0)
757  hw->fc &= (~E1000_FC_TX_PAUSE);
758 
759  if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
760  hw->fc &= (~E1000_FC_RX_PAUSE);
761 
762  hw->original_fc = hw->fc;
763 
764  e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc);
765 
766  /* Take the 4 bits from EEPROM word 0x0F that determine the initial
767  * polarity value for the SW controlled pins, and setup the
768  * Extended Device Control reg with that info.
769  * This is needed because one of the SW controlled pins is used for
770  * signal detection. So this should be done before e1000_setup_pcs_link()
771  * or e1000_phy_setup() is called.
772  */
773  if (hw->mac_type == e1000_82543) {
774  ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
775  1, &eeprom_data);
776  if (ret_val) {
777  e_dbg("EEPROM Read Error\n");
778  return -E1000_ERR_EEPROM;
779  }
780  ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
781  SWDPIO__EXT_SHIFT);
782  ew32(CTRL_EXT, ctrl_ext);
783  }
784 
785  /* Call the necessary subroutine to configure the link. */
786  ret_val = (hw->media_type == e1000_media_type_copper) ?
787  e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);
788 
789  /* Initialize the flow control address, type, and PAUSE timer
790  * registers to their default values. This is done even if flow
791  * control is disabled, because it does not hurt anything to
792  * initialize these registers.
793  */
794  e_dbg("Initializing the Flow Control address, type and timer regs\n");
795 
796  ew32(FCT, FLOW_CONTROL_TYPE);
797  ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
798  ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
799 
800  ew32(FCTTV, hw->fc_pause_time);
801 
802  /* Set the flow control receive threshold registers. Normally,
803  * these registers will be set to a default threshold that may be
804  * adjusted later by the driver's runtime code. However, if the
805  * ability to transmit pause frames in not enabled, then these
806  * registers will be set to 0.
807  */
808  if (!(hw->fc & E1000_FC_TX_PAUSE)) {
809  ew32(FCRTL, 0);
810  ew32(FCRTH, 0);
811  } else {
812  /* We need to set up the Receive Threshold high and low water marks
813  * as well as (optionally) enabling the transmission of XON frames.
814  */
815  if (hw->fc_send_xon) {
816  ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
817  ew32(FCRTH, hw->fc_high_water);
818  } else {
819  ew32(FCRTL, hw->fc_low_water);
820  ew32(FCRTH, hw->fc_high_water);
821  }
822  }
823  return ret_val;
824 }
825 
834 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
835 {
836  u32 ctrl;
837  u32 status;
838  u32 txcw = 0;
839  u32 i;
840  u32 signal = 0;
841  s32 ret_val;
842 
843  e_dbg("e1000_setup_fiber_serdes_link");
844 
845  /* On adapters with a MAC newer than 82544, SWDP 1 will be
846  * set when the optics detect a signal. On older adapters, it will be
847  * cleared when there is a signal. This applies to fiber media only.
848  * If we're on serdes media, adjust the output amplitude to value
849  * set in the EEPROM.
850  */
851  ctrl = er32(CTRL);
852  if (hw->media_type == e1000_media_type_fiber)
853  signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
854 
855  ret_val = e1000_adjust_serdes_amplitude(hw);
856  if (ret_val)
857  return ret_val;
858 
859  /* Take the link out of reset */
860  ctrl &= ~(E1000_CTRL_LRST);
861 
862  /* Adjust VCO speed to improve BER performance */
863  ret_val = e1000_set_vco_speed(hw);
864  if (ret_val)
865  return ret_val;
866 
867  e1000_config_collision_dist(hw);
868 
869  /* Check for a software override of the flow control settings, and setup
870  * the device accordingly. If auto-negotiation is enabled, then software
871  * will have to set the "PAUSE" bits to the correct value in the Tranmsit
872  * Config Word Register (TXCW) and re-start auto-negotiation. However, if
873  * auto-negotiation is disabled, then software will have to manually
874  * configure the two flow control enable bits in the CTRL register.
875  *
876  * The possible values of the "fc" parameter are:
877  * 0: Flow control is completely disabled
878  * 1: Rx flow control is enabled (we can receive pause frames, but
879  * not send pause frames).
880  * 2: Tx flow control is enabled (we can send pause frames but we do
881  * not support receiving pause frames).
882  * 3: Both Rx and TX flow control (symmetric) are enabled.
883  */
884  switch (hw->fc) {
885  case E1000_FC_NONE:
886  /* Flow control is completely disabled by a software over-ride. */
887  txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
888  break;
889  case E1000_FC_RX_PAUSE:
890  /* RX Flow control is enabled and TX Flow control is disabled by a
891  * software over-ride. Since there really isn't a way to advertise
892  * that we are capable of RX Pause ONLY, we will advertise that we
893  * support both symmetric and asymmetric RX PAUSE. Later, we will
894  * disable the adapter's ability to send PAUSE frames.
895  */
896  txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
897  break;
898  case E1000_FC_TX_PAUSE:
899  /* TX Flow control is enabled, and RX Flow control is disabled, by a
900  * software over-ride.
901  */
902  txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
903  break;
904  case E1000_FC_FULL:
905  /* Flow control (both RX and TX) is enabled by a software over-ride. */
906  txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
907  break;
908  default:
909  e_dbg("Flow control param set incorrectly\n");
910  return -E1000_ERR_CONFIG;
911  break;
912  }
913 
914  /* Since auto-negotiation is enabled, take the link out of reset (the link
915  * will be in reset, because we previously reset the chip). This will
916  * restart auto-negotiation. If auto-negotiation is successful then the
917  * link-up status bit will be set and the flow control enable bits (RFCE
918  * and TFCE) will be set according to their negotiated value.
919  */
920  e_dbg("Auto-negotiation enabled\n");
921 
922  ew32(TXCW, txcw);
923  ew32(CTRL, ctrl);
924  E1000_WRITE_FLUSH();
925 
926  hw->txcw = txcw;
927  msleep(1);
928 
929  /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
930  * indication in the Device Status Register. Time-out if a link isn't
931  * seen in 500 milliseconds seconds (Auto-negotiation should complete in
932  * less than 500 milliseconds even if the other end is doing it in SW).
933  * For internal serdes, we just assume a signal is present, then poll.
934  */
935  if (hw->media_type == e1000_media_type_internal_serdes ||
936  (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
937  e_dbg("Looking for Link\n");
938  for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
939  msleep(10);
940  status = er32(STATUS);
941  if (status & E1000_STATUS_LU)
942  break;
943  }
944  if (i == (LINK_UP_TIMEOUT / 10)) {
945  e_dbg("Never got a valid link from auto-neg!!!\n");
946  hw->autoneg_failed = 1;
947  /* AutoNeg failed to achieve a link, so we'll call
948  * e1000_check_for_link. This routine will force the link up if
949  * we detect a signal. This will allow us to communicate with
950  * non-autonegotiating link partners.
951  */
952  ret_val = e1000_check_for_link(hw);
953  if (ret_val) {
954  e_dbg("Error while checking for link\n");
955  return ret_val;
956  }
957  hw->autoneg_failed = 0;
958  } else {
959  hw->autoneg_failed = 0;
960  e_dbg("Valid Link Found\n");
961  }
962  } else {
963  e_dbg("No Signal Detected\n");
964  }
965  return E1000_SUCCESS;
966 }
967 
974 static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw)
975 {
976  s32 ret_val;
977 
978  /* SW reset the PHY so all changes take effect */
979  ret_val = e1000_phy_reset(hw);
980  if (ret_val) {
981  e_dbg("Error Resetting the PHY\n");
982  return ret_val;
983  }
984 
985  return E1000_SUCCESS;
986 }
987 
988 static s32 gbe_dhg_phy_setup(struct e1000_hw *hw)
989 {
990  s32 ret_val;
991  u32 ctrl_aux;
992 
993  switch (hw->phy_type) {
994  case e1000_phy_8211:
995  ret_val = e1000_copper_link_rtl_setup(hw);
996  if (ret_val) {
997  e_dbg("e1000_copper_link_rtl_setup failed!\n");
998  return ret_val;
999  }
1000  break;
1001  case e1000_phy_8201:
1002  /* Set RMII mode */
1003  ctrl_aux = er32(CTL_AUX);
1004  ctrl_aux |= E1000_CTL_AUX_RMII;
1005  ew32(CTL_AUX, ctrl_aux);
1006  E1000_WRITE_FLUSH();
1007 
1008  /* Disable the J/K bits required for receive */
1009  ctrl_aux = er32(CTL_AUX);
1010  ctrl_aux |= 0x4;
1011  ctrl_aux &= ~0x2;
1012  ew32(CTL_AUX, ctrl_aux);
1013  E1000_WRITE_FLUSH();
1014  ret_val = e1000_copper_link_rtl_setup(hw);
1015 
1016  if (ret_val) {
1017  e_dbg("e1000_copper_link_rtl_setup failed!\n");
1018  return ret_val;
1019  }
1020  break;
1021  default:
1022  e_dbg("Error Resetting the PHY\n");
1023  return E1000_ERR_PHY_TYPE;
1024  }
1025 
1026  return E1000_SUCCESS;
1027 }
1028 
1035 static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
1036 {
1037  u32 ctrl;
1038  s32 ret_val;
1039  u16 phy_data;
1040 
1041  e_dbg("e1000_copper_link_preconfig");
1042 
1043  ctrl = er32(CTRL);
1044  /* With 82543, we need to force speed and duplex on the MAC equal to what
1045  * the PHY speed and duplex configuration is. In addition, we need to
1046  * perform a hardware reset on the PHY to take it out of reset.
1047  */
1048  if (hw->mac_type > e1000_82543) {
1049  ctrl |= E1000_CTRL_SLU;
1050  ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1051  ew32(CTRL, ctrl);
1052  } else {
1053  ctrl |=
1054  (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1055  ew32(CTRL, ctrl);
1056  ret_val = e1000_phy_hw_reset(hw);
1057  if (ret_val)
1058  return ret_val;
1059  }
1060 
1061  /* Make sure we have a valid PHY */
1062  ret_val = e1000_detect_gig_phy(hw);
1063  if (ret_val) {
1064  e_dbg("Error, did not detect valid phy.\n");
1065  return ret_val;
1066  }
1067  e_dbg("Phy ID = %x\n", hw->phy_id);
1068 
1069  /* Set PHY to class A mode (if necessary) */
1070  ret_val = e1000_set_phy_mode(hw);
1071  if (ret_val)
1072  return ret_val;
1073 
1074  if ((hw->mac_type == e1000_82545_rev_3) ||
1075  (hw->mac_type == e1000_82546_rev_3)) {
1076  ret_val =
1077  e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1078  phy_data |= 0x00000008;
1079  ret_val =
1080  e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1081  }
1082 
1083  if (hw->mac_type <= e1000_82543 ||
1084  hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1085  hw->mac_type == e1000_82541_rev_2
1086  || hw->mac_type == e1000_82547_rev_2)
1087  hw->phy_reset_disable = false;
1088 
1089  return E1000_SUCCESS;
1090 }
1091 
1096 static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1097 {
1098  u32 led_ctrl;
1099  s32 ret_val;
1100  u16 phy_data;
1101 
1102  e_dbg("e1000_copper_link_igp_setup");
1103 
1104  if (hw->phy_reset_disable)
1105  return E1000_SUCCESS;
1106 
1107  ret_val = e1000_phy_reset(hw);
1108  if (ret_val) {
1109  e_dbg("Error Resetting the PHY\n");
1110  return ret_val;
1111  }
1112 
1113  /* Wait 15ms for MAC to configure PHY from eeprom settings */
1114  msleep(15);
1115  /* Configure activity LED after PHY reset */
1116  led_ctrl = er32(LEDCTL);
1117  led_ctrl &= IGP_ACTIVITY_LED_MASK;
1118  led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1119  ew32(LEDCTL, led_ctrl);
1120 
1121  /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1122  if (hw->phy_type == e1000_phy_igp) {
1123  /* disable lplu d3 during driver init */
1124  ret_val = e1000_set_d3_lplu_state(hw, false);
1125  if (ret_val) {
1126  e_dbg("Error Disabling LPLU D3\n");
1127  return ret_val;
1128  }
1129  }
1130 
1131  /* Configure mdi-mdix settings */
1132  ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1133  if (ret_val)
1134  return ret_val;
1135 
1136  if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1137  hw->dsp_config_state = e1000_dsp_config_disabled;
1138  /* Force MDI for earlier revs of the IGP PHY */
1139  phy_data &=
1140  ~(IGP01E1000_PSCR_AUTO_MDIX |
1141  IGP01E1000_PSCR_FORCE_MDI_MDIX);
1142  hw->mdix = 1;
1143 
1144  } else {
1145  hw->dsp_config_state = e1000_dsp_config_enabled;
1146  phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1147 
1148  switch (hw->mdix) {
1149  case 1:
1150  phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1151  break;
1152  case 2:
1153  phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1154  break;
1155  case 0:
1156  default:
1157  phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1158  break;
1159  }
1160  }
1161  ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1162  if (ret_val)
1163  return ret_val;
1164 
1165  /* set auto-master slave resolution settings */
1166  if (hw->autoneg) {
1167  e1000_ms_type phy_ms_setting = hw->master_slave;
1168 
1169  if (hw->ffe_config_state == e1000_ffe_config_active)
1170  hw->ffe_config_state = e1000_ffe_config_enabled;
1171 
1172  if (hw->dsp_config_state == e1000_dsp_config_activated)
1173  hw->dsp_config_state = e1000_dsp_config_enabled;
1174 
1175  /* when autonegotiation advertisement is only 1000Mbps then we
1176  * should disable SmartSpeed and enable Auto MasterSlave
1177  * resolution as hardware default. */
1178  if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1179  /* Disable SmartSpeed */
1180  ret_val =
1181  e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1182  &phy_data);
1183  if (ret_val)
1184  return ret_val;
1185  phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1186  ret_val =
1187  e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1188  phy_data);
1189  if (ret_val)
1190  return ret_val;
1191  /* Set auto Master/Slave resolution process */
1192  ret_val =
1193  e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1194  if (ret_val)
1195  return ret_val;
1196  phy_data &= ~CR_1000T_MS_ENABLE;
1197  ret_val =
1198  e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1199  if (ret_val)
1200  return ret_val;
1201  }
1202 
1203  ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1204  if (ret_val)
1205  return ret_val;
1206 
1207  /* load defaults for future use */
1208  hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1209  ((phy_data & CR_1000T_MS_VALUE) ?
1210  e1000_ms_force_master :
1211  e1000_ms_force_slave) : e1000_ms_auto;
1212 
1213  switch (phy_ms_setting) {
1214  case e1000_ms_force_master:
1215  phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1216  break;
1217  case e1000_ms_force_slave:
1218  phy_data |= CR_1000T_MS_ENABLE;
1219  phy_data &= ~(CR_1000T_MS_VALUE);
1220  break;
1221  case e1000_ms_auto:
1222  phy_data &= ~CR_1000T_MS_ENABLE;
1223  default:
1224  break;
1225  }
1226  ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1227  if (ret_val)
1228  return ret_val;
1229  }
1230 
1231  return E1000_SUCCESS;
1232 }
1233 
1238 static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1239 {
1240  s32 ret_val;
1241  u16 phy_data;
1242 
1243  e_dbg("e1000_copper_link_mgp_setup");
1244 
1245  if (hw->phy_reset_disable)
1246  return E1000_SUCCESS;
1247 
1248  /* Enable CRS on TX. This must be set for half-duplex operation. */
1249  ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1250  if (ret_val)
1251  return ret_val;
1252 
1253  phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1254 
1255  /* Options:
1256  * MDI/MDI-X = 0 (default)
1257  * 0 - Auto for all speeds
1258  * 1 - MDI mode
1259  * 2 - MDI-X mode
1260  * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1261  */
1262  phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1263 
1264  switch (hw->mdix) {
1265  case 1:
1266  phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1267  break;
1268  case 2:
1269  phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1270  break;
1271  case 3:
1272  phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1273  break;
1274  case 0:
1275  default:
1276  phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1277  break;
1278  }
1279 
1280  /* Options:
1281  * disable_polarity_correction = 0 (default)
1282  * Automatic Correction for Reversed Cable Polarity
1283  * 0 - Disabled
1284  * 1 - Enabled
1285  */
1286  phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1287  if (hw->disable_polarity_correction == 1)
1288  phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1289  ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1290  if (ret_val)
1291  return ret_val;
1292 
1293  if (hw->phy_revision < M88E1011_I_REV_4) {
1294  /* Force TX_CLK in the Extended PHY Specific Control Register
1295  * to 25MHz clock.
1296  */
1297  ret_val =
1298  e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1299  &phy_data);
1300  if (ret_val)
1301  return ret_val;
1302 
1303  phy_data |= M88E1000_EPSCR_TX_CLK_25;
1304 
1305  if ((hw->phy_revision == E1000_REVISION_2) &&
1306  (hw->phy_id == M88E1111_I_PHY_ID)) {
1307  /* Vidalia Phy, set the downshift counter to 5x */
1308  phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1309  phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1310  ret_val = e1000_write_phy_reg(hw,
1311  M88E1000_EXT_PHY_SPEC_CTRL,
1312  phy_data);
1313  if (ret_val)
1314  return ret_val;
1315  } else {
1316  /* Configure Master and Slave downshift values */
1317  phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1318  M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1319  phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1320  M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1321  ret_val = e1000_write_phy_reg(hw,
1322  M88E1000_EXT_PHY_SPEC_CTRL,
1323  phy_data);
1324  if (ret_val)
1325  return ret_val;
1326  }
1327  }
1328 
1329  /* SW Reset the PHY so all changes take effect */
1330  ret_val = e1000_phy_reset(hw);
1331  if (ret_val) {
1332  e_dbg("Error Resetting the PHY\n");
1333  return ret_val;
1334  }
1335 
1336  return E1000_SUCCESS;
1337 }
1338 
1346 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1347 {
1348  s32 ret_val;
1349  u16 phy_data;
1350 
1351  e_dbg("e1000_copper_link_autoneg");
1352 
1353  /* Perform some bounds checking on the hw->autoneg_advertised
1354  * parameter. If this variable is zero, then set it to the default.
1355  */
1356  hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1357 
1358  /* If autoneg_advertised is zero, we assume it was not defaulted
1359  * by the calling code so we set to advertise full capability.
1360  */
1361  if (hw->autoneg_advertised == 0)
1362  hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1363 
1364  /* IFE/RTL8201N PHY only supports 10/100 */
1365  if (hw->phy_type == e1000_phy_8201)
1366  hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1367 
1368  e_dbg("Reconfiguring auto-neg advertisement params\n");
1369  ret_val = e1000_phy_setup_autoneg(hw);
1370  if (ret_val) {
1371  e_dbg("Error Setting up Auto-Negotiation\n");
1372  return ret_val;
1373  }
1374  e_dbg("Restarting Auto-Neg\n");
1375 
1376  /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1377  * the Auto Neg Restart bit in the PHY control register.
1378  */
1379  ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1380  if (ret_val)
1381  return ret_val;
1382 
1383  phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1384  ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1385  if (ret_val)
1386  return ret_val;
1387 
1388  /* Does the user want to wait for Auto-Neg to complete here, or
1389  * check at a later time (for example, callback routine).
1390  */
1391  if (hw->wait_autoneg_complete) {
1392  ret_val = e1000_wait_autoneg(hw);
1393  if (ret_val) {
1394  e_dbg
1395  ("Error while waiting for autoneg to complete\n");
1396  return ret_val;
1397  }
1398  }
1399 
1400  hw->get_link_status = true;
1401 
1402  return E1000_SUCCESS;
1403 }
1404 
1418 static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1419 {
1420  s32 ret_val;
1421  e_dbg("e1000_copper_link_postconfig");
1422 
1423  if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) {
1424  e1000_config_collision_dist(hw);
1425  } else {
1426  ret_val = e1000_config_mac_to_phy(hw);
1427  if (ret_val) {
1428  e_dbg("Error configuring MAC to PHY settings\n");
1429  return ret_val;
1430  }
1431  }
1432  ret_val = e1000_config_fc_after_link_up(hw);
1433  if (ret_val) {
1434  e_dbg("Error Configuring Flow Control\n");
1435  return ret_val;
1436  }
1437 
1438  /* Config DSP to improve Giga link quality */
1439  if (hw->phy_type == e1000_phy_igp) {
1440  ret_val = e1000_config_dsp_after_link_change(hw, true);
1441  if (ret_val) {
1442  e_dbg("Error Configuring DSP after link up\n");
1443  return ret_val;
1444  }
1445  }
1446 
1447  return E1000_SUCCESS;
1448 }
1449 
1456 static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1457 {
1458  s32 ret_val;
1459  u16 i;
1460  u16 phy_data;
1461 
1462  e_dbg("e1000_setup_copper_link");
1463 
1464  /* Check if it is a valid PHY and set PHY mode if necessary. */
1465  ret_val = e1000_copper_link_preconfig(hw);
1466  if (ret_val)
1467  return ret_val;
1468 
1469  if (hw->phy_type == e1000_phy_igp) {
1470  ret_val = e1000_copper_link_igp_setup(hw);
1471  if (ret_val)
1472  return ret_val;
1473  } else if (hw->phy_type == e1000_phy_m88) {
1474  ret_val = e1000_copper_link_mgp_setup(hw);
1475  if (ret_val)
1476  return ret_val;
1477  } else {
1478  ret_val = gbe_dhg_phy_setup(hw);
1479  if (ret_val) {
1480  e_dbg("gbe_dhg_phy_setup failed!\n");
1481  return ret_val;
1482  }
1483  }
1484 
1485  if (hw->autoneg) {
1486  /* Setup autoneg and flow control advertisement
1487  * and perform autonegotiation */
1488  ret_val = e1000_copper_link_autoneg(hw);
1489  if (ret_val)
1490  return ret_val;
1491  } else {
1492  /* PHY will be set to 10H, 10F, 100H,or 100F
1493  * depending on value from forced_speed_duplex. */
1494  e_dbg("Forcing speed and duplex\n");
1495  ret_val = e1000_phy_force_speed_duplex(hw);
1496  if (ret_val) {
1497  e_dbg("Error Forcing Speed and Duplex\n");
1498  return ret_val;
1499  }
1500  }
1501 
1502  /* Check link status. Wait up to 100 microseconds for link to become
1503  * valid.
1504  */
1505  for (i = 0; i < 10; i++) {
1506  ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1507  if (ret_val)
1508  return ret_val;
1509  ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1510  if (ret_val)
1511  return ret_val;
1512 
1513  if (phy_data & MII_SR_LINK_STATUS) {
1514  /* Config the MAC and PHY after link is up */
1515  ret_val = e1000_copper_link_postconfig(hw);
1516  if (ret_val)
1517  return ret_val;
1518 
1519  e_dbg("Valid link established!!!\n");
1520  return E1000_SUCCESS;
1521  }
1522  udelay(10);
1523  }
1524 
1525  e_dbg("Unable to establish link!!!\n");
1526  return E1000_SUCCESS;
1527 }
1528 
1535 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1536 {
1537  s32 ret_val;
1538  u16 mii_autoneg_adv_reg;
1539  u16 mii_1000t_ctrl_reg;
1540 
1541  e_dbg("e1000_phy_setup_autoneg");
1542 
1543  /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1544  ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1545  if (ret_val)
1546  return ret_val;
1547 
1548  /* Read the MII 1000Base-T Control Register (Address 9). */
1549  ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1550  if (ret_val)
1551  return ret_val;
1552  else if (hw->phy_type == e1000_phy_8201)
1553  mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1554 
1555  /* Need to parse both autoneg_advertised and fc and set up
1556  * the appropriate PHY registers. First we will parse for
1557  * autoneg_advertised software override. Since we can advertise
1558  * a plethora of combinations, we need to check each bit
1559  * individually.
1560  */
1561 
1562  /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1563  * Advertisement Register (Address 4) and the 1000 mb speed bits in
1564  * the 1000Base-T Control Register (Address 9).
1565  */
1566  mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1567  mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1568 
1569  e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised);
1570 
1571  /* Do we want to advertise 10 Mb Half Duplex? */
1572  if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1573  e_dbg("Advertise 10mb Half duplex\n");
1574  mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1575  }
1576 
1577  /* Do we want to advertise 10 Mb Full Duplex? */
1578  if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1579  e_dbg("Advertise 10mb Full duplex\n");
1580  mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1581  }
1582 
1583  /* Do we want to advertise 100 Mb Half Duplex? */
1584  if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1585  e_dbg("Advertise 100mb Half duplex\n");
1586  mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1587  }
1588 
1589  /* Do we want to advertise 100 Mb Full Duplex? */
1590  if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1591  e_dbg("Advertise 100mb Full duplex\n");
1592  mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1593  }
1594 
1595  /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1596  if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1597  e_dbg
1598  ("Advertise 1000mb Half duplex requested, request denied!\n");
1599  }
1600 
1601  /* Do we want to advertise 1000 Mb Full Duplex? */
1602  if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1603  e_dbg("Advertise 1000mb Full duplex\n");
1604  mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1605  }
1606 
1607  /* Check for a software override of the flow control settings, and
1608  * setup the PHY advertisement registers accordingly. If
1609  * auto-negotiation is enabled, then software will have to set the
1610  * "PAUSE" bits to the correct value in the Auto-Negotiation
1611  * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1612  *
1613  * The possible values of the "fc" parameter are:
1614  * 0: Flow control is completely disabled
1615  * 1: Rx flow control is enabled (we can receive pause frames
1616  * but not send pause frames).
1617  * 2: Tx flow control is enabled (we can send pause frames
1618  * but we do not support receiving pause frames).
1619  * 3: Both Rx and TX flow control (symmetric) are enabled.
1620  * other: No software override. The flow control configuration
1621  * in the EEPROM is used.
1622  */
1623  switch (hw->fc) {
1624  case E1000_FC_NONE: /* 0 */
1625  /* Flow control (RX & TX) is completely disabled by a
1626  * software over-ride.
1627  */
1628  mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1629  break;
1630  case E1000_FC_RX_PAUSE: /* 1 */
1631  /* RX Flow control is enabled, and TX Flow control is
1632  * disabled, by a software over-ride.
1633  */
1634  /* Since there really isn't a way to advertise that we are
1635  * capable of RX Pause ONLY, we will advertise that we
1636  * support both symmetric and asymmetric RX PAUSE. Later
1637  * (in e1000_config_fc_after_link_up) we will disable the
1638  *hw's ability to send PAUSE frames.
1639  */
1640  mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1641  break;
1642  case E1000_FC_TX_PAUSE: /* 2 */
1643  /* TX Flow control is enabled, and RX Flow control is
1644  * disabled, by a software over-ride.
1645  */
1646  mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1647  mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1648  break;
1649  case E1000_FC_FULL: /* 3 */
1650  /* Flow control (both RX and TX) is enabled by a software
1651  * over-ride.
1652  */
1653  mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1654  break;
1655  default:
1656  e_dbg("Flow control param set incorrectly\n");
1657  return -E1000_ERR_CONFIG;
1658  }
1659 
1660  ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1661  if (ret_val)
1662  return ret_val;
1663 
1664  e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1665 
1666  if (hw->phy_type == e1000_phy_8201) {
1667  mii_1000t_ctrl_reg = 0;
1668  } else {
1669  ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1670  mii_1000t_ctrl_reg);
1671  if (ret_val)
1672  return ret_val;
1673  }
1674 
1675  return E1000_SUCCESS;
1676 }
1677 
1684 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1685 {
1686  u32 ctrl;
1687  s32 ret_val;
1688  u16 mii_ctrl_reg;
1689  u16 mii_status_reg;
1690  u16 phy_data;
1691  u16 i;
1692 
1693  e_dbg("e1000_phy_force_speed_duplex");
1694 
1695  /* Turn off Flow control if we are forcing speed and duplex. */
1696  hw->fc = E1000_FC_NONE;
1697 
1698  e_dbg("hw->fc = %d\n", hw->fc);
1699 
1700  /* Read the Device Control Register. */
1701  ctrl = er32(CTRL);
1702 
1703  /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1704  ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1705  ctrl &= ~(DEVICE_SPEED_MASK);
1706 
1707  /* Clear the Auto Speed Detect Enable bit. */
1708  ctrl &= ~E1000_CTRL_ASDE;
1709 
1710  /* Read the MII Control Register. */
1711  ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1712  if (ret_val)
1713  return ret_val;
1714 
1715  /* We need to disable autoneg in order to force link and duplex. */
1716 
1717  mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1718 
1719  /* Are we forcing Full or Half Duplex? */
1720  if (hw->forced_speed_duplex == e1000_100_full ||
1721  hw->forced_speed_duplex == e1000_10_full) {
1722  /* We want to force full duplex so we SET the full duplex bits in the
1723  * Device and MII Control Registers.
1724  */
1725  ctrl |= E1000_CTRL_FD;
1726  mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1727  e_dbg("Full Duplex\n");
1728  } else {
1729  /* We want to force half duplex so we CLEAR the full duplex bits in
1730  * the Device and MII Control Registers.
1731  */
1732  ctrl &= ~E1000_CTRL_FD;
1733  mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1734  e_dbg("Half Duplex\n");
1735  }
1736 
1737  /* Are we forcing 100Mbps??? */
1738  if (hw->forced_speed_duplex == e1000_100_full ||
1739  hw->forced_speed_duplex == e1000_100_half) {
1740  /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1741  ctrl |= E1000_CTRL_SPD_100;
1742  mii_ctrl_reg |= MII_CR_SPEED_100;
1743  mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1744  e_dbg("Forcing 100mb ");
1745  } else {
1746  /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1747  ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1748  mii_ctrl_reg |= MII_CR_SPEED_10;
1749  mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1750  e_dbg("Forcing 10mb ");
1751  }
1752 
1753  e1000_config_collision_dist(hw);
1754 
1755  /* Write the configured values back to the Device Control Reg. */
1756  ew32(CTRL, ctrl);
1757 
1758  if (hw->phy_type == e1000_phy_m88) {
1759  ret_val =
1760  e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1761  if (ret_val)
1762  return ret_val;
1763 
1764  /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1765  * forced whenever speed are duplex are forced.
1766  */
1767  phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1768  ret_val =
1769  e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1770  if (ret_val)
1771  return ret_val;
1772 
1773  e_dbg("M88E1000 PSCR: %x\n", phy_data);
1774 
1775  /* Need to reset the PHY or these changes will be ignored */
1776  mii_ctrl_reg |= MII_CR_RESET;
1777 
1778  /* Disable MDI-X support for 10/100 */
1779  } else {
1780  /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1781  * forced whenever speed or duplex are forced.
1782  */
1783  ret_val =
1784  e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1785  if (ret_val)
1786  return ret_val;
1787 
1788  phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1789  phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1790 
1791  ret_val =
1792  e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1793  if (ret_val)
1794  return ret_val;
1795  }
1796 
1797  /* Write back the modified PHY MII control register. */
1798  ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1799  if (ret_val)
1800  return ret_val;
1801 
1802  udelay(1);
1803 
1804  /* The wait_autoneg_complete flag may be a little misleading here.
1805  * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1806  * But we do want to delay for a period while forcing only so we
1807  * don't generate false No Link messages. So we will wait here
1808  * only if the user has set wait_autoneg_complete to 1, which is
1809  * the default.
1810  */
1811  if (hw->wait_autoneg_complete) {
1812  /* We will wait for autoneg to complete. */
1813  e_dbg("Waiting for forced speed/duplex link.\n");
1814  mii_status_reg = 0;
1815 
1816  /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1817  for (i = PHY_FORCE_TIME; i > 0; i--) {
1818  /* Read the MII Status Register and wait for Auto-Neg Complete bit
1819  * to be set.
1820  */
1821  ret_val =
1822  e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1823  if (ret_val)
1824  return ret_val;
1825 
1826  ret_val =
1827  e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1828  if (ret_val)
1829  return ret_val;
1830 
1831  if (mii_status_reg & MII_SR_LINK_STATUS)
1832  break;
1833  msleep(100);
1834  }
1835  if ((i == 0) && (hw->phy_type == e1000_phy_m88)) {
1836  /* We didn't get link. Reset the DSP and wait again for link. */
1837  ret_val = e1000_phy_reset_dsp(hw);
1838  if (ret_val) {
1839  e_dbg("Error Resetting PHY DSP\n");
1840  return ret_val;
1841  }
1842  }
1843  /* This loop will early-out if the link condition has been met. */
1844  for (i = PHY_FORCE_TIME; i > 0; i--) {
1845  if (mii_status_reg & MII_SR_LINK_STATUS)
1846  break;
1847  msleep(100);
1848  /* Read the MII Status Register and wait for Auto-Neg Complete bit
1849  * to be set.
1850  */
1851  ret_val =
1852  e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1853  if (ret_val)
1854  return ret_val;
1855 
1856  ret_val =
1857  e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1858  if (ret_val)
1859  return ret_val;
1860  }
1861  }
1862 
1863  if (hw->phy_type == e1000_phy_m88) {
1864  /* Because we reset the PHY above, we need to re-force TX_CLK in the
1865  * Extended PHY Specific Control Register to 25MHz clock. This value
1866  * defaults back to a 2.5MHz clock when the PHY is reset.
1867  */
1868  ret_val =
1869  e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1870  &phy_data);
1871  if (ret_val)
1872  return ret_val;
1873 
1874  phy_data |= M88E1000_EPSCR_TX_CLK_25;
1875  ret_val =
1876  e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1877  phy_data);
1878  if (ret_val)
1879  return ret_val;
1880 
1881  /* In addition, because of the s/w reset above, we need to enable CRS on
1882  * TX. This must be set for both full and half duplex operation.
1883  */
1884  ret_val =
1885  e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1886  if (ret_val)
1887  return ret_val;
1888 
1889  phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1890  ret_val =
1891  e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1892  if (ret_val)
1893  return ret_val;
1894 
1895  if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543)
1896  && (!hw->autoneg)
1897  && (hw->forced_speed_duplex == e1000_10_full
1898  || hw->forced_speed_duplex == e1000_10_half)) {
1899  ret_val = e1000_polarity_reversal_workaround(hw);
1900  if (ret_val)
1901  return ret_val;
1902  }
1903  }
1904  return E1000_SUCCESS;
1905 }
1906 
1915 void e1000_config_collision_dist(struct e1000_hw *hw)
1916 {
1917  u32 tctl, coll_dist;
1918 
1919  e_dbg("e1000_config_collision_dist");
1920 
1921  if (hw->mac_type < e1000_82543)
1922  coll_dist = E1000_COLLISION_DISTANCE_82542;
1923  else
1924  coll_dist = E1000_COLLISION_DISTANCE;
1925 
1926  tctl = er32(TCTL);
1927 
1928  tctl &= ~E1000_TCTL_COLD;
1929  tctl |= coll_dist << E1000_COLD_SHIFT;
1930 
1931  ew32(TCTL, tctl);
1932  E1000_WRITE_FLUSH();
1933 }
1934 
1944 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
1945 {
1946  u32 ctrl;
1947  s32 ret_val;
1948  u16 phy_data;
1949 
1950  e_dbg("e1000_config_mac_to_phy");
1951 
1952  /* 82544 or newer MAC, Auto Speed Detection takes care of
1953  * MAC speed/duplex configuration.*/
1954  if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100))
1955  return E1000_SUCCESS;
1956 
1957  /* Read the Device Control Register and set the bits to Force Speed
1958  * and Duplex.
1959  */
1960  ctrl = er32(CTRL);
1961  ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1962  ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1963 
1964  switch (hw->phy_type) {
1965  case e1000_phy_8201:
1966  ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1967  if (ret_val)
1968  return ret_val;
1969 
1970  if (phy_data & RTL_PHY_CTRL_FD)
1971  ctrl |= E1000_CTRL_FD;
1972  else
1973  ctrl &= ~E1000_CTRL_FD;
1974 
1975  if (phy_data & RTL_PHY_CTRL_SPD_100)
1976  ctrl |= E1000_CTRL_SPD_100;
1977  else
1978  ctrl |= E1000_CTRL_SPD_10;
1979 
1980  e1000_config_collision_dist(hw);
1981  break;
1982  default:
1983  /* Set up duplex in the Device Control and Transmit Control
1984  * registers depending on negotiated values.
1985  */
1986  ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1987  &phy_data);
1988  if (ret_val)
1989  return ret_val;
1990 
1991  if (phy_data & M88E1000_PSSR_DPLX)
1992  ctrl |= E1000_CTRL_FD;
1993  else
1994  ctrl &= ~E1000_CTRL_FD;
1995 
1996  e1000_config_collision_dist(hw);
1997 
1998  /* Set up speed in the Device Control register depending on
1999  * negotiated values.
2000  */
2001  if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2002  ctrl |= E1000_CTRL_SPD_1000;
2003  else if ((phy_data & M88E1000_PSSR_SPEED) ==
2004  M88E1000_PSSR_100MBS)
2005  ctrl |= E1000_CTRL_SPD_100;
2006  }
2007 
2008  /* Write the configured values back to the Device Control Reg. */
2009  ew32(CTRL, ctrl);
2010  return E1000_SUCCESS;
2011 }
2012 
2024 s32 e1000_force_mac_fc(struct e1000_hw *hw)
2025 {
2026  u32 ctrl;
2027 
2028  e_dbg("e1000_force_mac_fc");
2029 
2030  /* Get the current configuration of the Device Control Register */
2031  ctrl = er32(CTRL);
2032 
2033  /* Because we didn't get link via the internal auto-negotiation
2034  * mechanism (we either forced link or we got link via PHY
2035  * auto-neg), we have to manually enable/disable transmit an
2036  * receive flow control.
2037  *
2038  * The "Case" statement below enables/disable flow control
2039  * according to the "hw->fc" parameter.
2040  *
2041  * The possible values of the "fc" parameter are:
2042  * 0: Flow control is completely disabled
2043  * 1: Rx flow control is enabled (we can receive pause
2044  * frames but not send pause frames).
2045  * 2: Tx flow control is enabled (we can send pause frames
2046  * frames but we do not receive pause frames).
2047  * 3: Both Rx and TX flow control (symmetric) is enabled.
2048  * other: No other values should be possible at this point.
2049  */
2050 
2051  switch (hw->fc) {
2052  case E1000_FC_NONE:
2053  ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2054  break;
2055  case E1000_FC_RX_PAUSE:
2056  ctrl &= (~E1000_CTRL_TFCE);
2057  ctrl |= E1000_CTRL_RFCE;
2058  break;
2059  case E1000_FC_TX_PAUSE:
2060  ctrl &= (~E1000_CTRL_RFCE);
2061  ctrl |= E1000_CTRL_TFCE;
2062  break;
2063  case E1000_FC_FULL:
2064  ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2065  break;
2066  default:
2067  e_dbg("Flow control param set incorrectly\n");
2068  return -E1000_ERR_CONFIG;
2069  }
2070 
2071  /* Disable TX Flow Control for 82542 (rev 2.0) */
2072  if (hw->mac_type == e1000_82542_rev2_0)
2073  ctrl &= (~E1000_CTRL_TFCE);
2074 
2075  ew32(CTRL, ctrl);
2076  return E1000_SUCCESS;
2077 }
2078 
2090 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2091 {
2092  s32 ret_val;
2093  u16 mii_status_reg;
2094  u16 mii_nway_adv_reg;
2095  u16 mii_nway_lp_ability_reg;
2096  u16 speed;
2097  u16 duplex;
2098 
2099  e_dbg("e1000_config_fc_after_link_up");
2100 
2101  /* Check for the case where we have fiber media and auto-neg failed
2102  * so we had to force link. In this case, we need to force the
2103  * configuration of the MAC to match the "fc" parameter.
2104  */
2105  if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
2106  || ((hw->media_type == e1000_media_type_internal_serdes)
2107  && (hw->autoneg_failed))
2108  || ((hw->media_type == e1000_media_type_copper)
2109  && (!hw->autoneg))) {
2110  ret_val = e1000_force_mac_fc(hw);
2111  if (ret_val) {
2112  e_dbg("Error forcing flow control settings\n");
2113  return ret_val;
2114  }
2115  }
2116 
2117  /* Check for the case where we have copper media and auto-neg is
2118  * enabled. In this case, we need to check and see if Auto-Neg
2119  * has completed, and if so, how the PHY and link partner has
2120  * flow control configured.
2121  */
2122  if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2123  /* Read the MII Status Register and check to see if AutoNeg
2124  * has completed. We read this twice because this reg has
2125  * some "sticky" (latched) bits.
2126  */
2127  ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2128  if (ret_val)
2129  return ret_val;
2130  ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2131  if (ret_val)
2132  return ret_val;
2133 
2134  if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2135  /* The AutoNeg process has completed, so we now need to
2136  * read both the Auto Negotiation Advertisement Register
2137  * (Address 4) and the Auto_Negotiation Base Page Ability
2138  * Register (Address 5) to determine how flow control was
2139  * negotiated.
2140  */
2141  ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2142  &mii_nway_adv_reg);
2143  if (ret_val)
2144  return ret_val;
2145  ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2146  &mii_nway_lp_ability_reg);
2147  if (ret_val)
2148  return ret_val;
2149 
2150  /* Two bits in the Auto Negotiation Advertisement Register
2151  * (Address 4) and two bits in the Auto Negotiation Base
2152  * Page Ability Register (Address 5) determine flow control
2153  * for both the PHY and the link partner. The following
2154  * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2155  * 1999, describes these PAUSE resolution bits and how flow
2156  * control is determined based upon these settings.
2157  * NOTE: DC = Don't Care
2158  *
2159  * LOCAL DEVICE | LINK PARTNER
2160  * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2161  *-------|---------|-------|---------|--------------------
2162  * 0 | 0 | DC | DC | E1000_FC_NONE
2163  * 0 | 1 | 0 | DC | E1000_FC_NONE
2164  * 0 | 1 | 1 | 0 | E1000_FC_NONE
2165  * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2166  * 1 | 0 | 0 | DC | E1000_FC_NONE
2167  * 1 | DC | 1 | DC | E1000_FC_FULL
2168  * 1 | 1 | 0 | 0 | E1000_FC_NONE
2169  * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2170  *
2171  */
2172  /* Are both PAUSE bits set to 1? If so, this implies
2173  * Symmetric Flow Control is enabled at both ends. The
2174  * ASM_DIR bits are irrelevant per the spec.
2175  *
2176  * For Symmetric Flow Control:
2177  *
2178  * LOCAL DEVICE | LINK PARTNER
2179  * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2180  *-------|---------|-------|---------|--------------------
2181  * 1 | DC | 1 | DC | E1000_FC_FULL
2182  *
2183  */
2184  if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2185  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2186  /* Now we need to check if the user selected RX ONLY
2187  * of pause frames. In this case, we had to advertise
2188  * FULL flow control because we could not advertise RX
2189  * ONLY. Hence, we must now check to see if we need to
2190  * turn OFF the TRANSMISSION of PAUSE frames.
2191  */
2192  if (hw->original_fc == E1000_FC_FULL) {
2193  hw->fc = E1000_FC_FULL;
2194  e_dbg("Flow Control = FULL.\n");
2195  } else {
2196  hw->fc = E1000_FC_RX_PAUSE;
2197  e_dbg
2198  ("Flow Control = RX PAUSE frames only.\n");
2199  }
2200  }
2201  /* For receiving PAUSE frames ONLY.
2202  *
2203  * LOCAL DEVICE | LINK PARTNER
2204  * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2205  *-------|---------|-------|---------|--------------------
2206  * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2207  *
2208  */
2209  else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2210  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2211  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2212  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2213  {
2214  hw->fc = E1000_FC_TX_PAUSE;
2215  e_dbg
2216  ("Flow Control = TX PAUSE frames only.\n");
2217  }
2218  /* For transmitting PAUSE frames ONLY.
2219  *
2220  * LOCAL DEVICE | LINK PARTNER
2221  * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2222  *-------|---------|-------|---------|--------------------
2223  * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2224  *
2225  */
2226  else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2227  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2228  !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2229  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2230  {
2231  hw->fc = E1000_FC_RX_PAUSE;
2232  e_dbg
2233  ("Flow Control = RX PAUSE frames only.\n");
2234  }
2235  /* Per the IEEE spec, at this point flow control should be
2236  * disabled. However, we want to consider that we could
2237  * be connected to a legacy switch that doesn't advertise
2238  * desired flow control, but can be forced on the link
2239  * partner. So if we advertised no flow control, that is
2240  * what we will resolve to. If we advertised some kind of
2241  * receive capability (Rx Pause Only or Full Flow Control)
2242  * and the link partner advertised none, we will configure
2243  * ourselves to enable Rx Flow Control only. We can do
2244  * this safely for two reasons: If the link partner really
2245  * didn't want flow control enabled, and we enable Rx, no
2246  * harm done since we won't be receiving any PAUSE frames
2247  * anyway. If the intent on the link partner was to have
2248  * flow control enabled, then by us enabling RX only, we
2249  * can at least receive pause frames and process them.
2250  * This is a good idea because in most cases, since we are
2251  * predominantly a server NIC, more times than not we will
2252  * be asked to delay transmission of packets than asking
2253  * our link partner to pause transmission of frames.
2254  */
2255  else if ((hw->original_fc == E1000_FC_NONE ||
2256  hw->original_fc == E1000_FC_TX_PAUSE) ||
2257  hw->fc_strict_ieee) {
2258  hw->fc = E1000_FC_NONE;
2259  e_dbg("Flow Control = NONE.\n");
2260  } else {
2261  hw->fc = E1000_FC_RX_PAUSE;
2262  e_dbg
2263  ("Flow Control = RX PAUSE frames only.\n");
2264  }
2265 
2266  /* Now we need to do one last check... If we auto-
2267  * negotiated to HALF DUPLEX, flow control should not be
2268  * enabled per IEEE 802.3 spec.
2269  */
2270  ret_val =
2271  e1000_get_speed_and_duplex(hw, &speed, &duplex);
2272  if (ret_val) {
2273  e_dbg
2274  ("Error getting link speed and duplex\n");
2275  return ret_val;
2276  }
2277 
2278  if (duplex == HALF_DUPLEX)
2279  hw->fc = E1000_FC_NONE;
2280 
2281  /* Now we call a subroutine to actually force the MAC
2282  * controller to use the correct flow control settings.
2283  */
2284  ret_val = e1000_force_mac_fc(hw);
2285  if (ret_val) {
2286  e_dbg
2287  ("Error forcing flow control settings\n");
2288  return ret_val;
2289  }
2290  } else {
2291  e_dbg
2292  ("Copper PHY and Auto Neg has not completed.\n");
2293  }
2294  }
2295  return E1000_SUCCESS;
2296 }
2297 
2305 static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2306 {
2307  u32 rxcw;
2308  u32 ctrl;
2309  u32 status;
2310  s32 ret_val = E1000_SUCCESS;
2311 
2312  e_dbg("e1000_check_for_serdes_link_generic");
2313 
2314  ctrl = er32(CTRL);
2315  status = er32(STATUS);
2316  rxcw = er32(RXCW);
2317 
2318  /*
2319  * If we don't have link (auto-negotiation failed or link partner
2320  * cannot auto-negotiate), and our link partner is not trying to
2321  * auto-negotiate with us (we are receiving idles or data),
2322  * we need to force link up. We also need to give auto-negotiation
2323  * time to complete.
2324  */
2325  /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
2326  if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
2327  if (hw->autoneg_failed == 0) {
2328  hw->autoneg_failed = 1;
2329  goto out;
2330  }
2331  e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
2332 
2333  /* Disable auto-negotiation in the TXCW register */
2334  ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2335 
2336  /* Force link-up and also force full-duplex. */
2337  ctrl = er32(CTRL);
2338  ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2339  ew32(CTRL, ctrl);
2340 
2341  /* Configure Flow Control after forcing link up. */
2342  ret_val = e1000_config_fc_after_link_up(hw);
2343  if (ret_val) {
2344  e_dbg("Error configuring flow control\n");
2345  goto out;
2346  }
2347  } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2348  /*
2349  * If we are forcing link and we are receiving /C/ ordered
2350  * sets, re-enable auto-negotiation in the TXCW register
2351  * and disable forced link in the Device Control register
2352  * in an attempt to auto-negotiate with our link partner.
2353  */
2354  e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
2355  ew32(TXCW, hw->txcw);
2356  ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
2357 
2358  hw->serdes_has_link = true;
2359  } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
2360  /*
2361  * If we force link for non-auto-negotiation switch, check
2362  * link status based on MAC synchronization for internal
2363  * serdes media type.
2364  */
2365  /* SYNCH bit and IV bit are sticky. */
2366  udelay(10);
2367  rxcw = er32(RXCW);
2368  if (rxcw & E1000_RXCW_SYNCH) {
2369  if (!(rxcw & E1000_RXCW_IV)) {
2370  hw->serdes_has_link = true;
2371  e_dbg("SERDES: Link up - forced.\n");
2372  }
2373  } else {
2374  hw->serdes_has_link = false;
2375  e_dbg("SERDES: Link down - force failed.\n");
2376  }
2377  }
2378 
2379  if (E1000_TXCW_ANE & er32(TXCW)) {
2380  status = er32(STATUS);
2381  if (status & E1000_STATUS_LU) {
2382  /* SYNCH bit and IV bit are sticky, so reread rxcw. */
2383  udelay(10);
2384  rxcw = er32(RXCW);
2385  if (rxcw & E1000_RXCW_SYNCH) {
2386  if (!(rxcw & E1000_RXCW_IV)) {
2387  hw->serdes_has_link = true;
2388  e_dbg("SERDES: Link up - autoneg "
2389  "completed successfully.\n");
2390  } else {
2391  hw->serdes_has_link = false;
2392  e_dbg("SERDES: Link down - invalid"
2393  "codewords detected in autoneg.\n");
2394  }
2395  } else {
2396  hw->serdes_has_link = false;
2397  e_dbg("SERDES: Link down - no sync.\n");
2398  }
2399  } else {
2400  hw->serdes_has_link = false;
2401  e_dbg("SERDES: Link down - autoneg failed\n");
2402  }
2403  }
2404 
2405  out:
2406  return ret_val;
2407 }
2408 
2416 s32 e1000_check_for_link(struct e1000_hw *hw)
2417 {
2418  u32 rxcw = 0;
2419  u32 ctrl;
2420  u32 status;
2421  u32 rctl;
2422  u32 icr;
2423  u32 signal = 0;
2424  s32 ret_val;
2425  u16 phy_data;
2426 
2427  e_dbg("e1000_check_for_link");
2428 
2429  ctrl = er32(CTRL);
2430  status = er32(STATUS);
2431 
2432  /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be
2433  * set when the optics detect a signal. On older adapters, it will be
2434  * cleared when there is a signal. This applies to fiber media only.
2435  */
2436  if ((hw->media_type == e1000_media_type_fiber) ||
2437  (hw->media_type == e1000_media_type_internal_serdes)) {
2438  rxcw = er32(RXCW);
2439 
2440  if (hw->media_type == e1000_media_type_fiber) {
2441  signal =
2442  (hw->mac_type >
2443  e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2444  if (status & E1000_STATUS_LU)
2445  hw->get_link_status = false;
2446  }
2447  }
2448 
2449  /* If we have a copper PHY then we only want to go out to the PHY
2450  * registers to see if Auto-Neg has completed and/or if our link
2451  * status has changed. The get_link_status flag will be set if we
2452  * receive a Link Status Change interrupt or we have Rx Sequence
2453  * Errors.
2454  */
2455  if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2456  /* First we want to see if the MII Status Register reports
2457  * link. If so, then we want to get the current speed/duplex
2458  * of the PHY.
2459  * Read the register twice since the link bit is sticky.
2460  */
2461  ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2462  if (ret_val)
2463  return ret_val;
2464  ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2465  if (ret_val)
2466  return ret_val;
2467 
2468  if (phy_data & MII_SR_LINK_STATUS) {
2469  hw->get_link_status = false;
2470  /* Check if there was DownShift, must be checked immediately after
2471  * link-up */
2472  e1000_check_downshift(hw);
2473 
2474  /* If we are on 82544 or 82543 silicon and speed/duplex
2475  * are forced to 10H or 10F, then we will implement the polarity
2476  * reversal workaround. We disable interrupts first, and upon
2477  * returning, place the devices interrupt state to its previous
2478  * value except for the link status change interrupt which will
2479  * happen due to the execution of this workaround.
2480  */
2481 
2482  if ((hw->mac_type == e1000_82544
2483  || hw->mac_type == e1000_82543) && (!hw->autoneg)
2484  && (hw->forced_speed_duplex == e1000_10_full
2485  || hw->forced_speed_duplex == e1000_10_half)) {
2486  ew32(IMC, 0xffffffff);
2487  ret_val =
2488  e1000_polarity_reversal_workaround(hw);
2489  icr = er32(ICR);
2490  ew32(ICS, (icr & ~E1000_ICS_LSC));
2491  ew32(IMS, IMS_ENABLE_MASK);
2492  }
2493 
2494  } else {
2495  /* No link detected */
2496  e1000_config_dsp_after_link_change(hw, false);
2497  return 0;
2498  }
2499 
2500  /* If we are forcing speed/duplex, then we simply return since
2501  * we have already determined whether we have link or not.
2502  */
2503  if (!hw->autoneg)
2504  return -E1000_ERR_CONFIG;
2505 
2506  /* optimize the dsp settings for the igp phy */
2507  e1000_config_dsp_after_link_change(hw, true);
2508 
2509  /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2510  * have Si on board that is 82544 or newer, Auto
2511  * Speed Detection takes care of MAC speed/duplex
2512  * configuration. So we only need to configure Collision
2513  * Distance in the MAC. Otherwise, we need to force
2514  * speed/duplex on the MAC to the current PHY speed/duplex
2515  * settings.
2516  */
2517  if ((hw->mac_type >= e1000_82544) &&
2518  (hw->mac_type != e1000_ce4100))
2519  e1000_config_collision_dist(hw);
2520  else {
2521  ret_val = e1000_config_mac_to_phy(hw);
2522  if (ret_val) {
2523  e_dbg
2524  ("Error configuring MAC to PHY settings\n");
2525  return ret_val;
2526  }
2527  }
2528 
2529  /* Configure Flow Control now that Auto-Neg has completed. First, we
2530  * need to restore the desired flow control settings because we may
2531  * have had to re-autoneg with a different link partner.
2532  */
2533  ret_val = e1000_config_fc_after_link_up(hw);
2534  if (ret_val) {
2535  e_dbg("Error configuring flow control\n");
2536  return ret_val;
2537  }
2538 
2539  /* At this point we know that we are on copper and we have
2540  * auto-negotiated link. These are conditions for checking the link
2541  * partner capability register. We use the link speed to determine if
2542  * TBI compatibility needs to be turned on or off. If the link is not
2543  * at gigabit speed, then TBI compatibility is not needed. If we are
2544  * at gigabit speed, we turn on TBI compatibility.
2545  */
2546  if (hw->tbi_compatibility_en) {
2547  u16 speed, duplex;
2548  ret_val =
2549  e1000_get_speed_and_duplex(hw, &speed, &duplex);
2550  if (ret_val) {
2551  e_dbg
2552  ("Error getting link speed and duplex\n");
2553  return ret_val;
2554  }
2555  if (speed != SPEED_1000) {
2556  /* If link speed is not set to gigabit speed, we do not need
2557  * to enable TBI compatibility.
2558  */
2559  if (hw->tbi_compatibility_on) {
2560  /* If we previously were in the mode, turn it off. */
2561  rctl = er32(RCTL);
2562  rctl &= ~E1000_RCTL_SBP;
2563  ew32(RCTL, rctl);
2564  hw->tbi_compatibility_on = false;
2565  }
2566  } else {
2567  /* If TBI compatibility is was previously off, turn it on. For
2568  * compatibility with a TBI link partner, we will store bad
2569  * packets. Some frames have an additional byte on the end and
2570  * will look like CRC errors to to the hardware.
2571  */
2572  if (!hw->tbi_compatibility_on) {
2573  hw->tbi_compatibility_on = true;
2574  rctl = er32(RCTL);
2575  rctl |= E1000_RCTL_SBP;
2576  ew32(RCTL, rctl);
2577  }
2578  }
2579  }
2580  }
2581 
2582  if ((hw->media_type == e1000_media_type_fiber) ||
2583  (hw->media_type == e1000_media_type_internal_serdes))
2584  e1000_check_for_serdes_link_generic(hw);
2585 
2586  return E1000_SUCCESS;
2587 }
2588 
2597 s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
2598 {
2599  u32 status;
2600  s32 ret_val;
2601  u16 phy_data;
2602 
2603  e_dbg("e1000_get_speed_and_duplex");
2604 
2605  if (hw->mac_type >= e1000_82543) {
2606  status = er32(STATUS);
2607  if (status & E1000_STATUS_SPEED_1000) {
2608  *speed = SPEED_1000;
2609  e_dbg("1000 Mbs, ");
2610  } else if (status & E1000_STATUS_SPEED_100) {
2611  *speed = SPEED_100;
2612  e_dbg("100 Mbs, ");
2613  } else {
2614  *speed = SPEED_10;
2615  e_dbg("10 Mbs, ");
2616  }
2617 
2618  if (status & E1000_STATUS_FD) {
2619  *duplex = FULL_DUPLEX;
2620  e_dbg("Full Duplex\n");
2621  } else {
2622  *duplex = HALF_DUPLEX;
2623  e_dbg(" Half Duplex\n");
2624  }
2625  } else {
2626  e_dbg("1000 Mbs, Full Duplex\n");
2627  *speed = SPEED_1000;
2628  *duplex = FULL_DUPLEX;
2629  }
2630 
2631  /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2632  * if it is operating at half duplex. Here we set the duplex settings to
2633  * match the duplex in the link partner's capabilities.
2634  */
2635  if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2636  ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2637  if (ret_val)
2638  return ret_val;
2639 
2640  if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2641  *duplex = HALF_DUPLEX;
2642  else {
2643  ret_val =
2644  e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2645  if (ret_val)
2646  return ret_val;
2647  if ((*speed == SPEED_100
2648  && !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
2649  || (*speed == SPEED_10
2650  && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2651  *duplex = HALF_DUPLEX;
2652  }
2653  }
2654 
2655  return E1000_SUCCESS;
2656 }
2657 
2664 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2665 {
2666  s32 ret_val;
2667  u16 i;
2668  u16 phy_data;
2669 
2670  e_dbg("e1000_wait_autoneg");
2671  e_dbg("Waiting for Auto-Neg to complete.\n");
2672 
2673  /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2674  for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2675  /* Read the MII Status Register and wait for Auto-Neg
2676  * Complete bit to be set.
2677  */
2678  ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2679  if (ret_val)
2680  return ret_val;
2681  ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2682  if (ret_val)
2683  return ret_val;
2684  if (phy_data & MII_SR_AUTONEG_COMPLETE) {
2685  return E1000_SUCCESS;
2686  }
2687  msleep(100);
2688  }
2689  return E1000_SUCCESS;
2690 }
2691 
2697 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2698 {
2699  /* Raise the clock input to the Management Data Clock (by setting the MDC
2700  * bit), and then delay 10 microseconds.
2701  */
2702  ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
2703  E1000_WRITE_FLUSH();
2704  udelay(10);
2705 }
2706 
2712 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2713 {
2714  /* Lower the clock input to the Management Data Clock (by clearing the MDC
2715  * bit), and then delay 10 microseconds.
2716  */
2717  ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
2718  E1000_WRITE_FLUSH();
2719  udelay(10);
2720 }
2721 
2730 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
2731 {
2732  u32 ctrl;
2733  u32 mask;
2734 
2735  /* We need to shift "count" number of bits out to the PHY. So, the value
2736  * in the "data" parameter will be shifted out to the PHY one bit at a
2737  * time. In order to do this, "data" must be broken down into bits.
2738  */
2739  mask = 0x01;
2740  mask <<= (count - 1);
2741 
2742  ctrl = er32(CTRL);
2743 
2744  /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2745  ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2746 
2747  while (mask) {
2748  /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2749  * then raising and lowering the Management Data Clock. A "0" is
2750  * shifted out to the PHY by setting the MDIO bit to "0" and then
2751  * raising and lowering the clock.
2752  */
2753  if (data & mask)
2754  ctrl |= E1000_CTRL_MDIO;
2755  else
2756  ctrl &= ~E1000_CTRL_MDIO;
2757 
2758  ew32(CTRL, ctrl);
2759  E1000_WRITE_FLUSH();
2760 
2761  udelay(10);
2762 
2763  e1000_raise_mdi_clk(hw, &ctrl);
2764  e1000_lower_mdi_clk(hw, &ctrl);
2765 
2766  mask = mask >> 1;
2767  }
2768 }
2769 
2776 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2777 {
2778  u32 ctrl;
2779  u16 data = 0;
2780  u8 i;
2781 
2782  /* In order to read a register from the PHY, we need to shift in a total
2783  * of 18 bits from the PHY. The first two bit (turnaround) times are used
2784  * to avoid contention on the MDIO pin when a read operation is performed.
2785  * These two bits are ignored by us and thrown away. Bits are "shifted in"
2786  * by raising the input to the Management Data Clock (setting the MDC bit),
2787  * and then reading the value of the MDIO bit.
2788  */
2789  ctrl = er32(CTRL);
2790 
2791  /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2792  ctrl &= ~E1000_CTRL_MDIO_DIR;
2793  ctrl &= ~E1000_CTRL_MDIO;
2794 
2795  ew32(CTRL, ctrl);
2796  E1000_WRITE_FLUSH();
2797 
2798  /* Raise and Lower the clock before reading in the data. This accounts for
2799  * the turnaround bits. The first clock occurred when we clocked out the
2800  * last bit of the Register Address.
2801  */
2802  e1000_raise_mdi_clk(hw, &ctrl);
2803  e1000_lower_mdi_clk(hw, &ctrl);
2804 
2805  for (data = 0, i = 0; i < 16; i++) {
2806  data = data << 1;
2807  e1000_raise_mdi_clk(hw, &ctrl);
2808  ctrl = er32(CTRL);
2809  /* Check to see if we shifted in a "1". */
2810  if (ctrl & E1000_CTRL_MDIO)
2811  data |= 1;
2812  e1000_lower_mdi_clk(hw, &ctrl);
2813  }
2814 
2815  e1000_raise_mdi_clk(hw, &ctrl);
2816  e1000_lower_mdi_clk(hw, &ctrl);
2817 
2818  return data;
2819 }
2820 
2821 
2830 s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
2831 {
2832  u32 ret_val;
2833 
2834  e_dbg("e1000_read_phy_reg");
2835 
2836  if ((hw->phy_type == e1000_phy_igp) &&
2837  (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2838  ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2839  (u16) reg_addr);
2840  if (ret_val)
2841  return ret_val;
2842  }
2843 
2844  ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2845  phy_data);
2846 
2847  return ret_val;
2848 }
2849 
2850 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2851  u16 *phy_data)
2852 {
2853  u32 i;
2854  u32 mdic = 0;
2855  const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2856 
2857  e_dbg("e1000_read_phy_reg_ex");
2858 
2859  if (reg_addr > MAX_PHY_REG_ADDRESS) {
2860  e_dbg("PHY Address %d is out of range\n", reg_addr);
2861  return -E1000_ERR_PARAM;
2862  }
2863 
2864  if (hw->mac_type > e1000_82543) {
2865  /* Set up Op-code, Phy Address, and register address in the MDI
2866  * Control register. The MAC will take care of interfacing with the
2867  * PHY to retrieve the desired data.
2868  */
2869  if (hw->mac_type == e1000_ce4100) {
2870  mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2871  (phy_addr << E1000_MDIC_PHY_SHIFT) |
2872  (INTEL_CE_GBE_MDIC_OP_READ) |
2873  (INTEL_CE_GBE_MDIC_GO));
2874 
2875  writel(mdic, E1000_MDIO_CMD);
2876 
2877  /* Poll the ready bit to see if the MDI read
2878  * completed
2879  */
2880  for (i = 0; i < 64; i++) {
2881  udelay(50);
2882  mdic = readl(E1000_MDIO_CMD);
2883  if (!(mdic & INTEL_CE_GBE_MDIC_GO))
2884  break;
2885  }
2886 
2887  if (mdic & INTEL_CE_GBE_MDIC_GO) {
2888  e_dbg("MDI Read did not complete\n");
2889  return -E1000_ERR_PHY;
2890  }
2891 
2892  mdic = readl(E1000_MDIO_STS);
2893  if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) {
2894  e_dbg("MDI Read Error\n");
2895  return -E1000_ERR_PHY;
2896  }
2897  *phy_data = (u16) mdic;
2898  } else {
2899  mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2900  (phy_addr << E1000_MDIC_PHY_SHIFT) |
2901  (E1000_MDIC_OP_READ));
2902 
2903  ew32(MDIC, mdic);
2904 
2905  /* Poll the ready bit to see if the MDI read
2906  * completed
2907  */
2908  for (i = 0; i < 64; i++) {
2909  udelay(50);
2910  mdic = er32(MDIC);
2911  if (mdic & E1000_MDIC_READY)
2912  break;
2913  }
2914  if (!(mdic & E1000_MDIC_READY)) {
2915  e_dbg("MDI Read did not complete\n");
2916  return -E1000_ERR_PHY;
2917  }
2918  if (mdic & E1000_MDIC_ERROR) {
2919  e_dbg("MDI Error\n");
2920  return -E1000_ERR_PHY;
2921  }
2922  *phy_data = (u16) mdic;
2923  }
2924  } else {
2925  /* We must first send a preamble through the MDIO pin to signal the
2926  * beginning of an MII instruction. This is done by sending 32
2927  * consecutive "1" bits.
2928  */
2929  e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2930 
2931  /* Now combine the next few fields that are required for a read
2932  * operation. We use this method instead of calling the
2933  * e1000_shift_out_mdi_bits routine five different times. The format of
2934  * a MII read instruction consists of a shift out of 14 bits and is
2935  * defined as follows:
2936  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2937  * followed by a shift in of 18 bits. This first two bits shifted in
2938  * are TurnAround bits used to avoid contention on the MDIO pin when a
2939  * READ operation is performed. These two bits are thrown away
2940  * followed by a shift in of 16 bits which contains the desired data.
2941  */
2942  mdic = ((reg_addr) | (phy_addr << 5) |
2943  (PHY_OP_READ << 10) | (PHY_SOF << 12));
2944 
2945  e1000_shift_out_mdi_bits(hw, mdic, 14);
2946 
2947  /* Now that we've shifted out the read command to the MII, we need to
2948  * "shift in" the 16-bit value (18 total bits) of the requested PHY
2949  * register address.
2950  */
2951  *phy_data = e1000_shift_in_mdi_bits(hw);
2952  }
2953  return E1000_SUCCESS;
2954 }
2955 
2965 s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
2966 {
2967  u32 ret_val;
2968 
2969  e_dbg("e1000_write_phy_reg");
2970 
2971  if ((hw->phy_type == e1000_phy_igp) &&
2972  (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2973  ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2974  (u16) reg_addr);
2975  if (ret_val)
2976  return ret_val;
2977  }
2978 
2979  ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2980  phy_data);
2981 
2982  return ret_val;
2983 }
2984 
2985 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2986  u16 phy_data)
2987 {
2988  u32 i;
2989  u32 mdic = 0;
2990  const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2991 
2992  e_dbg("e1000_write_phy_reg_ex");
2993 
2994  if (reg_addr > MAX_PHY_REG_ADDRESS) {
2995  e_dbg("PHY Address %d is out of range\n", reg_addr);
2996  return -E1000_ERR_PARAM;
2997  }
2998 
2999  if (hw->mac_type > e1000_82543) {
3000  /* Set up Op-code, Phy Address, register address, and data
3001  * intended for the PHY register in the MDI Control register.
3002  * The MAC will take care of interfacing with the PHY to send
3003  * the desired data.
3004  */
3005  if (hw->mac_type == e1000_ce4100) {
3006  mdic = (((u32) phy_data) |
3007  (reg_addr << E1000_MDIC_REG_SHIFT) |
3008  (phy_addr << E1000_MDIC_PHY_SHIFT) |
3009  (INTEL_CE_GBE_MDIC_OP_WRITE) |
3010  (INTEL_CE_GBE_MDIC_GO));
3011 
3012  writel(mdic, E1000_MDIO_CMD);
3013 
3014  /* Poll the ready bit to see if the MDI read
3015  * completed
3016  */
3017  for (i = 0; i < 640; i++) {
3018  udelay(5);
3019  mdic = readl(E1000_MDIO_CMD);
3020  if (!(mdic & INTEL_CE_GBE_MDIC_GO))
3021  break;
3022  }
3023  if (mdic & INTEL_CE_GBE_MDIC_GO) {
3024  e_dbg("MDI Write did not complete\n");
3025  return -E1000_ERR_PHY;
3026  }
3027  } else {
3028  mdic = (((u32) phy_data) |
3029  (reg_addr << E1000_MDIC_REG_SHIFT) |
3030  (phy_addr << E1000_MDIC_PHY_SHIFT) |
3031  (E1000_MDIC_OP_WRITE));
3032 
3033  ew32(MDIC, mdic);
3034 
3035  /* Poll the ready bit to see if the MDI read
3036  * completed
3037  */
3038  for (i = 0; i < 641; i++) {
3039  udelay(5);
3040  mdic = er32(MDIC);
3041  if (mdic & E1000_MDIC_READY)
3042  break;
3043  }
3044  if (!(mdic & E1000_MDIC_READY)) {
3045  e_dbg("MDI Write did not complete\n");
3046  return -E1000_ERR_PHY;
3047  }
3048  }
3049  } else {
3050  /* We'll need to use the SW defined pins to shift the write command
3051  * out to the PHY. We first send a preamble to the PHY to signal the
3052  * beginning of the MII instruction. This is done by sending 32
3053  * consecutive "1" bits.
3054  */
3055  e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3056 
3057  /* Now combine the remaining required fields that will indicate a
3058  * write operation. We use this method instead of calling the
3059  * e1000_shift_out_mdi_bits routine for each field in the command. The
3060  * format of a MII write instruction is as follows:
3061  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3062  */
3063  mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3064  (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3065  mdic <<= 16;
3066  mdic |= (u32) phy_data;
3067 
3068  e1000_shift_out_mdi_bits(hw, mdic, 32);
3069  }
3070 
3071  return E1000_SUCCESS;
3072 }
3073 
3080 s32 e1000_phy_hw_reset(struct e1000_hw *hw)
3081 {
3082  u32 ctrl, ctrl_ext;
3083  u32 led_ctrl;
3084 
3085  e_dbg("e1000_phy_hw_reset");
3086 
3087  e_dbg("Resetting Phy...\n");
3088 
3089  if (hw->mac_type > e1000_82543) {
3090  /* Read the device control register and assert the E1000_CTRL_PHY_RST
3091  * bit. Then, take it out of reset.
3092  * For e1000 hardware, we delay for 10ms between the assert
3093  * and deassert.
3094  */
3095  ctrl = er32(CTRL);
3096  ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
3097  E1000_WRITE_FLUSH();
3098 
3099  msleep(10);
3100 
3101  ew32(CTRL, ctrl);
3102  E1000_WRITE_FLUSH();
3103 
3104  } else {
3105  /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3106  * bit to put the PHY into reset. Then, take it out of reset.
3107  */
3108  ctrl_ext = er32(CTRL_EXT);
3109  ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3110  ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3111  ew32(CTRL_EXT, ctrl_ext);
3112  E1000_WRITE_FLUSH();
3113  msleep(10);
3114  ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3115  ew32(CTRL_EXT, ctrl_ext);
3116  E1000_WRITE_FLUSH();
3117  }
3118  udelay(150);
3119 
3120  if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3121  /* Configure activity LED after PHY reset */
3122  led_ctrl = er32(LEDCTL);
3123  led_ctrl &= IGP_ACTIVITY_LED_MASK;
3124  led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3125  ew32(LEDCTL, led_ctrl);
3126  }
3127 
3128  /* Wait for FW to finish PHY configuration. */
3129  return e1000_get_phy_cfg_done(hw);
3130 }
3131 
3139 s32 e1000_phy_reset(struct e1000_hw *hw)
3140 {
3141  s32 ret_val;
3142  u16 phy_data;
3143 
3144  e_dbg("e1000_phy_reset");
3145 
3146  switch (hw->phy_type) {
3147  case e1000_phy_igp:
3148  ret_val = e1000_phy_hw_reset(hw);
3149  if (ret_val)
3150  return ret_val;
3151  break;
3152  default:
3153  ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3154  if (ret_val)
3155  return ret_val;
3156 
3157  phy_data |= MII_CR_RESET;
3158  ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3159  if (ret_val)
3160  return ret_val;
3161 
3162  udelay(1);
3163  break;
3164  }
3165 
3166  if (hw->phy_type == e1000_phy_igp)
3167  e1000_phy_init_script(hw);
3168 
3169  return E1000_SUCCESS;
3170 }
3171 
3178 static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
3179 {
3180  s32 phy_init_status, ret_val;
3181  u16 phy_id_high, phy_id_low;
3182  bool match = false;
3183 
3184  e_dbg("e1000_detect_gig_phy");
3185 
3186  if (hw->phy_id != 0)
3187  return E1000_SUCCESS;
3188 
3189  /* Read the PHY ID Registers to identify which PHY is onboard. */
3190  ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3191  if (ret_val)
3192  return ret_val;
3193 
3194  hw->phy_id = (u32) (phy_id_high << 16);
3195  udelay(20);
3196  ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3197  if (ret_val)
3198  return ret_val;
3199 
3200  hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK);
3201  hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK;
3202 
3203  switch (hw->mac_type) {
3204  case e1000_82543:
3205  if (hw->phy_id == M88E1000_E_PHY_ID)
3206  match = true;
3207  break;
3208  case e1000_82544:
3209  if (hw->phy_id == M88E1000_I_PHY_ID)
3210  match = true;
3211  break;
3212  case e1000_82540:
3213  case e1000_82545:
3214  case e1000_82545_rev_3:
3215  case e1000_82546:
3216  case e1000_82546_rev_3:
3217  if (hw->phy_id == M88E1011_I_PHY_ID)
3218  match = true;
3219  break;
3220  case e1000_ce4100:
3221  if ((hw->phy_id == RTL8211B_PHY_ID) ||
3222  (hw->phy_id == RTL8201N_PHY_ID) ||
3223  (hw->phy_id == M88E1118_E_PHY_ID))
3224  match = true;
3225  break;
3226  case e1000_82541:
3227  case e1000_82541_rev_2:
3228  case e1000_82547:
3229  case e1000_82547_rev_2:
3230  if (hw->phy_id == IGP01E1000_I_PHY_ID)
3231  match = true;
3232  break;
3233  default:
3234  e_dbg("Invalid MAC type %d\n", hw->mac_type);
3235  return -E1000_ERR_CONFIG;
3236  }
3237  phy_init_status = e1000_set_phy_type(hw);
3238 
3239  if ((match) && (phy_init_status == E1000_SUCCESS)) {
3240  e_dbg("PHY ID 0x%X detected\n", hw->phy_id);
3241  return E1000_SUCCESS;
3242  }
3243  e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id);
3244  return -E1000_ERR_PHY;
3245 }
3246 
3253 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
3254 {
3255  s32 ret_val;
3256  e_dbg("e1000_phy_reset_dsp");
3257 
3258  do {
3259  ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
3260  if (ret_val)
3261  break;
3262  ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
3263  if (ret_val)
3264  break;
3265  ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
3266  if (ret_val)
3267  break;
3268  ret_val = E1000_SUCCESS;
3269  } while (0);
3270 
3271  return ret_val;
3272 }
3273 
3281 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
3282  struct e1000_phy_info *phy_info)
3283 {
3284  s32 ret_val;
3285  u16 phy_data, min_length, max_length, average;
3286  e1000_rev_polarity polarity;
3287 
3288  e_dbg("e1000_phy_igp_get_info");
3289 
3290  /* The downshift status is checked only once, after link is established,
3291  * and it stored in the hw->speed_downgraded parameter. */
3292  phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3293 
3294  /* IGP01E1000 does not need to support it. */
3295  phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
3296 
3297  /* IGP01E1000 always correct polarity reversal */
3298  phy_info->polarity_correction = e1000_polarity_reversal_enabled;
3299 
3300  /* Check polarity status */
3301  ret_val = e1000_check_polarity(hw, &polarity);
3302  if (ret_val)
3303  return ret_val;
3304 
3305  phy_info->cable_polarity = polarity;
3306 
3307  ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
3308  if (ret_val)
3309  return ret_val;
3310 
3311  phy_info->mdix_mode =
3312  (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >>
3313  IGP01E1000_PSSR_MDIX_SHIFT);
3314 
3315  if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
3316  IGP01E1000_PSSR_SPEED_1000MBPS) {
3317  /* Local/Remote Receiver Information are only valid at 1000 Mbps */
3318  ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3319  if (ret_val)
3320  return ret_val;
3321 
3322  phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3323  SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3324  e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3325  phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3326  SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3327  e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3328 
3329  /* Get cable length */
3330  ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
3331  if (ret_val)
3332  return ret_val;
3333 
3334  /* Translate to old method */
3335  average = (max_length + min_length) / 2;
3336 
3337  if (average <= e1000_igp_cable_length_50)
3338  phy_info->cable_length = e1000_cable_length_50;
3339  else if (average <= e1000_igp_cable_length_80)
3340  phy_info->cable_length = e1000_cable_length_50_80;
3341  else if (average <= e1000_igp_cable_length_110)
3342  phy_info->cable_length = e1000_cable_length_80_110;
3343  else if (average <= e1000_igp_cable_length_140)
3344  phy_info->cable_length = e1000_cable_length_110_140;
3345  else
3346  phy_info->cable_length = e1000_cable_length_140;
3347  }
3348 
3349  return E1000_SUCCESS;
3350 }
3351 
3359 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
3360  struct e1000_phy_info *phy_info)
3361 {
3362  s32 ret_val;
3363  u16 phy_data;
3364  e1000_rev_polarity polarity;
3365 
3366  e_dbg("e1000_phy_m88_get_info");
3367 
3368  /* The downshift status is checked only once, after link is established,
3369  * and it stored in the hw->speed_downgraded parameter. */
3370  phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3371 
3372  ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3373  if (ret_val)
3374  return ret_val;
3375 
3376  phy_info->extended_10bt_distance =
3377  ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
3378  M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
3379  e1000_10bt_ext_dist_enable_lower :
3380  e1000_10bt_ext_dist_enable_normal;
3381 
3382  phy_info->polarity_correction =
3383  ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
3384  M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
3385  e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
3386 
3387  /* Check polarity status */
3388  ret_val = e1000_check_polarity(hw, &polarity);
3389  if (ret_val)
3390  return ret_val;
3391  phy_info->cable_polarity = polarity;
3392 
3393  ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3394  if (ret_val)
3395  return ret_val;
3396 
3397  phy_info->mdix_mode =
3398  (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >>
3399  M88E1000_PSSR_MDIX_SHIFT);
3400 
3401  if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
3402  /* Cable Length Estimation and Local/Remote Receiver Information
3403  * are only valid at 1000 Mbps.
3404  */
3405  phy_info->cable_length =
3406  (e1000_cable_length) ((phy_data &
3407  M88E1000_PSSR_CABLE_LENGTH) >>
3408  M88E1000_PSSR_CABLE_LENGTH_SHIFT);
3409 
3410  ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3411  if (ret_val)
3412  return ret_val;
3413 
3414  phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3415  SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3416  e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3417  phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3418  SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3419  e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3420 
3421  }
3422 
3423  return E1000_SUCCESS;
3424 }
3425 
3433 s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
3434 {
3435  s32 ret_val;
3436  u16 phy_data;
3437 
3438  e_dbg("e1000_phy_get_info");
3439 
3440  phy_info->cable_length = e1000_cable_length_undefined;
3441  phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3442  phy_info->cable_polarity = e1000_rev_polarity_undefined;
3443  phy_info->downshift = e1000_downshift_undefined;
3444  phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3445  phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3446  phy_info->local_rx = e1000_1000t_rx_status_undefined;
3447  phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3448 
3449  if (hw->media_type != e1000_media_type_copper) {
3450  e_dbg("PHY info is only valid for copper media\n");
3451  return -E1000_ERR_CONFIG;
3452  }
3453 
3454  ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3455  if (ret_val)
3456  return ret_val;
3457 
3458  ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3459  if (ret_val)
3460  return ret_val;
3461 
3462  if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3463  e_dbg("PHY info is only valid if link is up\n");
3464  return -E1000_ERR_CONFIG;
3465  }
3466 
3467  if (hw->phy_type == e1000_phy_igp)
3468  return e1000_phy_igp_get_info(hw, phy_info);
3469  else if ((hw->phy_type == e1000_phy_8211) ||
3470  (hw->phy_type == e1000_phy_8201))
3471  return E1000_SUCCESS;
3472  else
3473  return e1000_phy_m88_get_info(hw, phy_info);
3474 }
3475 
3476 s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
3477 {
3478  e_dbg("e1000_validate_mdi_settings");
3479 
3480  if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3481  e_dbg("Invalid MDI setting detected\n");
3482  hw->mdix = 1;
3483  return -E1000_ERR_CONFIG;
3484  }
3485  return E1000_SUCCESS;
3486 }
3487 
3495 s32 e1000_init_eeprom_params(struct e1000_hw *hw)
3496 {
3497  struct e1000_eeprom_info *eeprom = &hw->eeprom;
3498  u32 eecd = er32(EECD);
3499  s32 ret_val = E1000_SUCCESS;
3500  u16 eeprom_size;
3501 
3502  e_dbg("e1000_init_eeprom_params");
3503 
3504  switch (hw->mac_type) {
3505  case e1000_82542_rev2_0:
3506  case e1000_82542_rev2_1:
3507  case e1000_82543:
3508  case e1000_82544:
3509  eeprom->type = e1000_eeprom_microwire;
3510  eeprom->word_size = 64;
3511  eeprom->opcode_bits = 3;
3512  eeprom->address_bits = 6;
3513  eeprom->delay_usec = 50;
3514  break;
3515  case e1000_82540:
3516  case e1000_82545:
3517  case e1000_82545_rev_3:
3518  case e1000_82546:
3519  case e1000_82546_rev_3:
3520  eeprom->type = e1000_eeprom_microwire;
3521  eeprom->opcode_bits = 3;
3522  eeprom->delay_usec = 50;
3523  if (eecd & E1000_EECD_SIZE) {
3524  eeprom->word_size = 256;
3525  eeprom->address_bits = 8;
3526  } else {
3527  eeprom->word_size = 64;
3528  eeprom->address_bits = 6;
3529  }
3530  break;
3531  case e1000_82541:
3532  case e1000_82541_rev_2:
3533  case e1000_82547:
3534  case e1000_82547_rev_2:
3535  if (eecd & E1000_EECD_TYPE) {
3536  eeprom->type = e1000_eeprom_spi;
3537  eeprom->opcode_bits = 8;
3538  eeprom->delay_usec = 1;
3539  if (eecd & E1000_EECD_ADDR_BITS) {
3540  eeprom->page_size = 32;
3541  eeprom->address_bits = 16;
3542  } else {
3543  eeprom->page_size = 8;
3544  eeprom->address_bits = 8;
3545  }
3546  } else {
3547  eeprom->type = e1000_eeprom_microwire;
3548  eeprom->opcode_bits = 3;
3549  eeprom->delay_usec = 50;
3550  if (eecd & E1000_EECD_ADDR_BITS) {
3551  eeprom->word_size = 256;
3552  eeprom->address_bits = 8;
3553  } else {
3554  eeprom->word_size = 64;
3555  eeprom->address_bits = 6;
3556  }
3557  }
3558  break;
3559  default:
3560  break;
3561  }
3562 
3563  if (eeprom->type == e1000_eeprom_spi) {
3564  /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
3565  * 32KB (incremented by powers of 2).
3566  */
3567  /* Set to default value for initial eeprom read. */
3568  eeprom->word_size = 64;
3569  ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3570  if (ret_val)
3571  return ret_val;
3572  eeprom_size =
3573  (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3574  /* 256B eeprom size was not supported in earlier hardware, so we
3575  * bump eeprom_size up one to ensure that "1" (which maps to 256B)
3576  * is never the result used in the shifting logic below. */
3577  if (eeprom_size)
3578  eeprom_size++;
3579 
3580  eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3581  }
3582  return ret_val;
3583 }
3584 
3590 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
3591 {
3592  /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3593  * wait <delay> microseconds.
3594  */
3595  *eecd = *eecd | E1000_EECD_SK;
3596  ew32(EECD, *eecd);
3597  E1000_WRITE_FLUSH();
3598  udelay(hw->eeprom.delay_usec);
3599 }
3600 
3606 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
3607 {
3608  /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3609  * wait 50 microseconds.
3610  */
3611  *eecd = *eecd & ~E1000_EECD_SK;
3612  ew32(EECD, *eecd);
3613  E1000_WRITE_FLUSH();
3614  udelay(hw->eeprom.delay_usec);
3615 }
3616 
3623 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
3624 {
3625  struct e1000_eeprom_info *eeprom = &hw->eeprom;
3626  u32 eecd;
3627  u32 mask;
3628 
3629  /* We need to shift "count" bits out to the EEPROM. So, value in the
3630  * "data" parameter will be shifted out to the EEPROM one bit at a time.
3631  * In order to do this, "data" must be broken down into bits.
3632  */
3633  mask = 0x01 << (count - 1);
3634  eecd = er32(EECD);
3635  if (eeprom->type == e1000_eeprom_microwire) {
3636  eecd &= ~E1000_EECD_DO;
3637  } else if (eeprom->type == e1000_eeprom_spi) {
3638  eecd |= E1000_EECD_DO;
3639  }
3640  do {
3641  /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3642  * and then raising and then lowering the clock (the SK bit controls
3643  * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3644  * by setting "DI" to "0" and then raising and then lowering the clock.
3645  */
3646  eecd &= ~E1000_EECD_DI;
3647 
3648  if (data & mask)
3649  eecd |= E1000_EECD_DI;
3650 
3651  ew32(EECD, eecd);
3652  E1000_WRITE_FLUSH();
3653 
3654  udelay(eeprom->delay_usec);
3655 
3656  e1000_raise_ee_clk(hw, &eecd);
3657  e1000_lower_ee_clk(hw, &eecd);
3658 
3659  mask = mask >> 1;
3660 
3661  } while (mask);
3662 
3663  /* We leave the "DI" bit set to "0" when we leave this routine. */
3664  eecd &= ~E1000_EECD_DI;
3665  ew32(EECD, eecd);
3666 }
3667 
3673 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
3674 {
3675  u32 eecd;
3676  u32 i;
3677  u16 data;
3678 
3679  /* In order to read a register from the EEPROM, we need to shift 'count'
3680  * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3681  * input to the EEPROM (setting the SK bit), and then reading the value of
3682  * the "DO" bit. During this "shifting in" process the "DI" bit should
3683  * always be clear.
3684  */
3685 
3686  eecd = er32(EECD);
3687 
3688  eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3689  data = 0;
3690 
3691  for (i = 0; i < count; i++) {
3692  data = data << 1;
3693  e1000_raise_ee_clk(hw, &eecd);
3694 
3695  eecd = er32(EECD);
3696 
3697  eecd &= ~(E1000_EECD_DI);
3698  if (eecd & E1000_EECD_DO)
3699  data |= 1;
3700 
3701  e1000_lower_ee_clk(hw, &eecd);
3702  }
3703 
3704  return data;
3705 }
3706 
3714 static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
3715 {
3716  struct e1000_eeprom_info *eeprom = &hw->eeprom;
3717  u32 eecd, i = 0;
3718 
3719  e_dbg("e1000_acquire_eeprom");
3720 
3721  eecd = er32(EECD);
3722 
3723  /* Request EEPROM Access */
3724  if (hw->mac_type > e1000_82544) {
3725  eecd |= E1000_EECD_REQ;
3726  ew32(EECD, eecd);
3727  eecd = er32(EECD);
3728  while ((!(eecd & E1000_EECD_GNT)) &&
3729  (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3730  i++;
3731  udelay(5);
3732  eecd = er32(EECD);
3733  }
3734  if (!(eecd & E1000_EECD_GNT)) {
3735  eecd &= ~E1000_EECD_REQ;
3736  ew32(EECD, eecd);
3737  e_dbg("Could not acquire EEPROM grant\n");
3738  return -E1000_ERR_EEPROM;
3739  }
3740  }
3741 
3742  /* Setup EEPROM for Read/Write */
3743 
3744  if (eeprom->type == e1000_eeprom_microwire) {
3745  /* Clear SK and DI */
3746  eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3747  ew32(EECD, eecd);
3748 
3749  /* Set CS */
3750  eecd |= E1000_EECD_CS;
3751  ew32(EECD, eecd);
3752  } else if (eeprom->type == e1000_eeprom_spi) {
3753  /* Clear SK and CS */
3754  eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3755  ew32(EECD, eecd);
3756  E1000_WRITE_FLUSH();
3757  udelay(1);
3758  }
3759 
3760  return E1000_SUCCESS;
3761 }
3762 
3767 static void e1000_standby_eeprom(struct e1000_hw *hw)
3768 {
3769  struct e1000_eeprom_info *eeprom = &hw->eeprom;
3770  u32 eecd;
3771 
3772  eecd = er32(EECD);
3773 
3774  if (eeprom->type == e1000_eeprom_microwire) {
3775  eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3776  ew32(EECD, eecd);
3777  E1000_WRITE_FLUSH();
3778  udelay(eeprom->delay_usec);
3779 
3780  /* Clock high */
3781  eecd |= E1000_EECD_SK;
3782  ew32(EECD, eecd);
3783  E1000_WRITE_FLUSH();
3784  udelay(eeprom->delay_usec);
3785 
3786  /* Select EEPROM */
3787  eecd |= E1000_EECD_CS;
3788  ew32(EECD, eecd);
3789  E1000_WRITE_FLUSH();
3790  udelay(eeprom->delay_usec);
3791 
3792  /* Clock low */
3793  eecd &= ~E1000_EECD_SK;
3794  ew32(EECD, eecd);
3795  E1000_WRITE_FLUSH();
3796  udelay(eeprom->delay_usec);
3797  } else if (eeprom->type == e1000_eeprom_spi) {
3798  /* Toggle CS to flush commands */
3799  eecd |= E1000_EECD_CS;
3800  ew32(EECD, eecd);
3801  E1000_WRITE_FLUSH();
3802  udelay(eeprom->delay_usec);
3803  eecd &= ~E1000_EECD_CS;
3804  ew32(EECD, eecd);
3805  E1000_WRITE_FLUSH();
3806  udelay(eeprom->delay_usec);
3807  }
3808 }
3809 
3816 static void e1000_release_eeprom(struct e1000_hw *hw)
3817 {
3818  u32 eecd;
3819 
3820  e_dbg("e1000_release_eeprom");
3821 
3822  eecd = er32(EECD);
3823 
3824  if (hw->eeprom.type == e1000_eeprom_spi) {
3825  eecd |= E1000_EECD_CS; /* Pull CS high */
3826  eecd &= ~E1000_EECD_SK; /* Lower SCK */
3827 
3828  ew32(EECD, eecd);
3829  E1000_WRITE_FLUSH();
3830 
3831  udelay(hw->eeprom.delay_usec);
3832  } else if (hw->eeprom.type == e1000_eeprom_microwire) {
3833  /* cleanup eeprom */
3834 
3835  /* CS on Microwire is active-high */
3836  eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3837 
3838  ew32(EECD, eecd);
3839 
3840  /* Rising edge of clock */
3841  eecd |= E1000_EECD_SK;
3842  ew32(EECD, eecd);
3843  E1000_WRITE_FLUSH();
3844  udelay(hw->eeprom.delay_usec);
3845 
3846  /* Falling edge of clock */
3847  eecd &= ~E1000_EECD_SK;
3848  ew32(EECD, eecd);
3849  E1000_WRITE_FLUSH();
3850  udelay(hw->eeprom.delay_usec);
3851  }
3852 
3853  /* Stop requesting EEPROM access */
3854  if (hw->mac_type > e1000_82544) {
3855  eecd &= ~E1000_EECD_REQ;
3856  ew32(EECD, eecd);
3857  }
3858 }
3859 
3864 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3865 {
3866  u16 retry_count = 0;
3867  u8 spi_stat_reg;
3868 
3869  e_dbg("e1000_spi_eeprom_ready");
3870 
3871  /* Read "Status Register" repeatedly until the LSB is cleared. The
3872  * EEPROM will signal that the command has been completed by clearing
3873  * bit 0 of the internal status register. If it's not cleared within
3874  * 5 milliseconds, then error out.
3875  */
3876  retry_count = 0;
3877  do {
3878  e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3879  hw->eeprom.opcode_bits);
3880  spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8);
3881  if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3882  break;
3883 
3884  udelay(5);
3885  retry_count += 5;
3886 
3887  e1000_standby_eeprom(hw);
3888  } while (retry_count < EEPROM_MAX_RETRY_SPI);
3889 
3890  /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3891  * only 0-5mSec on 5V devices)
3892  */
3893  if (retry_count >= EEPROM_MAX_RETRY_SPI) {
3894  e_dbg("SPI EEPROM Status error\n");
3895  return -E1000_ERR_EEPROM;
3896  }
3897 
3898  return E1000_SUCCESS;
3899 }
3900 
3908 s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
3909 {
3910  s32 ret;
3911  spin_lock(&e1000_eeprom_lock);
3912  ret = e1000_do_read_eeprom(hw, offset, words, data);
3913  spin_unlock(&e1000_eeprom_lock);
3914  return ret;
3915 }
3916 
3917 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3918  u16 *data)
3919 {
3920  struct e1000_eeprom_info *eeprom = &hw->eeprom;
3921  u32 i = 0;
3922 
3923  e_dbg("e1000_read_eeprom");
3924 
3925  if (hw->mac_type == e1000_ce4100) {
3926  GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words,
3927  data);
3928  return E1000_SUCCESS;
3929  }
3930 
3931  /* If eeprom is not yet detected, do so now */
3932  if (eeprom->word_size == 0)
3933  e1000_init_eeprom_params(hw);
3934 
3935  /* A check for invalid values: offset too large, too many words, and not
3936  * enough words.
3937  */
3938  if ((offset >= eeprom->word_size)
3939  || (words > eeprom->word_size - offset) || (words == 0)) {
3940  e_dbg("\"words\" parameter out of bounds. Words = %d,"
3941  "size = %d\n", offset, eeprom->word_size);
3942  return -E1000_ERR_EEPROM;
3943  }
3944 
3945  /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
3946  * directly. In this case, we need to acquire the EEPROM so that
3947  * FW or other port software does not interrupt.
3948  */
3949  /* Prepare the EEPROM for bit-bang reading */
3950  if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3951  return -E1000_ERR_EEPROM;
3952 
3953  /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
3954  * acquired the EEPROM at this point, so any returns should release it */
3955  if (eeprom->type == e1000_eeprom_spi) {
3956  u16 word_in;
3957  u8 read_opcode = EEPROM_READ_OPCODE_SPI;
3958 
3959  if (e1000_spi_eeprom_ready(hw)) {
3960  e1000_release_eeprom(hw);
3961  return -E1000_ERR_EEPROM;
3962  }
3963 
3964  e1000_standby_eeprom(hw);
3965 
3966  /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3967  if ((eeprom->address_bits == 8) && (offset >= 128))
3968  read_opcode |= EEPROM_A8_OPCODE_SPI;
3969 
3970  /* Send the READ command (opcode + addr) */
3971  e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3972  e1000_shift_out_ee_bits(hw, (u16) (offset * 2),
3973  eeprom->address_bits);
3974 
3975  /* Read the data. The address of the eeprom internally increments with
3976  * each byte (spi) being read, saving on the overhead of eeprom setup
3977  * and tear-down. The address counter will roll over if reading beyond
3978  * the size of the eeprom, thus allowing the entire memory to be read
3979  * starting from any offset. */
3980  for (i = 0; i < words; i++) {
3981  word_in = e1000_shift_in_ee_bits(hw, 16);
3982  data[i] = (word_in >> 8) | (word_in << 8);
3983  }
3984  } else if (eeprom->type == e1000_eeprom_microwire) {
3985  for (i = 0; i < words; i++) {
3986  /* Send the READ command (opcode + addr) */
3987  e1000_shift_out_ee_bits(hw,
3988  EEPROM_READ_OPCODE_MICROWIRE,
3989  eeprom->opcode_bits);
3990  e1000_shift_out_ee_bits(hw, (u16) (offset + i),
3991  eeprom->address_bits);
3992 
3993  /* Read the data. For microwire, each word requires the overhead
3994  * of eeprom setup and tear-down. */
3995  data[i] = e1000_shift_in_ee_bits(hw, 16);
3996  e1000_standby_eeprom(hw);
3997  }
3998  }
3999 
4000  /* End this read operation */
4001  e1000_release_eeprom(hw);
4002 
4003  return E1000_SUCCESS;
4004 }
4005 
4014 s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
4015 {
4016  u16 checksum = 0;
4017  u16 i, eeprom_data;
4018 
4019  e_dbg("e1000_validate_eeprom_checksum");
4020 
4021  for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
4022  if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4023  e_dbg("EEPROM Read Error\n");
4024  return -E1000_ERR_EEPROM;
4025  }
4026  checksum += eeprom_data;
4027  }
4028 
4029 #ifdef CONFIG_PARISC
4030  /* This is a signature and not a checksum on HP c8000 */
4031  if ((hw->subsystem_vendor_id == 0x103C) && (eeprom_data == 0x16d6))
4032  return E1000_SUCCESS;
4033 
4034 #endif
4035  if (checksum == (u16) EEPROM_SUM)
4036  return E1000_SUCCESS;
4037  else {
4038  e_dbg("EEPROM Checksum Invalid\n");
4039  return -E1000_ERR_EEPROM;
4040  }
4041 }
4042 
4050 s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
4051 {
4052  u16 checksum = 0;
4053  u16 i, eeprom_data;
4054 
4055  e_dbg("e1000_update_eeprom_checksum");
4056 
4057  for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
4058  if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4059  e_dbg("EEPROM Read Error\n");
4060  return -E1000_ERR_EEPROM;
4061  }
4062  checksum += eeprom_data;
4063  }
4064  checksum = (u16) EEPROM_SUM - checksum;
4065  if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
4066  e_dbg("EEPROM Write Error\n");
4067  return -E1000_ERR_EEPROM;
4068  }
4069  return E1000_SUCCESS;
4070 }
4071 
4082 s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
4083 {
4084  s32 ret;
4085  spin_lock(&e1000_eeprom_lock);
4086  ret = e1000_do_write_eeprom(hw, offset, words, data);
4087  spin_unlock(&e1000_eeprom_lock);
4088  return ret;
4089 }
4090 
4091 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
4092  u16 *data)
4093 {
4094  struct e1000_eeprom_info *eeprom = &hw->eeprom;
4095  s32 status = 0;
4096 
4097  e_dbg("e1000_write_eeprom");
4098 
4099  if (hw->mac_type == e1000_ce4100) {
4100  GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words,
4101  data);
4102  return E1000_SUCCESS;
4103  }
4104 
4105  /* If eeprom is not yet detected, do so now */
4106  if (eeprom->word_size == 0)
4107  e1000_init_eeprom_params(hw);
4108 
4109  /* A check for invalid values: offset too large, too many words, and not
4110  * enough words.
4111  */
4112  if ((offset >= eeprom->word_size)
4113  || (words > eeprom->word_size - offset) || (words == 0)) {
4114  e_dbg("\"words\" parameter out of bounds\n");
4115  return -E1000_ERR_EEPROM;
4116  }
4117 
4118  /* Prepare the EEPROM for writing */
4119  if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4120  return -E1000_ERR_EEPROM;
4121 
4122  if (eeprom->type == e1000_eeprom_microwire) {
4123  status = e1000_write_eeprom_microwire(hw, offset, words, data);
4124  } else {
4125  status = e1000_write_eeprom_spi(hw, offset, words, data);
4126  msleep(10);
4127  }
4128 
4129  /* Done with writing */
4130  e1000_release_eeprom(hw);
4131 
4132  return status;
4133 }
4134 
4142 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
4143  u16 *data)
4144 {
4145  struct e1000_eeprom_info *eeprom = &hw->eeprom;
4146  u16 widx = 0;
4147 
4148  e_dbg("e1000_write_eeprom_spi");
4149 
4150  while (widx < words) {
4151  u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
4152 
4153  if (e1000_spi_eeprom_ready(hw))
4154  return -E1000_ERR_EEPROM;
4155 
4156  e1000_standby_eeprom(hw);
4157 
4158  /* Send the WRITE ENABLE command (8 bit opcode ) */
4159  e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
4160  eeprom->opcode_bits);
4161 
4162  e1000_standby_eeprom(hw);
4163 
4164  /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4165  if ((eeprom->address_bits == 8) && (offset >= 128))
4166  write_opcode |= EEPROM_A8_OPCODE_SPI;
4167 
4168  /* Send the Write command (8-bit opcode + addr) */
4169  e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
4170 
4171  e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2),
4172  eeprom->address_bits);
4173 
4174  /* Send the data */
4175 
4176  /* Loop to allow for up to whole page write (32 bytes) of eeprom */
4177  while (widx < words) {
4178  u16 word_out = data[widx];
4179  word_out = (word_out >> 8) | (word_out << 8);
4180  e1000_shift_out_ee_bits(hw, word_out, 16);
4181  widx++;
4182 
4183  /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
4184  * operation, while the smaller eeproms are capable of an 8-byte
4185  * PAGE WRITE operation. Break the inner loop to pass new address
4186  */
4187  if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
4188  e1000_standby_eeprom(hw);
4189  break;
4190  }
4191  }
4192  }
4193 
4194  return E1000_SUCCESS;
4195 }
4196 
4204 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
4205  u16 words, u16 *data)
4206 {
4207  struct e1000_eeprom_info *eeprom = &hw->eeprom;
4208  u32 eecd;
4209  u16 words_written = 0;
4210  u16 i = 0;
4211 
4212  e_dbg("e1000_write_eeprom_microwire");
4213 
4214  /* Send the write enable command to the EEPROM (3-bit opcode plus
4215  * 6/8-bit dummy address beginning with 11). It's less work to include
4216  * the 11 of the dummy address as part of the opcode than it is to shift
4217  * it over the correct number of bits for the address. This puts the
4218  * EEPROM into write/erase mode.
4219  */
4220  e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
4221  (u16) (eeprom->opcode_bits + 2));
4222 
4223  e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
4224 
4225  /* Prepare the EEPROM */
4226  e1000_standby_eeprom(hw);
4227 
4228  while (words_written < words) {
4229  /* Send the Write command (3-bit opcode + addr) */
4230  e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
4231  eeprom->opcode_bits);
4232 
4233  e1000_shift_out_ee_bits(hw, (u16) (offset + words_written),
4234  eeprom->address_bits);
4235 
4236  /* Send the data */
4237  e1000_shift_out_ee_bits(hw, data[words_written], 16);
4238 
4239  /* Toggle the CS line. This in effect tells the EEPROM to execute
4240  * the previous command.
4241  */
4242  e1000_standby_eeprom(hw);
4243 
4244  /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
4245  * signal that the command has been completed by raising the DO signal.
4246  * If DO does not go high in 10 milliseconds, then error out.
4247  */
4248  for (i = 0; i < 200; i++) {
4249  eecd = er32(EECD);
4250  if (eecd & E1000_EECD_DO)
4251  break;
4252  udelay(50);
4253  }
4254  if (i == 200) {
4255  e_dbg("EEPROM Write did not complete\n");
4256  return -E1000_ERR_EEPROM;
4257  }
4258 
4259  /* Recover from write */
4260  e1000_standby_eeprom(hw);
4261 
4262  words_written++;
4263  }
4264 
4265  /* Send the write disable command to the EEPROM (3-bit opcode plus
4266  * 6/8-bit dummy address beginning with 10). It's less work to include
4267  * the 10 of the dummy address as part of the opcode than it is to shift
4268  * it over the correct number of bits for the address. This takes the
4269  * EEPROM out of write/erase mode.
4270  */
4271  e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
4272  (u16) (eeprom->opcode_bits + 2));
4273 
4274  e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
4275 
4276  return E1000_SUCCESS;
4277 }
4278 
4286 s32 e1000_read_mac_addr(struct e1000_hw *hw)
4287 {
4288  u16 offset;
4289  u16 eeprom_data, i;
4290 
4291  e_dbg("e1000_read_mac_addr");
4292 
4293  for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
4294  offset = i >> 1;
4295  if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4296  e_dbg("EEPROM Read Error\n");
4297  return -E1000_ERR_EEPROM;
4298  }
4299  hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF);
4300  hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8);
4301  }
4302 
4303  switch (hw->mac_type) {
4304  default:
4305  break;
4306  case e1000_82546:
4307  case e1000_82546_rev_3:
4308  if (er32(STATUS) & E1000_STATUS_FUNC_1)
4309  hw->perm_mac_addr[5] ^= 0x01;
4310  break;
4311  }
4312 
4313  for (i = 0; i < NODE_ADDRESS_SIZE; i++)
4314  hw->mac_addr[i] = hw->perm_mac_addr[i];
4315  return E1000_SUCCESS;
4316 }
4317 
4326 static void e1000_init_rx_addrs(struct e1000_hw *hw)
4327 {
4328  u32 i;
4329  u32 rar_num;
4330 
4331  e_dbg("e1000_init_rx_addrs");
4332 
4333  /* Setup the receive address. */
4334  e_dbg("Programming MAC Address into RAR[0]\n");
4335 
4336  e1000_rar_set(hw, hw->mac_addr, 0);
4337 
4338  rar_num = E1000_RAR_ENTRIES;
4339 
4340  /* Zero out the other 15 receive addresses. */
4341  e_dbg("Clearing RAR[1-15]\n");
4342  for (i = 1; i < rar_num; i++) {
4343  E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4344  E1000_WRITE_FLUSH();
4345  E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4346  E1000_WRITE_FLUSH();
4347  }
4348 }
4349 
4355 u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
4356 {
4357  u32 hash_value = 0;
4358 
4359  /* The portion of the address that is used for the hash table is
4360  * determined by the mc_filter_type setting.
4361  */
4362  switch (hw->mc_filter_type) {
4363  /* [0] [1] [2] [3] [4] [5]
4364  * 01 AA 00 12 34 56
4365  * LSB MSB
4366  */
4367  case 0:
4368  /* [47:36] i.e. 0x563 for above example address */
4369  hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
4370  break;
4371  case 1:
4372  /* [46:35] i.e. 0xAC6 for above example address */
4373  hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
4374  break;
4375  case 2:
4376  /* [45:34] i.e. 0x5D8 for above example address */
4377  hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
4378  break;
4379  case 3:
4380  /* [43:32] i.e. 0x634 for above example address */
4381  hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
4382  break;
4383  }
4384 
4385  hash_value &= 0xFFF;
4386  return hash_value;
4387 }
4388 
4395 void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
4396 {
4397  u32 rar_low, rar_high;
4398 
4399  /* HW expects these in little endian so we reverse the byte order
4400  * from network order (big endian) to little endian
4401  */
4402  rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
4403  ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
4404  rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
4405 
4406  /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
4407  * unit hang.
4408  *
4409  * Description:
4410  * If there are any Rx frames queued up or otherwise present in the HW
4411  * before RSS is enabled, and then we enable RSS, the HW Rx unit will
4412  * hang. To work around this issue, we have to disable receives and
4413  * flush out all Rx frames before we enable RSS. To do so, we modify we
4414  * redirect all Rx traffic to manageability and then reset the HW.
4415  * This flushes away Rx frames, and (since the redirections to
4416  * manageability persists across resets) keeps new ones from coming in
4417  * while we work. Then, we clear the Address Valid AV bit for all MAC
4418  * addresses and undo the re-direction to manageability.
4419  * Now, frames are coming in again, but the MAC won't accept them, so
4420  * far so good. We now proceed to initialize RSS (if necessary) and
4421  * configure the Rx unit. Last, we re-enable the AV bits and continue
4422  * on our merry way.
4423  */
4424  switch (hw->mac_type) {
4425  default:
4426  /* Indicate to hardware the Address is Valid. */
4427  rar_high |= E1000_RAH_AV;
4428  break;
4429  }
4430 
4431  E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4432  E1000_WRITE_FLUSH();
4433  E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4434  E1000_WRITE_FLUSH();
4435 }
4436 
4443 void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
4444 {
4445  u32 temp;
4446 
4447  if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4448  temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4449  E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4450  E1000_WRITE_FLUSH();
4451  E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4452  E1000_WRITE_FLUSH();
4453  } else {
4454  E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4455  E1000_WRITE_FLUSH();
4456  }
4457 }
4458 
4463 static void e1000_clear_vfta(struct e1000_hw *hw)
4464 {
4465  u32 offset;
4466  u32 vfta_value = 0;
4467  u32 vfta_offset = 0;
4468  u32 vfta_bit_in_reg = 0;
4469 
4470  for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4471  /* If the offset we want to clear is the same offset of the
4472  * manageability VLAN ID, then clear all bits except that of the
4473  * manageability unit */
4474  vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
4475  E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4476  E1000_WRITE_FLUSH();
4477  }
4478 }
4479 
4480 static s32 e1000_id_led_init(struct e1000_hw *hw)
4481 {
4482  u32 ledctl;
4483  const u32 ledctl_mask = 0x000000FF;
4484  const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4485  const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4486  u16 eeprom_data, i, temp;
4487  const u16 led_mask = 0x0F;
4488 
4489  e_dbg("e1000_id_led_init");
4490 
4491  if (hw->mac_type < e1000_82540) {
4492  /* Nothing to do */
4493  return E1000_SUCCESS;
4494  }
4495 
4496  ledctl = er32(LEDCTL);
4497  hw->ledctl_default = ledctl;
4498  hw->ledctl_mode1 = hw->ledctl_default;
4499  hw->ledctl_mode2 = hw->ledctl_default;
4500 
4501  if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4502  e_dbg("EEPROM Read Error\n");
4503  return -E1000_ERR_EEPROM;
4504  }
4505 
4506  if ((eeprom_data == ID_LED_RESERVED_0000) ||
4507  (eeprom_data == ID_LED_RESERVED_FFFF)) {
4508  eeprom_data = ID_LED_DEFAULT;
4509  }
4510 
4511  for (i = 0; i < 4; i++) {
4512  temp = (eeprom_data >> (i << 2)) & led_mask;
4513  switch (temp) {
4514  case ID_LED_ON1_DEF2:
4515  case ID_LED_ON1_ON2:
4516  case ID_LED_ON1_OFF2:
4517  hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4518  hw->ledctl_mode1 |= ledctl_on << (i << 3);
4519  break;
4520  case ID_LED_OFF1_DEF2:
4521  case ID_LED_OFF1_ON2:
4522  case ID_LED_OFF1_OFF2:
4523  hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4524  hw->ledctl_mode1 |= ledctl_off << (i << 3);
4525  break;
4526  default:
4527  /* Do nothing */
4528  break;
4529  }
4530  switch (temp) {
4531  case ID_LED_DEF1_ON2:
4532  case ID_LED_ON1_ON2:
4533  case ID_LED_OFF1_ON2:
4534  hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4535  hw->ledctl_mode2 |= ledctl_on << (i << 3);
4536  break;
4537  case ID_LED_DEF1_OFF2:
4538  case ID_LED_ON1_OFF2:
4539  case ID_LED_OFF1_OFF2:
4540  hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4541  hw->ledctl_mode2 |= ledctl_off << (i << 3);
4542  break;
4543  default:
4544  /* Do nothing */
4545  break;
4546  }
4547  }
4548  return E1000_SUCCESS;
4549 }
4550 
4557 s32 e1000_setup_led(struct e1000_hw *hw)
4558 {
4559  u32 ledctl;
4560  s32 ret_val = E1000_SUCCESS;
4561 
4562  e_dbg("e1000_setup_led");
4563 
4564  switch (hw->mac_type) {
4565  case e1000_82542_rev2_0:
4566  case e1000_82542_rev2_1:
4567  case e1000_82543:
4568  case e1000_82544:
4569  /* No setup necessary */
4570  break;
4571  case e1000_82541:
4572  case e1000_82547:
4573  case e1000_82541_rev_2:
4574  case e1000_82547_rev_2:
4575  /* Turn off PHY Smart Power Down (if enabled) */
4576  ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4577  &hw->phy_spd_default);
4578  if (ret_val)
4579  return ret_val;
4580  ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4581  (u16) (hw->phy_spd_default &
4582  ~IGP01E1000_GMII_SPD));
4583  if (ret_val)
4584  return ret_val;
4585  /* Fall Through */
4586  default:
4587  if (hw->media_type == e1000_media_type_fiber) {
4588  ledctl = er32(LEDCTL);
4589  /* Save current LEDCTL settings */
4590  hw->ledctl_default = ledctl;
4591  /* Turn off LED0 */
4592  ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4593  E1000_LEDCTL_LED0_BLINK |
4594  E1000_LEDCTL_LED0_MODE_MASK);
4595  ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4596  E1000_LEDCTL_LED0_MODE_SHIFT);
4597  ew32(LEDCTL, ledctl);
4598  } else if (hw->media_type == e1000_media_type_copper)
4599  ew32(LEDCTL, hw->ledctl_mode1);
4600  break;
4601  }
4602 
4603  return E1000_SUCCESS;
4604 }
4605 
4610 s32 e1000_cleanup_led(struct e1000_hw *hw)
4611 {
4612  s32 ret_val = E1000_SUCCESS;
4613 
4614  e_dbg("e1000_cleanup_led");
4615 
4616  switch (hw->mac_type) {
4617  case e1000_82542_rev2_0:
4618  case e1000_82542_rev2_1:
4619  case e1000_82543:
4620  case e1000_82544:
4621  /* No cleanup necessary */
4622  break;
4623  case e1000_82541:
4624  case e1000_82547:
4625  case e1000_82541_rev_2:
4626  case e1000_82547_rev_2:
4627  /* Turn on PHY Smart Power Down (if previously enabled) */
4628  ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4629  hw->phy_spd_default);
4630  if (ret_val)
4631  return ret_val;
4632  /* Fall Through */
4633  default:
4634  /* Restore LEDCTL settings */
4635  ew32(LEDCTL, hw->ledctl_default);
4636  break;
4637  }
4638 
4639  return E1000_SUCCESS;
4640 }
4641 
4646 s32 e1000_led_on(struct e1000_hw *hw)
4647 {
4648  u32 ctrl = er32(CTRL);
4649 
4650  e_dbg("e1000_led_on");
4651 
4652  switch (hw->mac_type) {
4653  case e1000_82542_rev2_0:
4654  case e1000_82542_rev2_1:
4655  case e1000_82543:
4656  /* Set SW Defineable Pin 0 to turn on the LED */
4657  ctrl |= E1000_CTRL_SWDPIN0;
4658  ctrl |= E1000_CTRL_SWDPIO0;
4659  break;
4660  case e1000_82544:
4661  if (hw->media_type == e1000_media_type_fiber) {
4662  /* Set SW Defineable Pin 0 to turn on the LED */
4663  ctrl |= E1000_CTRL_SWDPIN0;
4664  ctrl |= E1000_CTRL_SWDPIO0;
4665  } else {
4666  /* Clear SW Defineable Pin 0 to turn on the LED */
4667  ctrl &= ~E1000_CTRL_SWDPIN0;
4668  ctrl |= E1000_CTRL_SWDPIO0;
4669  }
4670  break;
4671  default:
4672  if (hw->media_type == e1000_media_type_fiber) {
4673  /* Clear SW Defineable Pin 0 to turn on the LED */
4674  ctrl &= ~E1000_CTRL_SWDPIN0;
4675  ctrl |= E1000_CTRL_SWDPIO0;
4676  } else if (hw->media_type == e1000_media_type_copper) {
4677  ew32(LEDCTL, hw->ledctl_mode2);
4678  return E1000_SUCCESS;
4679  }
4680  break;
4681  }
4682 
4683  ew32(CTRL, ctrl);
4684 
4685  return E1000_SUCCESS;
4686 }
4687 
4692 s32 e1000_led_off(struct e1000_hw *hw)
4693 {
4694  u32 ctrl = er32(CTRL);
4695 
4696  e_dbg("e1000_led_off");
4697 
4698  switch (hw->mac_type) {
4699  case e1000_82542_rev2_0:
4700  case e1000_82542_rev2_1:
4701  case e1000_82543:
4702  /* Clear SW Defineable Pin 0 to turn off the LED */
4703  ctrl &= ~E1000_CTRL_SWDPIN0;
4704  ctrl |= E1000_CTRL_SWDPIO0;
4705  break;
4706  case e1000_82544:
4707  if (hw->media_type == e1000_media_type_fiber) {
4708  /* Clear SW Defineable Pin 0 to turn off the LED */
4709  ctrl &= ~E1000_CTRL_SWDPIN0;
4710  ctrl |= E1000_CTRL_SWDPIO0;
4711  } else {
4712  /* Set SW Defineable Pin 0 to turn off the LED */
4713  ctrl |= E1000_CTRL_SWDPIN0;
4714  ctrl |= E1000_CTRL_SWDPIO0;
4715  }
4716  break;
4717  default:
4718  if (hw->media_type == e1000_media_type_fiber) {
4719  /* Set SW Defineable Pin 0 to turn off the LED */
4720  ctrl |= E1000_CTRL_SWDPIN0;
4721  ctrl |= E1000_CTRL_SWDPIO0;
4722  } else if (hw->media_type == e1000_media_type_copper) {
4723  ew32(LEDCTL, hw->ledctl_mode1);
4724  return E1000_SUCCESS;
4725  }
4726  break;
4727  }
4728 
4729  ew32(CTRL, ctrl);
4730 
4731  return E1000_SUCCESS;
4732 }
4733 
4738 static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
4739 {
4740  volatile u32 temp;
4741 
4742  temp = er32(CRCERRS);
4743  temp = er32(SYMERRS);
4744  temp = er32(MPC);
4745  temp = er32(SCC);
4746  temp = er32(ECOL);
4747  temp = er32(MCC);
4748  temp = er32(LATECOL);
4749  temp = er32(COLC);
4750  temp = er32(DC);
4751  temp = er32(SEC);
4752  temp = er32(RLEC);
4753  temp = er32(XONRXC);
4754  temp = er32(XONTXC);
4755  temp = er32(XOFFRXC);
4756  temp = er32(XOFFTXC);
4757  temp = er32(FCRUC);
4758 
4759  temp = er32(PRC64);
4760  temp = er32(PRC127);
4761  temp = er32(PRC255);
4762  temp = er32(PRC511);
4763  temp = er32(PRC1023);
4764  temp = er32(PRC1522);
4765 
4766  temp = er32(GPRC);
4767  temp = er32(BPRC);
4768  temp = er32(MPRC);
4769  temp = er32(GPTC);
4770  temp = er32(GORCL);
4771  temp = er32(GORCH);
4772  temp = er32(GOTCL);
4773  temp = er32(GOTCH);
4774  temp = er32(RNBC);
4775  temp = er32(RUC);
4776  temp = er32(RFC);
4777  temp = er32(ROC);
4778  temp = er32(RJC);
4779  temp = er32(TORL);
4780  temp = er32(TORH);
4781  temp = er32(TOTL);
4782  temp = er32(TOTH);
4783  temp = er32(TPR);
4784  temp = er32(TPT);
4785 
4786  temp = er32(PTC64);
4787  temp = er32(PTC127);
4788  temp = er32(PTC255);
4789  temp = er32(PTC511);
4790  temp = er32(PTC1023);
4791  temp = er32(PTC1522);
4792 
4793  temp = er32(MPTC);
4794  temp = er32(BPTC);
4795 
4796  if (hw->mac_type < e1000_82543)
4797  return;
4798 
4799  temp = er32(ALGNERRC);
4800  temp = er32(RXERRC);
4801  temp = er32(TNCRS);
4802  temp = er32(CEXTERR);
4803  temp = er32(TSCTC);
4804  temp = er32(TSCTFC);
4805 
4806  if (hw->mac_type <= e1000_82544)
4807  return;
4808 
4809  temp = er32(MGTPRC);
4810  temp = er32(MGTPDC);
4811  temp = er32(MGTPTC);
4812 }
4813 
4823 void e1000_reset_adaptive(struct e1000_hw *hw)
4824 {
4825  e_dbg("e1000_reset_adaptive");
4826 
4827  if (hw->adaptive_ifs) {
4828  if (!hw->ifs_params_forced) {
4829  hw->current_ifs_val = 0;
4830  hw->ifs_min_val = IFS_MIN;
4831  hw->ifs_max_val = IFS_MAX;
4832  hw->ifs_step_size = IFS_STEP;
4833  hw->ifs_ratio = IFS_RATIO;
4834  }
4835  hw->in_ifs_mode = false;
4836  ew32(AIT, 0);
4837  } else {
4838  e_dbg("Not in Adaptive IFS mode!\n");
4839  }
4840 }
4841 
4851 void e1000_update_adaptive(struct e1000_hw *hw)
4852 {
4853  e_dbg("e1000_update_adaptive");
4854 
4855  if (hw->adaptive_ifs) {
4856  if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) {
4857  if (hw->tx_packet_delta > MIN_NUM_XMITS) {
4858  hw->in_ifs_mode = true;
4859  if (hw->current_ifs_val < hw->ifs_max_val) {
4860  if (hw->current_ifs_val == 0)
4861  hw->current_ifs_val =
4862  hw->ifs_min_val;
4863  else
4864  hw->current_ifs_val +=
4865  hw->ifs_step_size;
4866  ew32(AIT, hw->current_ifs_val);
4867  }
4868  }
4869  } else {
4870  if (hw->in_ifs_mode
4871  && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4872  hw->current_ifs_val = 0;
4873  hw->in_ifs_mode = false;
4874  ew32(AIT, 0);
4875  }
4876  }
4877  } else {
4878  e_dbg("Not in Adaptive IFS mode!\n");
4879  }
4880 }
4881 
4890 void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
4891  u32 frame_len, u8 *mac_addr)
4892 {
4893  u64 carry_bit;
4894 
4895  /* First adjust the frame length. */
4896  frame_len--;
4897  /* We need to adjust the statistics counters, since the hardware
4898  * counters overcount this packet as a CRC error and undercount
4899  * the packet as a good packet
4900  */
4901  /* This packet should not be counted as a CRC error. */
4902  stats->crcerrs--;
4903  /* This packet does count as a Good Packet Received. */
4904  stats->gprc++;
4905 
4906  /* Adjust the Good Octets received counters */
4907  carry_bit = 0x80000000 & stats->gorcl;
4908  stats->gorcl += frame_len;
4909  /* If the high bit of Gorcl (the low 32 bits of the Good Octets
4910  * Received Count) was one before the addition,
4911  * AND it is zero after, then we lost the carry out,
4912  * need to add one to Gorch (Good Octets Received Count High).
4913  * This could be simplified if all environments supported
4914  * 64-bit integers.
4915  */
4916  if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
4917  stats->gorch++;
4918  /* Is this a broadcast or multicast? Check broadcast first,
4919  * since the test for a multicast frame will test positive on
4920  * a broadcast frame.
4921  */
4922  if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff))
4923  /* Broadcast packet */
4924  stats->bprc++;
4925  else if (*mac_addr & 0x01)
4926  /* Multicast packet */
4927  stats->mprc++;
4928 
4929  if (frame_len == hw->max_frame_size) {
4930  /* In this case, the hardware has overcounted the number of
4931  * oversize frames.
4932  */
4933  if (stats->roc > 0)
4934  stats->roc--;
4935  }
4936 
4937  /* Adjust the bin counters when the extra byte put the frame in the
4938  * wrong bin. Remember that the frame_len was adjusted above.
4939  */
4940  if (frame_len == 64) {
4941  stats->prc64++;
4942  stats->prc127--;
4943  } else if (frame_len == 127) {
4944  stats->prc127++;
4945  stats->prc255--;
4946  } else if (frame_len == 255) {
4947  stats->prc255++;
4948  stats->prc511--;
4949  } else if (frame_len == 511) {
4950  stats->prc511++;
4951  stats->prc1023--;
4952  } else if (frame_len == 1023) {
4953  stats->prc1023++;
4954  stats->prc1522--;
4955  } else if (frame_len == 1522) {
4956  stats->prc1522++;
4957  }
4958 }
4959 
4966 void e1000_get_bus_info(struct e1000_hw *hw)
4967 {
4968  u32 status;
4969 
4970  switch (hw->mac_type) {
4971  case e1000_82542_rev2_0:
4972  case e1000_82542_rev2_1:
4973  hw->bus_type = e1000_bus_type_pci;
4974  hw->bus_speed = e1000_bus_speed_unknown;
4975  hw->bus_width = e1000_bus_width_unknown;
4976  break;
4977  default:
4978  status = er32(STATUS);
4979  hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4980  e1000_bus_type_pcix : e1000_bus_type_pci;
4981 
4982  if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4983  hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
4984  e1000_bus_speed_66 : e1000_bus_speed_120;
4985  } else if (hw->bus_type == e1000_bus_type_pci) {
4986  hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4987  e1000_bus_speed_66 : e1000_bus_speed_33;
4988  } else {
4989  switch (status & E1000_STATUS_PCIX_SPEED) {
4990  case E1000_STATUS_PCIX_SPEED_66:
4991  hw->bus_speed = e1000_bus_speed_66;
4992  break;
4993  case E1000_STATUS_PCIX_SPEED_100:
4994  hw->bus_speed = e1000_bus_speed_100;
4995  break;
4996  case E1000_STATUS_PCIX_SPEED_133:
4997  hw->bus_speed = e1000_bus_speed_133;
4998  break;
4999  default:
5000  hw->bus_speed = e1000_bus_speed_reserved;
5001  break;
5002  }
5003  }
5004  hw->bus_width = (status & E1000_STATUS_BUS64) ?
5005  e1000_bus_width_64 : e1000_bus_width_32;
5006  break;
5007  }
5008 }
5009 
5019 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
5020 {
5021  unsigned long io_addr = hw->io_base;
5022  unsigned long io_data = hw->io_base + 4;
5023 
5024  e1000_io_write(hw, io_addr, offset);
5025  e1000_io_write(hw, io_data, value);
5026 }
5027 
5042 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
5043  u16 *max_length)
5044 {
5045  s32 ret_val;
5046  u16 agc_value = 0;
5047  u16 i, phy_data;
5048  u16 cable_length;
5049 
5050  e_dbg("e1000_get_cable_length");
5051 
5052  *min_length = *max_length = 0;
5053 
5054  /* Use old method for Phy older than IGP */
5055  if (hw->phy_type == e1000_phy_m88) {
5056 
5057  ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5058  &phy_data);
5059  if (ret_val)
5060  return ret_val;
5061  cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
5062  M88E1000_PSSR_CABLE_LENGTH_SHIFT;
5063 
5064  /* Convert the enum value to ranged values */
5065  switch (cable_length) {
5066  case e1000_cable_length_50:
5067  *min_length = 0;
5068  *max_length = e1000_igp_cable_length_50;
5069  break;
5070  case e1000_cable_length_50_80:
5071  *min_length = e1000_igp_cable_length_50;
5072  *max_length = e1000_igp_cable_length_80;
5073  break;
5074  case e1000_cable_length_80_110:
5075  *min_length = e1000_igp_cable_length_80;
5076  *max_length = e1000_igp_cable_length_110;
5077  break;
5078  case e1000_cable_length_110_140:
5079  *min_length = e1000_igp_cable_length_110;
5080  *max_length = e1000_igp_cable_length_140;
5081  break;
5082  case e1000_cable_length_140:
5083  *min_length = e1000_igp_cable_length_140;
5084  *max_length = e1000_igp_cable_length_170;
5085  break;
5086  default:
5087  return -E1000_ERR_PHY;
5088  break;
5089  }
5090  } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
5091  u16 cur_agc_value;
5092  u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
5093  static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
5094  IGP01E1000_PHY_AGC_A,
5095  IGP01E1000_PHY_AGC_B,
5096  IGP01E1000_PHY_AGC_C,
5097  IGP01E1000_PHY_AGC_D
5098  };
5099  /* Read the AGC registers for all channels */
5100  for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5101 
5102  ret_val =
5103  e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
5104  if (ret_val)
5105  return ret_val;
5106 
5107  cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
5108 
5109  /* Value bound check. */
5110  if ((cur_agc_value >=
5111  IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1)
5112  || (cur_agc_value == 0))
5113  return -E1000_ERR_PHY;
5114 
5115  agc_value += cur_agc_value;
5116 
5117  /* Update minimal AGC value. */
5118  if (min_agc_value > cur_agc_value)
5119  min_agc_value = cur_agc_value;
5120  }
5121 
5122  /* Remove the minimal AGC result for length < 50m */
5123  if (agc_value <
5124  IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
5125  agc_value -= min_agc_value;
5126 
5127  /* Get the average length of the remaining 3 channels */
5128  agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
5129  } else {
5130  /* Get the average length of all the 4 channels. */
5131  agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
5132  }
5133 
5134  /* Set the range of the calculated length. */
5135  *min_length = ((e1000_igp_cable_length_table[agc_value] -
5136  IGP01E1000_AGC_RANGE) > 0) ?
5137  (e1000_igp_cable_length_table[agc_value] -
5138  IGP01E1000_AGC_RANGE) : 0;
5139  *max_length = e1000_igp_cable_length_table[agc_value] +
5140  IGP01E1000_AGC_RANGE;
5141  }
5142 
5143  return E1000_SUCCESS;
5144 }
5145 
5161 static s32 e1000_check_polarity(struct e1000_hw *hw,
5162  e1000_rev_polarity *polarity)
5163 {
5164  s32 ret_val;
5165  u16 phy_data;
5166 
5167  e_dbg("e1000_check_polarity");
5168 
5169  if (hw->phy_type == e1000_phy_m88) {
5170  /* return the Polarity bit in the Status register. */
5171  ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5172  &phy_data);
5173  if (ret_val)
5174  return ret_val;
5175  *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
5176  M88E1000_PSSR_REV_POLARITY_SHIFT) ?
5177  e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
5178 
5179  } else if (hw->phy_type == e1000_phy_igp) {
5180  /* Read the Status register to check the speed */
5181  ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
5182  &phy_data);
5183  if (ret_val)
5184  return ret_val;
5185 
5186  /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
5187  * find the polarity status */
5188  if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
5189  IGP01E1000_PSSR_SPEED_1000MBPS) {
5190 
5191  /* Read the GIG initialization PCS register (0x00B4) */
5192  ret_val =
5193  e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
5194  &phy_data);
5195  if (ret_val)
5196  return ret_val;
5197 
5198  /* Check the polarity bits */
5199  *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
5200  e1000_rev_polarity_reversed :
5201  e1000_rev_polarity_normal;
5202  } else {
5203  /* For 10 Mbps, read the polarity bit in the status register. (for
5204  * 100 Mbps this bit is always 0) */
5205  *polarity =
5206  (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
5207  e1000_rev_polarity_reversed :
5208  e1000_rev_polarity_normal;
5209  }
5210  }
5211  return E1000_SUCCESS;
5212 }
5213 
5228 static s32 e1000_check_downshift(struct e1000_hw *hw)
5229 {
5230  s32 ret_val;
5231  u16 phy_data;
5232 
5233  e_dbg("e1000_check_downshift");
5234 
5235  if (hw->phy_type == e1000_phy_igp) {
5236  ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
5237  &phy_data);
5238  if (ret_val)
5239  return ret_val;
5240 
5241  hw->speed_downgraded =
5242  (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
5243  } else if (hw->phy_type == e1000_phy_m88) {
5244  ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5245  &phy_data);
5246  if (ret_val)
5247  return ret_val;
5248 
5249  hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
5250  M88E1000_PSSR_DOWNSHIFT_SHIFT;
5251  }
5252 
5253  return E1000_SUCCESS;
5254 }
5255 
5256 static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
5257  IGP01E1000_PHY_AGC_PARAM_A,
5258  IGP01E1000_PHY_AGC_PARAM_B,
5259  IGP01E1000_PHY_AGC_PARAM_C,
5260  IGP01E1000_PHY_AGC_PARAM_D
5261 };
5262 
5263 static s32 e1000_1000Mb_check_cable_length(struct e1000_hw *hw)
5264 {
5265  u16 min_length, max_length;
5266  u16 phy_data, i;
5267  s32 ret_val;
5268 
5269  ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
5270  if (ret_val)
5271  return ret_val;
5272 
5273  if (hw->dsp_config_state != e1000_dsp_config_enabled)
5274  return 0;
5275 
5276  if (min_length >= e1000_igp_cable_length_50) {
5277  for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5278  ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
5279  &phy_data);
5280  if (ret_val)
5281  return ret_val;
5282 
5283  phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5284 
5285  ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
5286  phy_data);
5287  if (ret_val)
5288  return ret_val;
5289  }
5290  hw->dsp_config_state = e1000_dsp_config_activated;
5291  } else {
5292  u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5293  u32 idle_errs = 0;
5294 
5295  /* clear previous idle error counts */
5296  ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
5297  if (ret_val)
5298  return ret_val;
5299 
5300  for (i = 0; i < ffe_idle_err_timeout; i++) {
5301  udelay(1000);
5302  ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5303  &phy_data);
5304  if (ret_val)
5305  return ret_val;
5306 
5307  idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
5308  if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
5309  hw->ffe_config_state = e1000_ffe_config_active;
5310 
5311  ret_val = e1000_write_phy_reg(hw,
5312  IGP01E1000_PHY_DSP_FFE,
5313  IGP01E1000_PHY_DSP_FFE_CM_CP);
5314  if (ret_val)
5315  return ret_val;
5316  break;
5317  }
5318 
5319  if (idle_errs)
5320  ffe_idle_err_timeout =
5321  FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5322  }
5323  }
5324 
5325  return 0;
5326 }
5327 
5340 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
5341 {
5342  s32 ret_val;
5343  u16 phy_data, phy_saved_data, speed, duplex, i;
5344 
5345  e_dbg("e1000_config_dsp_after_link_change");
5346 
5347  if (hw->phy_type != e1000_phy_igp)
5348  return E1000_SUCCESS;
5349 
5350  if (link_up) {
5351  ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
5352  if (ret_val) {
5353  e_dbg("Error getting link speed and duplex\n");
5354  return ret_val;
5355  }
5356 
5357  if (speed == SPEED_1000) {
5358  ret_val = e1000_1000Mb_check_cable_length(hw);
5359  if (ret_val)
5360  return ret_val;
5361  }
5362  } else {
5363  if (hw->dsp_config_state == e1000_dsp_config_activated) {
5364  /* Save off the current value of register 0x2F5B to be restored at
5365  * the end of the routines. */
5366  ret_val =
5367  e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5368 
5369  if (ret_val)
5370  return ret_val;
5371 
5372  /* Disable the PHY transmitter */
5373  ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5374 
5375  if (ret_val)
5376  return ret_val;
5377 
5378  msleep(20);
5379 
5380  ret_val = e1000_write_phy_reg(hw, 0x0000,
5381  IGP01E1000_IEEE_FORCE_GIGA);
5382  if (ret_val)
5383  return ret_val;
5384  for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5385  ret_val =
5386  e1000_read_phy_reg(hw, dsp_reg_array[i],
5387  &phy_data);
5388  if (ret_val)
5389  return ret_val;
5390 
5391  phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5392  phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5393 
5394  ret_val =
5395  e1000_write_phy_reg(hw, dsp_reg_array[i],
5396  phy_data);
5397  if (ret_val)
5398  return ret_val;
5399  }
5400 
5401  ret_val = e1000_write_phy_reg(hw, 0x0000,
5402  IGP01E1000_IEEE_RESTART_AUTONEG);
5403  if (ret_val)
5404  return ret_val;
5405 
5406  msleep(20);
5407 
5408  /* Now enable the transmitter */
5409  ret_val =
5410  e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5411 
5412  if (ret_val)
5413  return ret_val;
5414 
5415  hw->dsp_config_state = e1000_dsp_config_enabled;
5416  }
5417 
5418  if (hw->ffe_config_state == e1000_ffe_config_active) {
5419  /* Save off the current value of register 0x2F5B to be restored at
5420  * the end of the routines. */
5421  ret_val =
5422  e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5423 
5424  if (ret_val)
5425  return ret_val;
5426 
5427  /* Disable the PHY transmitter */
5428  ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5429 
5430  if (ret_val)
5431  return ret_val;
5432 
5433  msleep(20);
5434 
5435  ret_val = e1000_write_phy_reg(hw, 0x0000,
5436  IGP01E1000_IEEE_FORCE_GIGA);
5437  if (ret_val)
5438  return ret_val;
5439  ret_val =
5440  e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5441  IGP01E1000_PHY_DSP_FFE_DEFAULT);
5442  if (ret_val)
5443  return ret_val;
5444 
5445  ret_val = e1000_write_phy_reg(hw, 0x0000,
5446  IGP01E1000_IEEE_RESTART_AUTONEG);
5447  if (ret_val)
5448  return ret_val;
5449 
5450  msleep(20);
5451 
5452  /* Now enable the transmitter */
5453  ret_val =
5454  e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5455 
5456  if (ret_val)
5457  return ret_val;
5458 
5459  hw->ffe_config_state = e1000_ffe_config_enabled;
5460  }
5461  }
5462  return E1000_SUCCESS;
5463 }
5464 
5473 static s32 e1000_set_phy_mode(struct e1000_hw *hw)
5474 {
5475  s32 ret_val;
5476  u16 eeprom_data;
5477 
5478  e_dbg("e1000_set_phy_mode");
5479 
5480  if ((hw->mac_type == e1000_82545_rev_3) &&
5481  (hw->media_type == e1000_media_type_copper)) {
5482  ret_val =
5483  e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
5484  &eeprom_data);
5485  if (ret_val) {
5486  return ret_val;
5487  }
5488 
5489  if ((eeprom_data != EEPROM_RESERVED_WORD) &&
5490  (eeprom_data & EEPROM_PHY_CLASS_A)) {
5491  ret_val =
5492  e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
5493  0x000B);
5494  if (ret_val)
5495  return ret_val;
5496  ret_val =
5497  e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
5498  0x8104);
5499  if (ret_val)
5500  return ret_val;
5501 
5502  hw->phy_reset_disable = false;
5503  }
5504  }
5505 
5506  return E1000_SUCCESS;
5507 }
5508 
5522 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
5523 {
5524  s32 ret_val;
5525  u16 phy_data;
5526  e_dbg("e1000_set_d3_lplu_state");
5527 
5528  if (hw->phy_type != e1000_phy_igp)
5529  return E1000_SUCCESS;
5530 
5531  /* During driver activity LPLU should not be used or it will attain link
5532  * from the lowest speeds starting from 10Mbps. The capability is used for
5533  * Dx transitions and states */
5534  if (hw->mac_type == e1000_82541_rev_2
5535  || hw->mac_type == e1000_82547_rev_2) {
5536  ret_val =
5537  e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5538  if (ret_val)
5539  return ret_val;
5540  }
5541 
5542  if (!active) {
5543  if (hw->mac_type == e1000_82541_rev_2 ||
5544  hw->mac_type == e1000_82547_rev_2) {
5545  phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5546  ret_val =
5547  e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5548  phy_data);
5549  if (ret_val)
5550  return ret_val;
5551  }
5552 
5553  /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5554  * Dx states where the power conservation is most important. During
5555  * driver activity we should enable SmartSpeed, so performance is
5556  * maintained. */
5557  if (hw->smart_speed == e1000_smart_speed_on) {
5558  ret_val =
5559  e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5560  &phy_data);
5561  if (ret_val)
5562  return ret_val;
5563 
5564  phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5565  ret_val =
5566  e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5567  phy_data);
5568  if (ret_val)
5569  return ret_val;
5570  } else if (hw->smart_speed == e1000_smart_speed_off) {
5571  ret_val =
5572  e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5573  &phy_data);
5574  if (ret_val)
5575  return ret_val;
5576 
5577  phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5578  ret_val =
5579  e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5580  phy_data);
5581  if (ret_val)
5582  return ret_val;
5583  }
5584  } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
5585  || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL)
5586  || (hw->autoneg_advertised ==
5587  AUTONEG_ADVERTISE_10_100_ALL)) {
5588 
5589  if (hw->mac_type == e1000_82541_rev_2 ||
5590  hw->mac_type == e1000_82547_rev_2) {
5591  phy_data |= IGP01E1000_GMII_FLEX_SPD;
5592  ret_val =
5593  e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5594  phy_data);
5595  if (ret_val)
5596  return ret_val;
5597  }
5598 
5599  /* When LPLU is enabled we should disable SmartSpeed */
5600  ret_val =
5601  e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5602  &phy_data);
5603  if (ret_val)
5604  return ret_val;
5605 
5606  phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5607  ret_val =
5608  e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5609  phy_data);
5610  if (ret_val)
5611  return ret_val;
5612 
5613  }
5614  return E1000_SUCCESS;
5615 }
5616 
5623 static s32 e1000_set_vco_speed(struct e1000_hw *hw)
5624 {
5625  s32 ret_val;
5626  u16 default_page = 0;
5627  u16 phy_data;
5628 
5629  e_dbg("e1000_set_vco_speed");
5630 
5631  switch (hw->mac_type) {
5632  case e1000_82545_rev_3:
5633  case e1000_82546_rev_3:
5634  break;
5635  default:
5636  return E1000_SUCCESS;
5637  }
5638 
5639  /* Set PHY register 30, page 5, bit 8 to 0 */
5640 
5641  ret_val =
5642  e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
5643  if (ret_val)
5644  return ret_val;
5645 
5646  ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
5647  if (ret_val)
5648  return ret_val;
5649 
5650  ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5651  if (ret_val)
5652  return ret_val;
5653 
5654  phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5655  ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5656  if (ret_val)
5657  return ret_val;
5658 
5659  /* Set PHY register 30, page 4, bit 11 to 1 */
5660 
5661  ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5662  if (ret_val)
5663  return ret_val;
5664 
5665  ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5666  if (ret_val)
5667  return ret_val;
5668 
5669  phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5670  ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5671  if (ret_val)
5672  return ret_val;
5673 
5674  ret_val =
5675  e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5676  if (ret_val)
5677  return ret_val;
5678 
5679  return E1000_SUCCESS;
5680 }
5681 
5682 
5690 u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
5691 {
5692  u32 manc;
5693 
5694  if (hw->asf_firmware_present) {
5695  manc = er32(MANC);
5696 
5697  if (!(manc & E1000_MANC_RCV_TCO_EN) ||
5698  !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
5699  return false;
5700  if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
5701  return true;
5702  }
5703  return false;
5704 }
5705 
5706 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5707 {
5708  s32 ret_val;
5709  u16 mii_status_reg;
5710  u16 i;
5711 
5712  /* Polarity reversal workaround for forced 10F/10H links. */
5713 
5714  /* Disable the transmitter on the PHY */
5715 
5716  ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5717  if (ret_val)
5718  return ret_val;
5719  ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
5720  if (ret_val)
5721  return ret_val;
5722 
5723  ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5724  if (ret_val)
5725  return ret_val;
5726 
5727  /* This loop will early-out if the NO link condition has been met. */
5728  for (i = PHY_FORCE_TIME; i > 0; i--) {
5729  /* Read the MII Status Register and wait for Link Status bit
5730  * to be clear.
5731  */
5732 
5733  ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5734  if (ret_val)
5735  return ret_val;
5736 
5737  ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5738  if (ret_val)
5739  return ret_val;
5740 
5741  if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
5742  break;
5743  msleep(100);
5744  }
5745 
5746  /* Recommended delay time after link has been lost */
5747  msleep(1000);
5748 
5749  /* Now we will re-enable th transmitter on the PHY */
5750 
5751  ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5752  if (ret_val)
5753  return ret_val;
5754  msleep(50);
5755  ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
5756  if (ret_val)
5757  return ret_val;
5758  msleep(50);
5759  ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
5760  if (ret_val)
5761  return ret_val;
5762  msleep(50);
5763  ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
5764  if (ret_val)
5765  return ret_val;
5766 
5767  ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5768  if (ret_val)
5769  return ret_val;
5770 
5771  /* This loop will early-out if the link condition has been met. */
5772  for (i = PHY_FORCE_TIME; i > 0; i--) {
5773  /* Read the MII Status Register and wait for Link Status bit
5774  * to be set.
5775  */
5776 
5777  ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5778  if (ret_val)
5779  return ret_val;
5780 
5781  ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5782  if (ret_val)
5783  return ret_val;
5784 
5785  if (mii_status_reg & MII_SR_LINK_STATUS)
5786  break;
5787  msleep(100);
5788  }
5789  return E1000_SUCCESS;
5790 }
5791 
5800 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
5801 {
5802  e_dbg("e1000_get_auto_rd_done");
5803  msleep(5);
5804  return E1000_SUCCESS;
5805 }
5806 
5815 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
5816 {
5817  e_dbg("e1000_get_phy_cfg_done");
5818  msleep(10);
5819  return E1000_SUCCESS;
5820 }
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