llvm::AArch64InstrInfo Class Reference

#include <AArch64InstrInfo.h>

Inheritance diagram for llvm::AArch64InstrInfo:

Collaboration diagram for llvm::AArch64InstrInfo:

List of all members.

Public Member Functions
	AArch64InstrInfo (const AArch64Subtarget &STI)
const AArch64RegisterInfo &	getRegisterInfo () const
unsigned	GetInstSizeInBytes (const MachineInstr *MI) const
bool	isAsCheapAsAMove (const MachineInstr *MI) const override
bool	isCoalescableExtInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
bool	areMemAccessesTriviallyDisjoint (MachineInstr *MIa, MachineInstr *MIb, AliasAnalysis *AA=nullptr) const override
unsigned	isLoadFromStackSlot (const MachineInstr *MI, int &FrameIndex) const override
unsigned	isStoreToStackSlot (const MachineInstr *MI, int &FrameIndex) const override
bool	hasShiftedReg (const MachineInstr *MI) const
	Return true if this is this instruction has a non-zero immediate.
bool	hasExtendedReg (const MachineInstr *MI) const
	Return true if this is this instruction has a non-zero immediate.
bool	isGPRZero (const MachineInstr *MI) const
	Does this instruction set its full destination register to zero?
bool	isGPRCopy (const MachineInstr *MI) const
	Does this instruction rename a GPR without modifying bits?
bool	isFPRCopy (const MachineInstr *MI) const
	Does this instruction rename an FPR without modifying bits?
bool	isScaledAddr (const MachineInstr *MI) const
bool	isLdStPairSuppressed (const MachineInstr *MI) const
	Check all MachineMemOperands for a hint to suppress pairing.
void	suppressLdStPair (MachineInstr *MI) const
	Hint that pairing the given load or store is unprofitable.
bool	getLdStBaseRegImmOfs (MachineInstr *LdSt, unsigned &BaseReg, unsigned &Offset, const TargetRegisterInfo *TRI) const override
bool	getLdStBaseRegImmOfsWidth (MachineInstr *LdSt, unsigned &BaseReg, int &Offset, int &Width, const TargetRegisterInfo *TRI) const
bool	enableClusterLoads () const override
bool	shouldClusterLoads (MachineInstr *FirstLdSt, MachineInstr *SecondLdSt, unsigned NumLoads) const override
bool	shouldScheduleAdjacent (MachineInstr *First, MachineInstr *Second) const override
MachineInstr *	emitFrameIndexDebugValue (MachineFunction &MF, int FrameIx, uint64_t Offset, const MDNode *MDPtr, DebugLoc DL) const
void	copyPhysRegTuple (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const override
bool	AnalyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
unsigned	RemoveBranch (MachineBasicBlock &MBB) const override
unsigned	InsertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl< MachineOperand > &Cond, DebugLoc DL) const override
bool	ReverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
bool	canInsertSelect (const MachineBasicBlock &, const SmallVectorImpl< MachineOperand > &Cond, unsigned, unsigned, int &, int &, int &) const override
void	insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DstReg, const SmallVectorImpl< MachineOperand > &Cond, unsigned TrueReg, unsigned FalseReg) const override
void	getNoopForMachoTarget (MCInst &NopInst) const override
bool	analyzeCompare (const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
bool	optimizeCompareInstr (MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
bool	hasPattern (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern::MC_PATTERN > &Pattern) const override
void	genAlternativeCodeSequence (MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
bool	useMachineCombiner () const override
	useMachineCombiner - AArch64 supports MachineCombiner
bool	expandPostRAPseudo (MachineBasicBlock::iterator MI) const override

---

Detailed Description

Definition at line 30 of file AArch64InstrInfo.h.

---

Constructor & Destructor Documentation

AArch64InstrInfo::AArch64InstrInfo

(

const AArch64Subtarget &

STI

)

[explicit]

Definition at line 32 of file AArch64InstrInfo.cpp.

---

Member Function Documentation

bool AArch64InstrInfo::AnalyzeBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock *&	TBB,
		MachineBasicBlock *&	FBB,
		SmallVectorImpl< MachineOperand > &	Cond,
		bool	AllowModify = false
	)		const [override]

Definition at line 93 of file AArch64InstrInfo.cpp.

References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::isCondBranchOpcode(), llvm::isIndirectBranchOpcode(), llvm::isUncondBranchOpcode(), and parseCondBranch().

bool AArch64InstrInfo::analyzeCompare	(	const MachineInstr *	MI,
		unsigned &	SrcReg,
		unsigned &	SrcReg2,
		int &	CmpMask,
		int &	CmpValue
	)		const [override]

analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2, and the value it compares against in CmpValue. Return true if the comparison instruction can be analyzed.

Definition at line 649 of file AArch64InstrInfo.cpp.

References llvm::AArch64_AM::decodeLogicalImmediate(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

bool AArch64InstrInfo::areMemAccessesTriviallyDisjoint	(	MachineInstr *	MIa,
		MachineInstr *	MIb,
		AliasAnalysis *	AA = nullptr
	)		const [override]

Definition at line 611 of file AArch64InstrInfo.cpp.

References getLdStBaseRegImmOfsWidth(), getRegisterInfo(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineInstr::mayLoad(), and llvm::MachineInstr::mayStore().

bool AArch64InstrInfo::canInsertSelect	(	const MachineBasicBlock &	MBB,
		const SmallVectorImpl< MachineOperand > &	Cond,
		unsigned	TrueReg,
		unsigned	FalseReg,
		int &	CondCycles,
		int &	TrueCycles,
		int &	FalseCycles
	)		const [override]

Definition at line 370 of file AArch64InstrInfo.cpp.

References canFoldIntoCSel(), llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), and llvm::SmallVectorTemplateCommon< T >::size().

void AArch64InstrInfo::copyPhysReg	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		DebugLoc	DL,
		unsigned	DestReg,
		unsigned	SrcReg,
		bool	KillSrc
	)		const [override]

Definition at line 1505 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), contains(), copyPhysRegTuple(), llvm::RegState::Define, llvm::getKillRegState(), llvm::TargetRegisterInfo::getMatchingSuperReg(), getRegisterInfo(), llvm::AArch64_AM::getShifterImm(), llvm::AArch64Subtarget::hasNEON(), llvm::AArch64Subtarget::hasZeroCycleRegMove(), llvm::AArch64Subtarget::hasZeroCycleZeroing(), llvm::RegState::Implicit, llvm_unreachable, llvm::AArch64_AM::LSL, llvm::AArch64SysReg::NZCV, and llvm::RegState::Undef.

void AArch64InstrInfo::copyPhysRegTuple	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		DebugLoc	DL,
		unsigned	DestReg,
		unsigned	SrcReg,
		bool	KillSrc,
		unsigned	Opcode,
		llvm::ArrayRef< unsigned >	Indices
	)		const

Definition at line 1479 of file AArch64InstrInfo.cpp.

References AddSubReg(), llvm::BuildMI(), llvm::RegState::Define, forwardCopyWillClobberTuple(), llvm::getKillRegState(), getRegisterInfo(), llvm::AArch64Subtarget::hasNEON(), and llvm::ArrayRef< T >::size().

Referenced by copyPhysReg().

MachineInstr * AArch64InstrInfo::emitFrameIndexDebugValue	(	MachineFunction &	MF,
		int	FrameIx,
		uint64_t	Offset,
		const MDNode *	MDPtr,
		DebugLoc	DL
	)		const

Definition at line 1447 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMetadata(), llvm::BuildMI(), and llvm::TargetOpcode::DBG_VALUE.

bool llvm::AArch64InstrInfo::enableClusterLoads

(

)

const [inline, override]

Definition at line 101 of file AArch64InstrInfo.h.

bool AArch64InstrInfo::expandPostRAPseudo

(

MachineBasicBlock::iterator

MI

)

const [override]

Definition at line 953 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::AArch64ISD::ADRP, llvm::BuildMI(), llvm::AArch64Subtarget::ClassifyGlobalReference(), llvm::MachineBasicBlock::erase(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getTarget(), llvm::RegState::Kill, llvm::CodeModel::Large, llvm::TargetOpcode::LOAD_STACK_GUARD, llvm::AArch64ISD::LOADgot, llvm::AArch64II::MO_G0, llvm::AArch64II::MO_G1, llvm::AArch64II::MO_G2, llvm::AArch64II::MO_G3, llvm::AArch64II::MO_GOT, llvm::AArch64II::MO_NC, llvm::AArch64II::MO_PAGE, llvm::AArch64II::MO_PAGEOFF, and llvm::SystemZISD::TM.

MachineInstr * AArch64InstrInfo::foldMemoryOperandImpl	(	MachineFunction &	MF,
		MachineInstr *	MI,
		const SmallVectorImpl< unsigned > &	Ops,
		int	FrameIndex
	)		const [override]

Definition at line 2041 of file AArch64InstrInfo.cpp.

References llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineInstr::isCopy(), and llvm::TargetRegisterInfo::isVirtualRegister().

void AArch64InstrInfo::genAlternativeCodeSequence	(	MachineInstr &	Root,
		MachineCombinerPattern::MC_PATTERN	Pattern,
		SmallVectorImpl< MachineInstr * > &	InsInstrs,
		SmallVectorImpl< MachineInstr * > &	DelInstrs,
		DenseMap< unsigned, unsigned > &	InstrIdxForVirtReg
	)		const [override]

genAlternativeCodeSequence - when hasPattern() finds a pattern this function generates the instructions that could replace the original code sequence

Definition at line 2645 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addOperand(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), genMadd(), genMaddR(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT >::insert(), llvm::MachineOperand::isImm(), llvm::MachineCombinerPattern::MC_MULADDW_OP1, llvm::MachineCombinerPattern::MC_MULADDW_OP2, llvm::MachineCombinerPattern::MC_MULADDWI_OP1, llvm::MachineCombinerPattern::MC_MULADDX_OP1, llvm::MachineCombinerPattern::MC_MULADDX_OP2, llvm::MachineCombinerPattern::MC_MULADDXI_OP1, llvm::MachineCombinerPattern::MC_MULSUBW_OP1, llvm::MachineCombinerPattern::MC_MULSUBW_OP2, llvm::MachineCombinerPattern::MC_MULSUBWI_OP1, llvm::MachineCombinerPattern::MC_MULSUBX_OP1, llvm::MachineCombinerPattern::MC_MULSUBX_OP2, llvm::MachineCombinerPattern::MC_MULSUBXI_OP1, llvm::ISD::MUL, llvm::AArch64_AM::processLogicalImmediate(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), and TII.

unsigned AArch64InstrInfo::GetInstSizeInBytes

(

const MachineInstr *

MI

)

const

GetInstSize - Return the number of bytes of code the specified instruction may be. This returns the maximum number of bytes.

Definition at line 38 of file AArch64InstrInfo.cpp.

References llvm::TargetOpcode::DBG_VALUE, llvm::TargetOpcode::EH_LABEL, llvm::MachineInstr::getDesc(), llvm::TargetMachine::getMCAsmInfo(), llvm::MCInstrDesc::getOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getSymbolName(), llvm::MachineFunction::getTarget(), llvm::TargetOpcode::IMPLICIT_DEF, llvm::ISD::INLINEASM, llvm::TargetOpcode::KILL, and llvm_unreachable.

bool AArch64InstrInfo::getLdStBaseRegImmOfs	(	MachineInstr *	LdSt,
		unsigned &	BaseReg,
		unsigned &	Offset,
		const TargetRegisterInfo *	TRI
	)		const [override]

Definition at line 1283 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().

bool AArch64InstrInfo::getLdStBaseRegImmOfsWidth	(	MachineInstr *	LdSt,
		unsigned &	BaseReg,
		int &	Offset,
		int &	Width,
		const TargetRegisterInfo *	TRI
	)		const

Definition at line 1309 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().

Referenced by areMemAccessesTriviallyDisjoint().

void AArch64InstrInfo::getNoopForMachoTarget

(

MCInst &

NopInst

)

const [override]

Definition at line 2336 of file AArch64InstrInfo.cpp.

References llvm::MCInst::addOperand(), llvm::MCOperand::CreateImm(), and llvm::MCInst::setOpcode().

const AArch64RegisterInfo& llvm::AArch64InstrInfo::getRegisterInfo

(

)

const [inline]

getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 46 of file AArch64InstrInfo.h.

Referenced by areMemAccessesTriviallyDisjoint(), copyPhysReg(), copyPhysRegTuple(), llvm::AArch64Subtarget::getRegisterInfo(), and optimizeCompareInstr().

bool AArch64InstrInfo::hasExtendedReg

(

const MachineInstr *

MI

)

const

Return true if this is this instruction has a non-zero immediate.

Returns true if there is an extendable register and that the extending value is non-zero.

Definition at line 1049 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::isImm().

bool AArch64InstrInfo::hasPattern	(	MachineInstr &	Root,
		SmallVectorImpl< MachineCombinerPattern::MC_PATTERN > &	Pattern
	)		const [override]

hasPattern - return true when there is potentially a faster code sequence for an instruction chain ending in <Root>. All potential patterns are listed in the <Pattern> array.

hasPattern - return true when there is potentially a faster code sequence for an instruction chain ending in Root. All potential patterns are listed in the Pattern vector. Pattern should be sorted in priority order since the pattern evaluator stops checking as soon as it finds a faster sequence.

Definition at line 2440 of file AArch64InstrInfo.cpp.

References canCombineWithMUL(), convertFlagSettingOpcode(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), isCombineInstrCandidate(), isCombineInstrSettingFlag(), llvm::MachineOperand::isReg(), llvm::MachineCombinerPattern::MC_MULADDW_OP1, llvm::MachineCombinerPattern::MC_MULADDW_OP2, llvm::MachineCombinerPattern::MC_MULADDWI_OP1, llvm::MachineCombinerPattern::MC_MULADDX_OP1, llvm::MachineCombinerPattern::MC_MULADDX_OP2, llvm::MachineCombinerPattern::MC_MULADDXI_OP1, llvm::MachineCombinerPattern::MC_MULSUBW_OP1, llvm::MachineCombinerPattern::MC_MULSUBW_OP2, llvm::MachineCombinerPattern::MC_MULSUBWI_OP1, llvm::MachineCombinerPattern::MC_MULSUBX_OP1, llvm::MachineCombinerPattern::MC_MULSUBX_OP2, llvm::MachineCombinerPattern::MC_MULSUBXI_OP1, llvm::AArch64SysReg::NZCV, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

bool AArch64InstrInfo::hasShiftedReg

(

const MachineInstr *

MI

)

const

Return true if this is this instruction has a non-zero immediate.

Returns true if there is a shiftable register and that the shift value is non-zero.

Definition at line 1003 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::isImm().

unsigned AArch64InstrInfo::InsertBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock *	TBB,
		MachineBasicBlock *	FBB,
		const SmallVectorImpl< MachineOperand > &	Cond,
		DebugLoc	DL
	)		const [override]

Definition at line 272 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::BuildMI(), and llvm::SmallVectorBase::empty().

void AArch64InstrInfo::insertSelect	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		DebugLoc	DL,
		unsigned	DstReg,
		const SmallVectorImpl< MachineOperand > &	Cond,
		unsigned	TrueReg,
		unsigned	FalseReg
	)		const [override]

Definition at line 411 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), canFoldIntoCSel(), llvm::MachineRegisterInfo::clearKillFlags(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::AArch64_AM::encodeLogicalImmediate(), EQ, llvm::AArch64CC::getInvertedCondCode(), llvm::MachineBasicBlock::getParent(), getReg(), llvm::MachineFunction::getRegInfo(), llvm_unreachable, llvm::AArch64CC::NE, and llvm::SmallVectorTemplateCommon< T >::size().

bool AArch64InstrInfo::isAsCheapAsAMove

(

const MachineInstr *

MI

)

const [override]

Definition at line 547 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::isAsCheapAsAMove(), llvm::AArch64Subtarget::isCortexA53(), llvm::AArch64Subtarget::isCortexA57(), and llvm_unreachable.

bool AArch64InstrInfo::isCoalescableExtInstr	(	const MachineInstr &	MI,
		unsigned &	SrcReg,
		unsigned &	DstReg,
		unsigned &	SubIdx
	)		const [override]

Definition at line 590 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

bool AArch64InstrInfo::isFPRCopy

(

const MachineInstr *

MI

)

const

Does this instruction rename an FPR without modifying bits?

Definition at line 1131 of file AArch64InstrInfo.cpp.

References contains(), llvm::TargetOpcode::COPY, llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isReg().

bool AArch64InstrInfo::isGPRCopy

(

const MachineInstr *

MI

)

const

Does this instruction rename a GPR without modifying bits?

Definition at line 1101 of file AArch64InstrInfo.cpp.

References contains(), llvm::TargetOpcode::COPY, llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

bool AArch64InstrInfo::isGPRZero

(

const MachineInstr *

MI

)

const

Does this instruction set its full destination register to zero?

Definition at line 1077 of file AArch64InstrInfo.cpp.

References llvm::TargetOpcode::COPY, llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isImm().

bool AArch64InstrInfo::isLdStPairSuppressed

(

const MachineInstr *

MI

)

const

Check all MachineMemOperands for a hint to suppress pairing.

Return true if pairing the given load or store is hinted to be unprofitable.

Definition at line 1259 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::memoperands(), llvm::MachineMemOperand::MOTargetNumBits, and llvm::MachineMemOperand::MOTargetStartBit.

unsigned AArch64InstrInfo::isLoadFromStackSlot	(	const MachineInstr *	MI,
		int &	FrameIndex
	)		const [override]

Definition at line 1152 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isFI(), and llvm::MachineOperand::isImm().

bool AArch64InstrInfo::isScaledAddr

(

const MachineInstr *

MI

)

const

Return true if this is load/store scales or extends its register offset. This refers to scaling a dynamic index as opposed to scaled immediates. MI should be a memory op that allows scaled addressing.

Definition at line 1200 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::AArch64_AM::getMemDoShift(), llvm::AArch64_AM::getMemExtendType(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::AArch64_AM::UXTX.

unsigned AArch64InstrInfo::isStoreToStackSlot	(	const MachineInstr *	MI,
		int &	FrameIndex
	)		const [override]

Definition at line 1175 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isFI(), and llvm::MachineOperand::isImm().

void AArch64InstrInfo::loadRegFromStackSlot	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		unsigned	DestReg,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI
	)		const [override]

Definition at line 1885 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), Align(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineBasicBlock::end(), llvm::getDefRegState(), llvm::PseudoSourceValue::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::getSize(), llvm::AArch64Subtarget::hasNEON(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::AArch64CC::MI, and llvm::MachineMemOperand::MOLoad.

bool AArch64InstrInfo::optimizeCompareInstr	(	MachineInstr *	CmpInstr,
		unsigned	SrcReg,
		unsigned	SrcReg2,
		int	CmpMask,
		int	CmpValue,
		const MachineRegisterInfo *	MRI
	)		const [override]

optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register.

Definition at line 773 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::addRegisterDefined(), llvm::MachineBasicBlock::begin(), llvm::MachineOperand::clobbersPhysReg(), convertFlagSettingOpcode(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::AArch64CC::GE, llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::AArch64CC::GT, I, llvm::MachineOperand::isDef(), llvm::MachineBasicBlock::isLiveIn(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), llvm::AArch64CC::LE, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::MachineInstr::modifiesRegister(), llvm::AArch64SysReg::NZCV, llvm::MachineInstr::readsRegister(), llvm::MachineInstr::RemoveOperand(), llvm::MachineInstr::setDesc(), llvm::MachineBasicBlock::successors(), UpdateOperandRegClass(), llvm::MachineRegisterInfo::use_nodbg_empty(), llvm::AArch64CC::VC, and llvm::AArch64CC::VS.

unsigned AArch64InstrInfo::RemoveBranch

(

MachineBasicBlock &

MBB

)

const [override]

Definition at line 226 of file AArch64InstrInfo.cpp.

References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), I, llvm::isCondBranchOpcode(), and llvm::isUncondBranchOpcode().

bool AArch64InstrInfo::ReverseBranchCondition

(

SmallVectorImpl< MachineOperand > &

Cond

)

const [override]

Definition at line 185 of file AArch64InstrInfo.cpp.

References llvm::AArch64CC::getInvertedCondCode(), and llvm_unreachable.

bool AArch64InstrInfo::shouldClusterLoads	(	MachineInstr *	FirstLdSt,
		MachineInstr *	SecondLdSt,
		unsigned	NumLoads
	)		const [override]

Detect opportunities for ldp/stp formation.

Only called for LdSt for which getLdStBaseRegImmOfs returns true.

Definition at line 1408 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().

bool AArch64InstrInfo::shouldScheduleAdjacent	(	MachineInstr *	First,
		MachineInstr *	Second
	)		const [override]

Definition at line 1426 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

void AArch64InstrInfo::storeRegToStackSlot	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		unsigned	SrcReg,
		bool	isKill,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI
	)		const [override]

Definition at line 1787 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), Align(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineBasicBlock::end(), llvm::PseudoSourceValue::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::getSize(), llvm::AArch64Subtarget::hasNEON(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::AArch64CC::MI, and llvm::MachineMemOperand::MOStore.

void AArch64InstrInfo::suppressLdStPair

(

MachineInstr *

MI

)

const

Hint that pairing the given load or store is unprofitable.

Set a flag on the first MachineMemOperand to suppress pairing.

Definition at line 1272 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_empty(), llvm::MachineMemOperand::MOTargetNumBits, and llvm::MachineMemOperand::MOTargetStartBit.

bool AArch64InstrInfo::useMachineCombiner

(

)

const [override]

useMachineCombiner - AArch64 supports MachineCombiner

useMachineCombiner - return true when a target supports MachineCombiner

Definition at line 2341 of file AArch64InstrInfo.cpp.

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The documentation for this class was generated from the following files:

• AArch64InstrInfo.h
• AArch64InstrInfo.cpp