AArch64ISelLowering.cpp File Reference

#include "AArch64ISelLowering.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64PerfectShuffle.h"
#include "AArch64Subtarget.h"
#include "AArch64TargetMachine.h"
#include "AArch64TargetObjectFile.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/Type.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetOptions.h"
#include "AArch64GenCallingConv.inc"

Include dependency graph for AArch64ISelLowering.cpp:

Go to the source code of this file.

Classes
struct	GenericSetCCInfo
	Helper structure to keep track of ISD::SET_CC operands. More...
struct	AArch64SetCCInfo
	Helper structure to keep track of a SET_CC lowered into AArch64 code. More...
union	SetCCInfo
	Helper structure to keep track of SetCC information. More...
struct	SetCCInfoAndKind
	Helper structure to be able to read SetCC information. If set to true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a GenericSetCCInfo. More...
Defines
#define	DEBUG_TYPE   "aarch64-lower"
Enumerations
enum	AlignMode
Functions
	STATISTIC (NumTailCalls,"Number of tail calls")
	STATISTIC (NumShiftInserts,"Number of vector shift inserts")
static cl::opt< AlignMode >	Align (cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
static TargetLoweringObjectFile *	createTLOF (const Triple &TT)
static AArch64CC::CondCode	changeIntCCToAArch64CC (ISD::CondCode CC)
static void	changeFPCCToAArch64CC (ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2)
	changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
static void	changeVectorFPCCToAArch64CC (ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2, bool &Invert)
static bool	isLegalArithImmed (uint64_t C)
static SDValue	emitComparison (SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl, SelectionDAG &DAG)
static SDValue	getAArch64Cmp (SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl)
static std::pair< SDValue, SDValue >	getAArch64XALUOOp (AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG)
static SDValue	LowerXOR (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerADDC_ADDE_SUBC_SUBE (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerXALUO (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerPREFETCH (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerVectorFP_TO_INT (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerVectorINT_TO_FP (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerBITCAST (SDValue Op, SelectionDAG &DAG)
static bool	selectCCOpsAreFMaxCompatible (SDValue Cmp, SDValue Result)
static SDValue	WidenVector (SDValue V64Reg, SelectionDAG &DAG)
static unsigned	getExtFactor (SDValue &V)
static SDValue	NarrowVector (SDValue V128Reg, SelectionDAG &DAG)
static bool	isSingletonEXTMask (ArrayRef< int > M, EVT VT, unsigned &Imm)
static bool	isEXTMask (ArrayRef< int > M, EVT VT, bool &ReverseEXT, unsigned &Imm)
static bool	isREVMask (ArrayRef< int > M, EVT VT, unsigned BlockSize)
static bool	isZIPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool	isUZPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool	isTRNMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool	isZIP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool	isUZP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool	isTRN_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool	isINSMask (ArrayRef< int > M, int NumInputElements, bool &DstIsLeft, int &Anomaly)
static bool	isConcatMask (ArrayRef< int > Mask, EVT VT, bool SplitLHS)
static SDValue	tryFormConcatFromShuffle (SDValue Op, SelectionDAG &DAG)
static SDValue	GeneratePerfectShuffle (unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, SDLoc dl)
static SDValue	GenerateTBL (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)
static unsigned	getDUPLANEOp (EVT EltType)
static bool	resolveBuildVector (BuildVectorSDNode *BVN, APInt &CnstBits, APInt &UndefBits)
static bool	isAllConstantBuildVector (const SDValue &PotentialBVec, uint64_t &ConstVal)
static unsigned	getIntrinsicID (const SDNode *N)
static SDValue	tryLowerToSLI (SDNode *N, SelectionDAG &DAG)
static SDValue	NormalizeBuildVector (SDValue Op, SelectionDAG &DAG)
static bool	getVShiftImm (SDValue Op, unsigned ElementBits, int64_t &Cnt)
static bool	isVShiftLImm (SDValue Op, EVT VT, bool isLong, int64_t &Cnt)
static bool	isVShiftRImm (SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, int64_t &Cnt)
static SDValue	EmitVectorComparison (SDValue LHS, SDValue RHS, AArch64CC::CondCode CC, bool NoNans, EVT VT, SDLoc dl, SelectionDAG &DAG)
static bool	memOpAlign (unsigned DstAlign, unsigned SrcAlign, unsigned AlignCheck)
static SDValue	performIntegerAbsCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performXorCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
static SDValue	performMulCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
static SDValue	performVectorCompareAndMaskUnaryOpCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performIntToFpCombine (SDNode *N, SelectionDAG &DAG)
static bool	findEXTRHalf (SDValue N, SDValue &Src, uint32_t &ShiftAmount, bool &FromHi)
static SDValue	tryCombineToEXTR (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	tryCombineToBSL (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
static SDValue	performBitcastCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	performConcatVectorsCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	tryCombineFixedPointConvert (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	tryExtendDUPToExtractHigh (SDValue N, SelectionDAG &DAG)
static bool	isEssentiallyExtractSubvector (SDValue N)
static bool	isSetCC (SDValue Op, SetCCInfoAndKind &SetCCInfo)
	Check whether or not Op is a SET_CC operation, either a generic or an AArch64 lowered one. SetCCInfo is filled accordingly.
static bool	isSetCCOrZExtSetCC (const SDValue &Op, SetCCInfoAndKind &Info)
static SDValue	performSetccAddFolding (SDNode *Op, SelectionDAG &DAG)
static SDValue	performAddSubLongCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	tryCombineLongOpWithDup (unsigned IID, SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	tryCombineShiftImm (unsigned IID, SDNode *N, SelectionDAG &DAG)
static SDValue	tryCombineCRC32 (unsigned Mask, SDNode *N, SelectionDAG &DAG)
static SDValue	performIntrinsicCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
static SDValue	performExtendCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	replaceSplatVectorStore (SelectionDAG &DAG, StoreSDNode *St)
static SDValue	performSTORECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
static SDValue	performPostLD1Combine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, bool IsLaneOp)
static SDValue	performNEONPostLDSTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static bool	checkValueWidth (SDValue V, unsigned width, ISD::LoadExtType &ExtType)
static bool	isEquivalentMaskless (unsigned CC, unsigned width, ISD::LoadExtType ExtType, signed AddConstant, signed CompConstant)
static SDValue	performCONDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, unsigned CCIndex, unsigned CmpIndex)
static SDValue	performBRCONDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
static SDValue	performVSelectCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performSelectCombine (SDNode *N, SelectionDAG &DAG)
static void	ReplaceBITCASTResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
Variables
static cl::opt< bool >	EnableAArch64ExtrGeneration ("aarch64-extr-generation", cl::Hidden, cl::desc("Allow AArch64 (or (shift)(shift))->extract"), cl::init(true))
static cl::opt< bool >	EnableAArch64SlrGeneration ("aarch64-shift-insert-generation", cl::Hidden, cl::desc("Allow AArch64 SLI/SRI formation"), cl::init(false))

---

Define Documentation

#define DEBUG_TYPE   "aarch64-lower"

Definition at line 36 of file AArch64ISelLowering.cpp.

---

Enumeration Type Documentation

enum AlignMode

Definition at line 42 of file AArch64ISelLowering.cpp.

---

Function Documentation

static cl::opt<AlignMode> Align	(	cl::	desc"Load/store alignment support",
		cl::Hidden	,
		cl::	initNoStrictAlign,
		cl::	valuesclEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd
	)		[static]

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AttrBuilder::addAlignmentAttr(), llvm::AttrBuilder::addStackAlignmentAttr(), AdjustStackOffset(), llvm::Recycler< MachineBasicBlock >::Allocate(), llvm::ArrayRecycler< MachineOperand >::allocate(), llvm::MCContext::Allocate(), CalculateStackSlotAlignment(), CalculateStackSlotUsed(), llvm::CC_ARM_AAPCS_Custom_HA(), clampStackAlignment(), computeKnownBits(), llvm::SelectionDAG::computeKnownBits(), llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachineFrameInfo::CreateFixedSpillStackObject(), llvm::SelectionDAG::CreateStackTemporary(), llvm::AArch64FrameLowering::eliminateCallFramePseudoInstr(), llvm::XCoreFrameLowering::eliminateCallFramePseudoInstr(), llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr(), llvm::RuntimeDyldImpl::emitCommonSymbols(), llvm::AsmPrinter::EmitConstantPool(), llvm::Thumb1FrameLowering::emitEpilogue(), llvm::ARMFrameLowering::emitEpilogue(), llvm::AsmPrinter::EmitGlobalVariable(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), enforceKnownAlignment(), llvm::MachineFrameInfo::ensureMaxAlignment(), estimateStackSize(), llvm::MachineFrameInfo::estimateStackSize(), FindMemType(), fixupFuncForFI(), llvm::ARMFunctionInfo::getArgRegsSaveSize(), llvm::PPCTargetLowering::getByValTypeAlignment(), llvm::SelectionDAG::getMemcpy(), getMemcpyLoadsAndStores(), llvm::SelectionDAG::getMemmove(), getMemmoveLoadsAndStores(), llvm::MipsInstrInfo::GetMemOperand(), llvm::SelectionDAG::getMemset(), getMemsetStores(), llvm::getOrEnforceKnownAlignment(), llvm::object::MachOObjectFile::getSectionAlignment(), llvm::SelectionDAG::getTargetConstantPool(), llvm::Attribute::getWithAlignment(), llvm::Attribute::getWithStackAlignment(), llvm::Hexagon_CCState::HandleByVal(), llvm::CCState::HandleByVal(), HandleByValArgument(), llvm::SelectionDAG::InferPtrAlignment(), llvm::isSafeToLoadUnconditionally(), llvm::RuntimeDyldImpl::loadObject(), llvm::HexagonInstrInfo::loadRegFromStackSlot(), llvm::AArch64InstrInfo::loadRegFromStackSlot(), llvm::ARMBaseInstrInfo::loadRegFromStackSlot(), llvm::SparcTargetLowering::LowerCall_32(), llvm::TargetLowering::LowerCallTo(), memsetStore(), llvm::Recycler< MachineBasicBlock >::PrintStats(), llvm::RoundUpToAlignment(), llvm::TargetLoweringObjectFileELF::SelectSectionForGlobal(), llvm::FunctionLoweringInfo::set(), llvm::MachineBasicBlock::setAlignment(), llvm::MCSymbolData::setCommon(), llvm::TargetLoweringBase::setJumpBufAlignment(), llvm::MachineFrameInfo::setLocalFrameMaxAlign(), llvm::TargetLoweringBase::setMinFunctionAlignment(), llvm::TargetLoweringBase::setMinStackArgumentAlignment(), llvm::MachineFrameInfo::setObjectAlignment(), llvm::TargetLoweringBase::setPrefFunctionAlignment(), llvm::TargetLoweringBase::setPrefLoopAlignment(), speculatePHINodeLoads(), llvm::HexagonInstrInfo::storeRegToStackSlot(), llvm::AArch64InstrInfo::storeRegToStackSlot(), llvm::ARMBaseInstrInfo::storeRegToStackSlot(), tryToMakeAllocaBePromotable(), llvm::InstCombiner::visitLoadInst(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), and llvm::MachObjectWriter::WriteNlist().

static void changeFPCCToAArch64CC	(	ISD::CondCode	CC,
		AArch64CC::CondCode &	CondCode,
		AArch64CC::CondCode &	CondCode2
	)		[static]

changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.

Definition at line 977 of file AArch64ISelLowering.cpp.

References llvm::AArch64CC::AL, llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::LE, llvm_unreachable, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, llvm::AArch64CC::PL, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, llvm::AArch64CC::VC, and llvm::AArch64CC::VS.

Referenced by changeVectorFPCCToAArch64CC().

static AArch64CC::CondCode changeIntCCToAArch64CC

(

ISD::CondCode

CC

)

[static]

changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64 CC

Definition at line 949 of file AArch64ISelLowering.cpp.

References llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::AArch64CC::LE, llvm_unreachable, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::NE, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.

Referenced by getAArch64Cmp().

static void changeVectorFPCCToAArch64CC	(	ISD::CondCode	CC,
		AArch64CC::CondCode &	CondCode,
		AArch64CC::CondCode &	CondCode2,
		bool &	Invert
	)		[static]

changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC usable with the vector instructions. Fewer operations are available without a real NZCV register, so we have to use less efficient combinations to get the same effect.

Definition at line 1041 of file AArch64ISelLowering.cpp.

References changeFPCCToAArch64CC(), llvm::AArch64CC::GE, llvm::ISD::getSetCCInverse(), llvm::AArch64CC::MI, llvm::ISD::SETO, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, and llvm::ISD::SETUO.

static bool checkValueWidth	(	SDValue	V,
		unsigned	width,
		ISD::LoadExtType &	ExtType
	)		[static]

Definition at line 7928 of file AArch64ISelLowering.cpp.

References llvm::LibFunc::abs, llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::Constant, llvm::LoadSDNode::getExtensionType(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::VTSDNode::getVT(), llvm::MVT::i16, llvm::MVT::i8, llvm::ISD::LOAD, llvm::ISD::NON_EXTLOAD, llvm::ISD::SEXTLOAD, llvm::ISD::TargetConstant, and llvm::ISD::ZEXTLOAD.

Referenced by performCONDCombine().

static TargetLoweringObjectFile* createTLOF

(

const Triple &

TT

)

[static]

Definition at line 72 of file AArch64ISelLowering.cpp.

References llvm::Triple::isOSBinFormatMachO().

static SDValue emitComparison	(	SDValue	LHS,
		SDValue	RHS,
		ISD::CondCode	CC,
		SDLoc	dl,
		SelectionDAG &	DAG
	)		[static]

Definition at line 1075 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::ADDS, llvm::ISD::AND, llvm::AArch64ISD::ANDS, llvm::AArch64ISD::FCMP, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::EVT::isFloatingPoint(), llvm::ISD::isUnsignedIntSetCC(), llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::ISD::SUB, and llvm::AArch64ISD::SUBS.

Referenced by getAArch64Cmp().

static SDValue EmitVectorComparison	(	SDValue	LHS,
		SDValue	RHS,
		AArch64CC::CondCode	CC,
		bool	NoNans,
		EVT	VT,
		SDLoc	dl,
		SelectionDAG &	DAG
	)		[static]

Definition at line 6074 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::CMEQ, llvm::AArch64ISD::CMEQz, llvm::AArch64ISD::CMGE, llvm::AArch64ISD::CMGEz, llvm::AArch64ISD::CMGT, llvm::AArch64ISD::CMGTz, llvm::AArch64ISD::CMHI, llvm::AArch64ISD::CMHS, llvm::AArch64ISD::CMLEz, llvm::AArch64ISD::CMLTz, llvm::dyn_cast(), llvm::AArch64CC::EQ, llvm::AArch64ISD::FCMEQ, llvm::AArch64ISD::FCMEQz, llvm::AArch64ISD::FCMGE, llvm::AArch64ISD::FCMGEz, llvm::AArch64ISD::FCMGT, llvm::AArch64ISD::FCMGTz, llvm::AArch64ISD::FCMLEz, llvm::AArch64ISD::FCMLTz, llvm::AArch64CC::GE, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::EVT::isFloatingPoint(), llvm::AArch64CC::LE, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, llvm::AArch64ISD::NOT, and resolveBuildVector().

static bool findEXTRHalf	(	SDValue	N,
		SDValue &	Src,
		uint32_t &	ShiftAmount,
		bool &	FromHi
	)		[static]

An EXTR instruction is made up of two shifts, ORed together. This helper searches for and classifies those shifts.

Definition at line 6798 of file AArch64ISelLowering.cpp.

References llvm::SDNode::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::ISD::SHL, and llvm::ISD::SRL.

Referenced by tryCombineToEXTR().

static SDValue GeneratePerfectShuffle	(	unsigned	PFEntry,
		SDValue	LHS,
		SDValue	RHS,
		SelectionDAG &	DAG,
		SDLoc	dl
	)		[static]

GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.

Definition at line 4785 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::AArch64ISD::DUPLANE64, llvm::AArch64ISD::DUPLANE8, llvm::AArch64ISD::EXT, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::SelectionDAG::getConstant(), getExtFactor(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm_unreachable, PerfectShuffleTable, llvm::AArch64ISD::REV16, llvm::AArch64ISD::REV32, llvm::AArch64ISD::REV64, llvm::AArch64ISD::TRN1, llvm::AArch64ISD::TRN2, llvm::AArch64ISD::UZP1, llvm::AArch64ISD::UZP2, WidenVector(), llvm::AArch64ISD::ZIP1, and llvm::AArch64ISD::ZIP2.

static SDValue GenerateTBL	(	SDValue	Op,
		ArrayRef< int >	ShuffleMask,
		SelectionDAG &	DAG
	)		[static]

Definition at line 4887 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::SmallVectorTemplateCommon< T, typename >::data(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::makeArrayRef(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::ISD::UNDEF, llvm::MVT::v16i8, llvm::NVPTX::PTXLdStInstCode::V2, and llvm::MVT::v8i8.

static SDValue getAArch64Cmp	(	SDValue	LHS,
		SDValue	RHS,
		ISD::CondCode	CC,
		SDValue &	AArch64cc,
		SelectionDAG &	DAG,
		SDLoc	dl
	)		[static]

Definition at line 1118 of file AArch64ISelLowering.cpp.

References llvm::CallingConv::C, changeIntCCToAArch64CC(), emitComparison(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::SDNode::hasNUsesOfValue(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, isLegalArithImmed(), llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::SExt, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::ZEXTLOAD.

Referenced by LowerXOR(), and performSetccAddFolding().

static std::pair<SDValue, SDValue> getAArch64XALUOOp	(	AArch64CC::CondCode &	CC,
		SDValue	Op,
		SelectionDAG &	DAG
	)		[static]

Definition at line 1220 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, llvm::AArch64ISD::ADDS, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::AArch64CC::HS, llvm::MVT::i32, llvm::MVT::i64, llvm_unreachable, llvm::AArch64CC::LO, llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::AArch64CC::NE, llvm::ISD::SADDO, llvm::ISD::SIGN_EXTEND, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SSUBO, llvm::AArch64ISD::SUBS, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::AArch64CC::VS, and llvm::ISD::ZERO_EXTEND.

Referenced by LowerXALUO().

static unsigned getDUPLANEOp

(

EVT

EltType

)

[static]

Definition at line 4949 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::AArch64ISD::DUPLANE64, llvm::AArch64ISD::DUPLANE8, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, and llvm_unreachable.

static unsigned getExtFactor

(

SDValue &

V

)

[static]

getExtFactor - Determine the adjustment factor for the position when generating an "extract from vector registers" instruction.

Definition at line 4296 of file AArch64ISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), and llvm::EVT::getVectorElementType().

Referenced by GeneratePerfectShuffle(), and llvm::AArch64TargetLowering::ReconstructShuffle().

static unsigned getIntrinsicID

(

const SDNode *

N

)

[static]

Definition at line 5252 of file AArch64ISelLowering.cpp.

References llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::Intrinsic::not_intrinsic.

Referenced by performExtendCombine(), and performIntrinsicCombine().

static bool getVShiftImm	(	SDValue	Op,
		unsigned	ElementBits,
		int64_t &	Cnt
	)		[static]

getVShiftImm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value.

Definition at line 5981 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::APInt::getSExtValue(), and llvm::BuildVectorSDNode::isConstantSplat().

Referenced by isVShiftLImm(), and isVShiftRImm().

static bool isAllConstantBuildVector	(	const SDValue &	PotentialBVec,
		uint64_t &	ConstVal
	)		[static]

Definition at line 5235 of file AArch64ISelLowering.cpp.

References llvm::dyn_cast(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), and llvm::ConstantSDNode::getZExtValue().

Referenced by tryLowerToSLI().

static bool isConcatMask	(	ArrayRef< int >	Mask,
		EVT	VT,
		bool	SplitLHS
	)		[static]

Definition at line 4734 of file AArch64ISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::EVT::getVectorNumElements(), and I.

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal(), and tryFormConcatFromShuffle().

static bool isEquivalentMaskless	(	unsigned	CC,
		unsigned	width,
		ISD::LoadExtType	ExtType,
		signed	AddConstant,
		signed	CompConstant
	)		[static]

Definition at line 8034 of file AArch64ISelLowering.cpp.

References llvm::AArch64CC::AL, llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::AArch64CC::Invalid, llvm::AArch64CC::LE, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, llvm::AArch64CC::NV, llvm::AArch64CC::PL, llvm::ISD::SEXTLOAD, llvm::AArch64CC::VC, and llvm::AArch64CC::VS.

Referenced by performCONDCombine().

static bool isEssentiallyExtractSubvector

(

SDValue

N

)

[static]

Definition at line 7141 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SDValue::getOpcode(), and llvm::SDValue::getOperand().

Referenced by performAddSubLongCombine(), and tryCombineLongOpWithDup().

static bool isEXTMask	(	ArrayRef< int >	M,
		EVT	VT,
		bool &	ReverseEXT,
		unsigned &	Imm
	)		[static]

Definition at line 4538 of file AArch64ISelLowering.cpp.

References llvm::ArrayRef< T >::begin(), llvm::ArrayRef< T >::end(), llvm::EVT::getVectorNumElements(), llvm::APInt::getZExtValue(), and llvm::APInt::logBase2().

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().

static bool isINSMask	(	ArrayRef< int >	M,
		int	NumInputElements,
		bool &	DstIsLeft,
		int &	Anomaly
	)		[static]

Definition at line 4695 of file AArch64ISelLowering.cpp.

References llvm::ArrayRef< T >::size().

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().

static bool isLegalArithImmed

(

uint64_t

C

)

[static]

Definition at line 1070 of file AArch64ISelLowering.cpp.

Referenced by getAArch64Cmp().

static bool isREVMask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned	BlockSize
	)		[static]

isREVMask - Check if a vector shuffle corresponds to a REV instruction with the specified blocksize. (The order of the elements within each block of the vector is reversed.)

Definition at line 4580 of file AArch64ISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), and llvm::EVT::getVectorNumElements().

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().

static bool isSetCC	(	SDValue	Op,
		SetCCInfoAndKind &	SetCCInfo
	)		[static]

Check whether or not Op is a SET_CC operation, either a generic or an AArch64 lowered one. SetCCInfo is filled accordingly.

Postcondition:

SetCCInfo is meanginfull only when this function returns true.

Returns:

True when Op is a kind of SET_CC operation.

Definition at line 7182 of file AArch64ISelLowering.cpp.

References SetCCInfo::AArch64, GenericSetCCInfo::CC, AArch64SetCCInfo::CC, AArch64SetCCInfo::Cmp, llvm::AArch64ISD::CSEL, llvm::dyn_cast(), SetCCInfo::Generic, llvm::AArch64CC::getInvertedCondCode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), SetCCInfoAndKind::Info, SetCCInfoAndKind::IsAArch64, llvm::ConstantSDNode::isOne(), GenericSetCCInfo::Opnd0, GenericSetCCInfo::Opnd1, llvm::ISD::SETCC, and std::swap().

Referenced by isSetCCOrZExtSetCC().

static bool isSetCCOrZExtSetCC	(	const SDValue &	Op,
		SetCCInfoAndKind &	Info
	)		[static]

Definition at line 7225 of file AArch64ISelLowering.cpp.

References llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), isSetCC(), and llvm::ISD::ZERO_EXTEND.

Referenced by performSetccAddFolding().

static bool isSingletonEXTMask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	Imm
	)		[static]

Definition at line 4507 of file AArch64ISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

static bool isTRN_v_undef_Mask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	WhichResult
	)		[static]

isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.

Definition at line 4684 of file AArch64ISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().

static bool isTRNMask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	WhichResult
	)		[static]

Definition at line 4634 of file AArch64ISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().

static bool isUZP_v_undef_Mask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	WhichResult
	)		[static]

isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,

Definition at line 4665 of file AArch64ISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().

static bool isUZPMask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	WhichResult
	)		[static]

Definition at line 4621 of file AArch64ISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().

static bool isVShiftLImm	(	SDValue	Op,
		EVT	VT,
		bool	isLong,
		int64_t &	Cnt
	)		[static]

isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation. That value must be in the range: 0 <= Value < ElementBits for a left shift; or 0 <= Value <= ElementBits for a long left shift.

Definition at line 6001 of file AArch64ISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), getVShiftImm(), and llvm::EVT::isVector().

static bool isVShiftRImm	(	SDValue	Op,
		EVT	VT,
		bool	isNarrow,
		bool	isIntrinsic,
		int64_t &	Cnt
	)		[static]

isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation. For a shift opcode, the value is positive, but for an intrinsic the value count must be negative. The absolute value must be in the range: 1 <= |Value| <= ElementBits for a right shift; or 1 <= |Value| <= ElementBits/2 for a narrow right shift.

Definition at line 6015 of file AArch64ISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), getVShiftImm(), and llvm::EVT::isVector().

static bool isZIP_v_undef_Mask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	WhichResult
	)		[static]

isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.

Definition at line 4648 of file AArch64ISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().

static bool isZIPMask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	WhichResult
	)		[static]

Definition at line 4607 of file AArch64ISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().

static SDValue LowerADDC_ADDE_SUBC_SUBE	(	SDValue	Op,
		SelectionDAG &	DAG
	)		[static]

Definition at line 1401 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::ADCS, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::AArch64ISD::ADDS, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::AArch64ISD::SBCS, llvm::ISD::SUBC, llvm::ISD::SUBE, and llvm::AArch64ISD::SUBS.

Referenced by llvm::AArch64TargetLowering::LowerOperation().

static SDValue LowerBITCAST	(	SDValue	Op,
		SelectionDAG &	DAG
	)		[static]

Definition at line 1655 of file AArch64ISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::ISD::BITCAST, llvm::TargetOpcode::EXTRACT_SUBREG, llvm::MVT::f16, llvm::MVT::f32, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::MVT::i16, and llvm::MVT::i32.

Referenced by llvm::AArch64TargetLowering::LowerOperation().

static SDValue LowerPREFETCH	(	SDValue	Op,
		SelectionDAG &	DAG
	)		[static]

Definition at line 1467 of file AArch64ISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::MVT::i32, llvm::MVT::Other, and llvm::AArch64ISD::PREFETCH.

Referenced by llvm::AArch64TargetLowering::LowerOperation().

static SDValue LowerVectorFP_TO_INT	(	SDValue	Op,
		SelectionDAG &	DAG
	)		[static]

Definition at line 1521 of file AArch64ISelLowering.cpp.

References llvm::EVT::changeVectorElementTypeToInteger(), llvm::MipsISD::Ext, llvm::ISD::FP_EXTEND, llvm::MVT::getFloatingPointVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), and llvm::ISD::TRUNCATE.

static SDValue LowerVectorINT_TO_FP	(	SDValue	Op,
		SelectionDAG &	DAG
	)		[static]

Definition at line 1573 of file AArch64ISelLowering.cpp.

References llvm::EVT::changeVectorElementTypeToInteger(), llvm::ISD::FP_ROUND, llvm::MVT::getFloatingPointVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::tgtok::In, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, and llvm::ISD::ZERO_EXTEND.

static SDValue LowerXALUO	(	SDValue	Op,
		SelectionDAG &	DAG
	)		[static]

Definition at line 1437 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::CSEL, getAArch64XALUOOp(), llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::TargetLoweringBase::isTypeLegal(), and llvm::ISD::MERGE_VALUES.

Referenced by llvm::AArch64TargetLowering::LowerOperation().

static SDValue LowerXOR	(	SDValue	Op,
		SelectionDAG &	DAG
	)		[static]

Definition at line 1342 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::CSEL, llvm::dyn_cast(), getAArch64Cmp(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::MVT::i64, llvm::ConstantSDNode::isAllOnesValue(), llvm::ConstantSDNode::isNullValue(), llvm::ISD::SELECT_CC, std::swap(), and llvm::ISD::XOR.

Referenced by llvm::AArch64TargetLowering::LowerOperation().

static bool memOpAlign	(	unsigned	DstAlign,
		unsigned	SrcAlign,
		unsigned	AlignCheck
	)		[static]

Definition at line 6395 of file AArch64ISelLowering.cpp.

Referenced by llvm::AArch64TargetLowering::getOptimalMemOpType().

static SDValue NarrowVector	(	SDValue	V128Reg,
		SelectionDAG &	DAG
	)		[static]

NarrowVector - Given a value in the V128 register class, produce the equivalent value in the V64 register class.

Definition at line 4303 of file AArch64ISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), and llvm::MVT::getVectorVT().

static SDValue NormalizeBuildVector	(	SDValue	Op,
		SelectionDAG &	DAG
	)		[static]

Definition at line 5434 of file AArch64ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::ISD::Constant, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), I, llvm::MVT::i32, llvm::EVT::isFloatingPoint(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

static SDValue performAddSubLongCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		SelectionDAG &	DAG
	)		[static]

Definition at line 7287 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::is128BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), isEssentiallyExtractSubvector(), performSetccAddFolding(), llvm::ISD::SIGN_EXTEND, tryExtendDUPToExtractHigh(), and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

static SDValue performBitcastCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		SelectionDAG &	DAG
	)		[static]

Definition at line 6929 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::dbgs(), DEBUG, llvm::TargetOpcode::EXTRACT_SUBREG, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMachineNode(), llvm::SDNode::getMachineOpcode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSimpleVT(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i32, llvm::MVT::i64, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::SDNode::isMachineOpcode(), llvm::EVT::isVector(), and llvm::Sched::Source.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

static SDValue performBRCONDCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		SelectionDAG &	DAG
	)		[static]

Definition at line 8185 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::ADDS, llvm::ISD::BR, llvm::AArch64ISD::CBNZ, llvm::AArch64ISD::CBZ, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::AArch64CC::EQ, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::hasNUsesOfValue(), llvm::MVT::i32, llvm::MVT::i64, llvm::AArch64CC::NE, llvm::AArch64CC::NV, llvm::MVT::Other, performCONDCombine(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::AArch64ISD::SUBS, and std::swap().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

static SDValue performConcatVectorsCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		SelectionDAG &	DAG
	)		[static]

Definition at line 6995 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, llvm::dbgs(), DEBUG, llvm::AArch64ISD::DUPLANE64, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::MVT::i64, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::MVT::isVector(), and WidenVector().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

static SDValue performCONDCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		SelectionDAG &	DAG,
		unsigned	CCIndex,
		unsigned	CmpIndex
	)		[static]

Definition at line 8111 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, checkValueWidth(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), isEquivalentMaskless(), llvm::SelectionDAG::ReplaceAllUsesWith(), and llvm::AArch64ISD::SUBS.

Referenced by performBRCONDCombine(), and llvm::AArch64TargetLowering::PerformDAGCombine().

static SDValue performExtendCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		SelectionDAG &	DAG
	)		[static]

Definition at line 7477 of file AArch64ISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getContext(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getIntPtrConstant(), getIntrinsicID(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::getVectorVT(), llvm::HexagonISD::Hi, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::EVT::isSimple(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::HexagonISD::Lo, tryCombineLongOpWithDup(), and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

static SDValue performIntegerAbsCombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)		[static]

Definition at line 6573 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, llvm::AArch64ISD::CSEL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::EVT::isInteger(), llvm::AArch64CC::PL, llvm::ISD::SRA, llvm::ISD::SUB, llvm::AArch64ISD::SUBS, and llvm::ISD::XOR.

Referenced by performXorCombine().

static SDValue performIntrinsicCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const AArch64Subtarget *	Subtarget
	)		[static]

Definition at line 7438 of file AArch64ISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::AArch64ISD::FMAX, llvm::AArch64ISD::FMIN, getIntrinsicID(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), tryCombineCRC32(), tryCombineFixedPointConvert(), tryCombineLongOpWithDup(), and tryCombineShiftImm().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

static SDValue performIntToFpCombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)		[static]

Definition at line 6756 of file AArch64ISelLowering.cpp.

References llvm::MVT::f32, llvm::MVT::f64, llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getLoad(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), llvm::MemSDNode::isInvariant(), llvm::MemSDNode::isNonTemporal(), llvm::ISD::isNormalLoad(), llvm::MemSDNode::isVolatile(), llvm::SPII::Load, performVectorCompareAndMaskUnaryOpCombine(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SINT_TO_FP, llvm::AArch64ISD::SITOF, and llvm::AArch64ISD::UITOF.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

static SDValue performMulCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const AArch64Subtarget *	Subtarget
	)		[static]

Definition at line 6652 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::MVT::i64, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::APInt::isNonNegative(), llvm::APInt::isPowerOf2(), llvm::APInt::logBase2(), llvm::ISD::SHL, and llvm::ISD::SUB.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

static SDValue performNEONPostLDSTCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		SelectionDAG &	DAG
	)		[static]

Target-specific DAG combine function for NEON load/store intrinsics to merge base address updates.

Definition at line 7795 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getRegister(), llvm::SDValue::getResNo(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::MVT::i64, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::SDNode::isPredecessorOf(), llvm::AArch64ISD::LD1x2post, llvm::AArch64ISD::LD1x3post, llvm::AArch64ISD::LD1x4post, llvm::AArch64ISD::LD2DUPpost, llvm::AArch64ISD::LD2LANEpost, llvm::AArch64ISD::LD2post, llvm::AArch64ISD::LD3DUPpost, llvm::AArch64ISD::LD3LANEpost, llvm::AArch64ISD::LD3post, llvm::AArch64ISD::LD4DUPpost, llvm::AArch64ISD::LD4LANEpost, llvm::AArch64ISD::LD4post, llvm_unreachable, llvm::makeArrayRef(), llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::AArch64ISD::ST1x2post, llvm::AArch64ISD::ST1x3post, llvm::AArch64ISD::ST1x4post, llvm::AArch64ISD::ST2LANEpost, llvm::AArch64ISD::ST2post, llvm::AArch64ISD::ST3LANEpost, llvm::AArch64ISD::ST3post, llvm::AArch64ISD::ST4LANEpost, llvm::AArch64ISD::ST4post, llvm::SDNode::use_begin(), and llvm::SDNode::use_end().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

static SDValue performORCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const AArch64Subtarget *	Subtarget
	)		[static]

Definition at line 6907 of file AArch64ISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, EnableAArch64ExtrGeneration, llvm::SDValue::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::TargetLoweringBase::isTypeLegal(), tryCombineToBSL(), and tryCombineToEXTR().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

static SDValue performPostLD1Combine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		bool	IsLaneOp
	)		[static]

Target-specific DAG combine function for post-increment LD1 (lane) and post-increment LD1R.

Definition at line 7704 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getRegister(), llvm::SDValue::getResNo(), llvm::EVT::getScalarSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i64, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::SDNode::isPredecessorOf(), llvm::AArch64DB::LD, llvm::AArch64ISD::LD1DUPpost, llvm::AArch64ISD::LD1LANEpost, llvm::ISD::LOAD, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::SDNode::use_begin(), and llvm::SDNode::use_end().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

static SDValue performSelectCombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)		[static]

A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with the compare-mask instructions rather than going via NZCV, even if LHS and RHS are really scalar. This replaces any scalar setcc in the above pattern with a vector one followed by a DUP shuffle on the result.

Definition at line 8275 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::EVT::changeVectorElementTypeToInteger(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSelect(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::MVT::i1, llvm::EVT::isVector(), llvm::ISD::SCALAR_TO_VECTOR, and llvm::ISD::SETCC.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

static SDValue performSetccAddFolding	(	SDNode *	Op,
		SelectionDAG &	DAG
	)		[static]

Definition at line 7238 of file AArch64ISelLowering.cpp.

References SetCCInfo::AArch64, llvm::ISD::ADD, GenericSetCCInfo::CC, AArch64SetCCInfo::CC, AArch64SetCCInfo::Cmp, llvm::AArch64ISD::CSEL, SetCCInfo::Generic, getAArch64Cmp(), llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, SetCCInfoAndKind::Info, SetCCInfoAndKind::IsAArch64, isSetCCOrZExtSetCC(), GenericSetCCInfo::Opnd0, GenericSetCCInfo::Opnd1, and std::swap().

Referenced by performAddSubLongCombine().

static SDValue performSTORECombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		SelectionDAG &	DAG,
		const AArch64Subtarget *	Subtarget
	)		[static]

Definition at line 7635 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::EXTRACT_SUBVECTOR, llvm::AttributeSet::FunctionIndex, llvm::MemSDNode::getAlignment(), llvm::Function::getAttributes(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getStore(), llvm::SDValue::getValue(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::AttributeSet::hasAttribute(), llvm::MVT::i64, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::AArch64Subtarget::isCyclone(), llvm::MemSDNode::isNonTemporal(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), llvm::Attribute::MinSize, replaceSplatVectorStore(), and llvm::MVT::v2i64.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

static SDValue performVectorCompareAndMaskUnaryOpCombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)		[static]

Definition at line 6710 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::isVector(), and llvm::ISD::SETCC.

Referenced by performIntToFpCombine().

static SDValue performVSelectCombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)		[static]

Definition at line 8246 of file AArch64ISelLowering.cpp.

References llvm::EVT::changeVectorElementTypeToInteger(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i1, llvm::ISD::SETCC, and llvm::ISD::VSELECT.

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

static SDValue performXorCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		TargetLowering::DAGCombinerInfo &	DCI,
		const AArch64Subtarget *	Subtarget
	)		[static]

Definition at line 6601 of file AArch64ISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), and performIntegerAbsCombine().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

static void ReplaceBITCASTResults	(	SDNode *	N,
		SmallVectorImpl< SDValue > &	Results,
		SelectionDAG &	DAG
	)		[static]

Definition at line 8502 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::MVT::f16, llvm::MVT::f32, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::TargetOpcode::INSERT_SUBREG, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), and llvm::ISD::TRUNCATE.

static SDValue replaceSplatVectorStore	(	SelectionDAG &	DAG,
		StoreSDNode *	St
	)		[static]

Replace a splat of a scalar to a vector store by scalar stores of the scalar value. The load store optimizer pass will merge them to store pair stores. This has better performance than a splat of the scalar followed by a split vector store. Even if the stores are not merged it is four stores vs a dup, followed by an ext.b and two stores.

Definition at line 7580 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, llvm::MemSDNode::getAlignment(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::SelectionDAG::getStore(), llvm::SDValue::getValue(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i64, llvm::ISD::INSERT_VECTOR_ELT, llvm::EVT::isFloatingPoint(), llvm::MemSDNode::isNonTemporal(), and llvm::MemSDNode::isVolatile().

Referenced by performSTORECombine().

static bool resolveBuildVector	(	BuildVectorSDNode *	BVN,
		APInt &	CnstBits,
		APInt &	UndefBits
	)		[static]

Definition at line 5117 of file AArch64ISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::BuildVectorSDNode::isConstantSplat(), and llvm::APInt::zextOrTrunc().

Referenced by EmitVectorComparison().

static bool selectCCOpsAreFMaxCompatible	(	SDValue	Cmp,
		SDValue	Result
	)		[static]

A SELECT_CC operation is really some kind of max or min if both values being compared are, in some sense, equal to the results in either case. However, it is permissible to compare f32 values and produce directly extended f64 values.

Extending the comparison operands would also be allowed, but is less likely to happen in practice since their use is right here. Note that truncate operations would *not* be semantically equivalent.

Definition at line 3356 of file AArch64ISelLowering.cpp.

References llvm::APFloat::convert(), llvm::dyn_cast(), llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FP_EXTEND, llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ConstantFPSDNode::getValueAPF(), llvm::SDValue::getValueType(), llvm::APFloat::IEEEdouble, and llvm::APFloat::rmNearestTiesToEven.

STATISTIC	(	NumTailCalls	,
		"Number of tail calls"
	)

STATISTIC	(	NumShiftInserts	,
		"Number of vector shift inserts"
	)

static SDValue tryCombineCRC32	(	unsigned	Mask,
		SDNode *	N,
		SelectionDAG &	DAG
	)		[static]

Definition at line 7425 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i32, and llvm::ISD::INTRINSIC_WO_CHAIN.

Referenced by performIntrinsicCombine().

static SDValue tryCombineFixedPointConvert	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		SelectionDAG &	DAG
	)		[static]

Definition at line 7044 of file AArch64ISelLowering.cpp.

References llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm_unreachable, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, and llvm::MVT::v4i32.

Referenced by performIntrinsicCombine().

static SDValue tryCombineLongOpWithDup	(	unsigned	IID,
		SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		SelectionDAG &	DAG
	)		[static]

Definition at line 7336 of file AArch64ISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is64BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), isEssentiallyExtractSubvector(), and tryExtendDUPToExtractHigh().

Referenced by performExtendCombine(), and performIntrinsicCombine().

static SDValue tryCombineShiftImm	(	unsigned	IID,
		SDNode *	N,
		SelectionDAG &	DAG
	)		[static]

Definition at line 7365 of file AArch64ISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::MVT::getScalarType(), llvm::APInt::getSExtValue(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::BuildVectorSDNode::isConstantSplat(), llvm_unreachable, llvm::AArch64ISD::SQSHL_I, llvm::AArch64ISD::SQSHLU_I, llvm::AArch64ISD::SRSHR_I, llvm::AArch64ISD::UQSHL_I, and llvm::AArch64ISD::URSHR_I.

Referenced by performIntrinsicCombine().

static SDValue tryCombineToBSL	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI
	)		[static]

Definition at line 6860 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, llvm::tgtok::Bits, llvm::AArch64ISD::BSL, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), and llvm::EVT::isVector().

Referenced by performORCombine().

static SDValue tryCombineToEXTR	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI
	)		[static]

EXTR instruction extracts a contiguous chunk of bits from two existing registers viewed as a high/low pair. This function looks for the pattern: (or (shl VAL1, N), (srl VAL2, #RegWidth-N)) and replaces it with an EXTR. Can't quite be done in TableGen because the two immediates aren't independent.

Definition at line 6820 of file AArch64ISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::AArch64ISD::EXTR, findEXTRHalf(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::OR, and std::swap().

Referenced by performORCombine().

static SDValue tryExtendDUPToExtractHigh	(	SDValue	N,
		SelectionDAG &	DAG
	)		[static]

Definition at line 7104 of file AArch64ISelLowering.cpp.

References llvm::AArch64ISD::DUP, llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::AArch64ISD::DUPLANE64, llvm::AArch64ISD::DUPLANE8, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::MVT::i64, and llvm::MVT::is64BitVector().

Referenced by performAddSubLongCombine(), and tryCombineLongOpWithDup().

static SDValue tryFormConcatFromShuffle	(	SDValue	Op,
		SelectionDAG &	DAG
	)		[static]

Definition at line 4754 of file AArch64ISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::i64, and isConcatMask().

static SDValue tryLowerToSLI	(	SDNode *	N,
		SelectionDAG &	DAG
	)		[static]

Definition at line 5270 of file AArch64ISelLowering.cpp.

References llvm::ISD::AND, llvm::APIntOps::And(), llvm::dbgs(), DEBUG, llvm::SDNode::dump(), llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, isAllConstantBuildVector(), llvm::EVT::isVector(), llvm::AArch64ISD::VLSHR, llvm::AArch64ISD::VSHL, llvm::X, and Y.

static SDValue WidenVector	(	SDValue	V64Reg,
		SelectionDAG &	DAG
	)		[static]

WidenVector - Given a value in the V64 register class, produce the equivalent value in the V128 register class.

Definition at line 4283 of file AArch64ISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::MVT::i32, and llvm::ISD::INSERT_SUBVECTOR.

Referenced by GeneratePerfectShuffle(), and performConcatVectorsCombine().

---

Variable Documentation

cl::opt<bool> EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden, cl::desc("Allow AArch64 (or (shift)(shift))->extract"), cl::init(true)) [static]

Referenced by performORCombine().

cl::opt<bool> EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden, cl::desc("Allow AArch64 SLI/SRI formation"), cl::init(false)) [static]