#include <SelectionDAGISel.h>

Inheritance diagram for llvm::SelectionDAGISel:

Collaboration diagram for llvm::SelectionDAGISel:

Public Types
enum	BuiltinOpcodes { OPC_Scope, OPC_RecordNode, OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3, OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7, OPC_RecordMemRef, OPC_CaptureGlueInput, OPC_MoveChild, OPC_MoveParent, OPC_CheckSame, OPC_CheckChild0Same, OPC_CheckChild1Same, OPC_CheckChild2Same, OPC_CheckChild3Same, OPC_CheckPatternPredicate, OPC_CheckPredicate, OPC_CheckOpcode, OPC_SwitchOpcode, OPC_CheckType, OPC_SwitchType, OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type, OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type, OPC_CheckChild6Type, OPC_CheckChild7Type, OPC_CheckInteger, OPC_CheckChild0Integer, OPC_CheckChild1Integer, OPC_CheckChild2Integer, OPC_CheckChild3Integer, OPC_CheckChild4Integer, OPC_CheckCondCode, OPC_CheckValueType, OPC_CheckComplexPat, OPC_CheckAndImm, OPC_CheckOrImm, OPC_CheckFoldableChainNode, OPC_EmitInteger, OPC_EmitRegister, OPC_EmitRegister2, OPC_EmitConvertToTarget, OPC_EmitMergeInputChains, OPC_EmitMergeInputChains1_0, OPC_EmitMergeInputChains1_1, OPC_EmitCopyToReg, OPC_EmitNodeXForm, OPC_EmitNode, OPC_MorphNodeTo, OPC_MarkGlueResults, OPC_CompleteMatch }
enum	{ OPFL_None = 0, OPFL_Chain = 1, OPFL_GlueInput = 2, OPFL_GlueOutput = 4, OPFL_MemRefs = 8, OPFL_Variadic0 = 1<<4, OPFL_Variadic1 = 2<<4, OPFL_Variadic2 = 3<<4, OPFL_Variadic3 = 4<<4, OPFL_Variadic4 = 5<<4, OPFL_Variadic5 = 6<<4, OPFL_Variadic6 = 7<<4, OPFL_VariadicInfo = OPFL_Variadic6 }
Public Member Functions
	SelectionDAGISel (TargetMachine &tm, CodeGenOpt::Level OL=CodeGenOpt::Default)
virtual	~SelectionDAGISel ()
const TargetLowering *	getTargetLowering () const
void	getAnalysisUsage (AnalysisUsage &AU) const override
bool	runOnMachineFunction (MachineFunction &MF) override
virtual void	EmitFunctionEntryCode ()
virtual void	PreprocessISelDAG ()
virtual void	PostprocessISelDAG ()
virtual SDNode *	Select (SDNode *N)=0
	Select - Main hook targets implement to select a node.
virtual bool	SelectInlineAsmMemoryOperand (const SDValue &Op, char ConstraintCode, std::vector< SDValue > &OutOps)
virtual bool	IsProfitableToFold (SDValue N, SDNode U, SDNode Root) const
bool	CheckAndMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
bool	CheckOrMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
virtual bool	CheckPatternPredicate (unsigned PredNo) const
virtual bool	CheckNodePredicate (SDNode *N, unsigned PredNo) const
virtual bool	CheckComplexPattern (SDNode Root, SDNode Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode * > > &Result)
virtual SDValue	RunSDNodeXForm (SDValue V, unsigned XFormNo)
SDNode *	SelectCodeCommon (SDNode NodeToMatch, const unsigned char MatcherTable, unsigned TableSize)
Static Public Member Functions
static bool	IsLegalToFold (SDValue N, SDNode U, SDNode Root, CodeGenOpt::Level OptLevel, bool IgnoreChains=false)
static int	getNumFixedFromVariadicInfo (unsigned Flags)
Public Attributes
TargetMachine &	TM
const TargetLibraryInfo *	LibInfo
FunctionLoweringInfo *	FuncInfo
MachineFunction *	MF
MachineRegisterInfo *	RegInfo
SelectionDAG *	CurDAG
SelectionDAGBuilder *	SDB
AliasAnalysis *	AA
GCFunctionInfo *	GFI
CodeGenOpt::Level	OptLevel
Static Public Attributes
static char	ID = 0
Protected Member Functions
void	ReplaceUses (SDValue F, SDValue T)
void	ReplaceUses (const SDValue F, const SDValue T, unsigned Num)
void	ReplaceUses (SDNode F, SDNode T)
void	SelectInlineAsmMemoryOperands (std::vector< SDValue > &Ops)
Protected Attributes
unsigned	DAGSize

Detailed Description

SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruction selectors.

Definition at line 42 of file SelectionDAGISel.h.

Member Enumeration Documentation

anonymous enum

Enumerator:

OPFL_None
OPFL_Chain
OPFL_GlueInput
OPFL_GlueOutput
OPFL_MemRefs
OPFL_Variadic0
OPFL_Variadic1
OPFL_Variadic2
OPFL_Variadic3
OPFL_Variadic4
OPFL_Variadic5
OPFL_Variadic6
OPFL_VariadicInfo

Definition at line 150 of file SelectionDAGISel.h.

enum llvm::SelectionDAGISel::BuiltinOpcodes

Enumerator:

OPC_Scope
OPC_RecordNode
OPC_RecordChild0
OPC_RecordChild1
OPC_RecordChild2
OPC_RecordChild3
OPC_RecordChild4
OPC_RecordChild5
OPC_RecordChild6
OPC_RecordChild7
OPC_RecordMemRef
OPC_CaptureGlueInput
OPC_MoveChild
OPC_MoveParent
OPC_CheckSame
OPC_CheckChild0Same
OPC_CheckChild1Same
OPC_CheckChild2Same
OPC_CheckChild3Same
OPC_CheckPatternPredicate
OPC_CheckPredicate
OPC_CheckOpcode
OPC_SwitchOpcode
OPC_CheckType
OPC_SwitchType
OPC_CheckChild0Type
OPC_CheckChild1Type
OPC_CheckChild2Type
OPC_CheckChild3Type
OPC_CheckChild4Type
OPC_CheckChild5Type
OPC_CheckChild6Type
OPC_CheckChild7Type
OPC_CheckInteger
OPC_CheckChild0Integer
OPC_CheckChild1Integer
OPC_CheckChild2Integer
OPC_CheckChild3Integer
OPC_CheckChild4Integer
OPC_CheckCondCode
OPC_CheckValueType
OPC_CheckComplexPat
OPC_CheckAndImm
OPC_CheckOrImm
OPC_CheckFoldableChainNode
OPC_EmitInteger
OPC_EmitRegister
OPC_EmitRegister2
OPC_EmitConvertToTarget
OPC_EmitMergeInputChains
OPC_EmitMergeInputChains1_0
OPC_EmitMergeInputChains1_1
OPC_EmitCopyToReg
OPC_EmitNodeXForm
OPC_EmitNode
OPC_MorphNodeTo
OPC_MarkGlueResults
OPC_CompleteMatch

Definition at line 105 of file SelectionDAGISel.h.

Constructor & Destructor Documentation

SelectionDAGISel::SelectionDAGISel	(	TargetMachine &	tm,
		CodeGenOpt::Level	OL = `CodeGenOpt::Default`
	)		`[explicit]`

Definition at line 336 of file SelectionDAGISel.cpp.

References llvm::PassRegistry::getPassRegistry(), llvm::initializeAliasAnalysisAnalysisGroup(), llvm::initializeBranchProbabilityInfoPass(), llvm::initializeGCModuleInfoPass(), and llvm::initializeTargetLibraryInfoPass().

SelectionDAGISel::~SelectionDAGISel ( ) [virtual]

Definition at line 351 of file SelectionDAGISel.cpp.

References CurDAG, FuncInfo, and SDB.

Member Function Documentation

bool SelectionDAGISel::CheckAndMask	(	SDValue	LHS,
		ConstantSDNode *	RHS,
		int64_t	DesiredMaskS
	)		const

CheckAndMask - The isel is trying to match something like (and X, 255). If the dag combiner simplified the 255, we still want to match. RHS is the actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value specified in the .td file (e.g. 255).

Definition at line 1608 of file SelectionDAGISel.cpp.

References CurDAG, llvm::ConstantSDNode::getAPIntValue(), llvm::SDValue::getValueSizeInBits(), llvm::APInt::intersects(), and llvm::SelectionDAG::MaskedValueIsZero().

Referenced by CheckAndImm().

virtual bool llvm::SelectionDAGISel::CheckComplexPattern	(	SDNode *	Root,
		SDNode *	Parent,
		SDValue	N,
		unsigned	PatternNo,
		SmallVectorImpl< std::pair< SDValue, SDNode * > > &	Result
	)		`[inline, virtual]`

Definition at line 228 of file SelectionDAGISel.h.

References llvm_unreachable.

Referenced by SelectCodeCommon().

virtual bool llvm::SelectionDAGISel::CheckNodePredicate	(	SDNode *	N,
		unsigned	PredNo
	)		const `[inline, virtual]`

CheckNodePredicate - This function is generated by tblgen in the target. It runs node predicate number PredNo and returns true if it succeeds or false if it fails. The number is a private implementation detail to the code tblgen produces.

Definition at line 224 of file SelectionDAGISel.h.

References llvm_unreachable.

Referenced by CheckNodePredicate(), and SelectCodeCommon().

bool SelectionDAGISel::CheckOrMask	(	SDValue	LHS,
		ConstantSDNode *	RHS,
		int64_t	DesiredMaskS
	)		const

CheckOrMask - The isel is trying to match something like (or X, 255). If the dag combiner simplified the 255, we still want to match. RHS is the actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value specified in the .td file (e.g. 255).

Definition at line 1637 of file SelectionDAGISel.cpp.

References llvm::SelectionDAG::computeKnownBits(), CurDAG, llvm::ConstantSDNode::getAPIntValue(), llvm::SDValue::getValueSizeInBits(), and llvm::APInt::intersects().

Referenced by CheckOrImm().

virtual bool llvm::SelectionDAGISel::CheckPatternPredicate ( unsigned PredNo ) const [inline, virtual]

CheckPatternPredicate - This function is generated by tblgen in the target. It runs the specified pattern predicate and returns true if it succeeds or false if it fails. The number is a private implementation detail to the code tblgen produces.

Definition at line 216 of file SelectionDAGISel.h.

References llvm_unreachable.

Referenced by CheckPatternPredicate(), and SelectCodeCommon().

virtual void llvm::SelectionDAGISel::EmitFunctionEntryCode ( ) [inline, virtual]

Definition at line 68 of file SelectionDAGISel.h.

void SelectionDAGISel::getAnalysisUsage ( AnalysisUsage & AU ) const [override, virtual]

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

For MachineFunctionPasses, calling AU.preservesCFG() indicates that the pass does not modify the MachineBasicBlock CFG.

Reimplemented from llvm::MachineFunctionPass.

Definition at line 357 of file SelectionDAGISel.cpp.

References llvm::AnalysisUsage::addPreserved(), llvm::AnalysisUsage::addRequired(), llvm::CodeGenOpt::None, OptLevel, and UseMBPI.

static int llvm::SelectionDAGISel::getNumFixedFromVariadicInfo ( unsigned Flags ) [inline, static]

getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the number of fixed arity values that should be skipped when copying from the root.

Definition at line 170 of file SelectionDAGISel.h.

References OPFL_VariadicInfo.

Referenced by SelectCodeCommon().

const TargetLowering* llvm::SelectionDAGISel::getTargetLowering ( ) const [inline]

Definition at line 60 of file SelectionDAGISel.h.

References llvm::TargetMachine::getSubtargetImpl(), llvm::TargetSubtargetInfo::getTargetLowering(), and TM.

Referenced by llvm::createDefaultScheduler(), llvm::createHybridListDAGScheduler(), llvm::createILPListDAGScheduler(), llvm::MipsDAGToDAGISel::getGlobalBaseReg(), IsPredicateKnownToFail(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), and SelectCodeCommon().

bool SelectionDAGISel::IsLegalToFold	(	SDValue	N,
		SDNode *	U,
		SDNode *	Root,
		CodeGenOpt::Level	OptLevel,
		bool	IgnoreChains = `false`
	)		`[static]`

IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction selection that starts at Root. FIXME: This is a static member function because the MSP430/X86 targets, which uses it during isel. This could become a proper member.

IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction selection that starts at Root.

Definition at line 1779 of file SelectionDAGISel.cpp.

References findGlueUse(), findNonImmUse(), llvm::SDValue::getNode(), llvm::SDNode::getNumValues(), llvm::SDNode::getValueType(), llvm::MVT::Glue, and llvm::CodeGenOpt::None.

Referenced by SelectCodeCommon().

bool SelectionDAGISel::IsProfitableToFold	(	SDValue	N,
		SDNode *	U,
		SDNode *	Root
	)		const `[virtual]`

IsProfitableToFold - Returns true if it's profitable to fold the specific operand node N of U during instruction selection that starts at Root.

Definition at line 1771 of file SelectionDAGISel.cpp.

References llvm::SDValue::hasOneUse(), llvm::CodeGenOpt::None, and OptLevel.

Referenced by SelectCodeCommon().

virtual void llvm::SelectionDAGISel::PostprocessISelDAG ( ) [inline, virtual]

PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.

Definition at line 76 of file SelectionDAGISel.h.

virtual void llvm::SelectionDAGISel::PreprocessISelDAG ( ) [inline, virtual]

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts.

Definition at line 72 of file SelectionDAGISel.h.

void llvm::SelectionDAGISel::ReplaceUses	(	SDValue	F,
		SDValue	T
	)		`[inline, protected]`

ReplaceUses - replace all uses of the old node F with the use of the new node T.

Definition at line 182 of file SelectionDAGISel.h.

References CurDAG, and llvm::SelectionDAG::ReplaceAllUsesOfValueWith().

void llvm::SelectionDAGISel::ReplaceUses	(	const SDValue *	F,
		const SDValue *	T,
		unsigned	Num
	)		`[inline, protected]`

ReplaceUses - replace all uses of the old nodes F with the use of the new nodes T.

Definition at line 188 of file SelectionDAGISel.h.

References CurDAG, and llvm::SelectionDAG::ReplaceAllUsesOfValuesWith().

void llvm::SelectionDAGISel::ReplaceUses	(	SDNode *	F,
		SDNode *	T
	)		`[inline, protected]`

ReplaceUses - replace all uses of the old node F with the use of the new node T.

Definition at line 194 of file SelectionDAGISel.h.

References CurDAG, and llvm::SelectionDAG::ReplaceAllUsesWith().

bool SelectionDAGISel::runOnMachineFunction ( MachineFunction & MF ) [override, virtual]

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformation or analysis.

Implements llvm::MachineFunctionPass.

Reimplemented in llvm::MipsDAGToDAGISel.

Definition at line 406 of file SelectionDAGISel.cpp.

References AA, llvm::FunctionLoweringInfo::ArgDbgValues, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT >::begin(), llvm::MachineBasicBlock::begin(), llvm::MachineFunction::begin(), llvm::FunctionLoweringInfo::BPI, llvm::BuildMI(), llvm::Function::callsFunctionThatReturnsTwice(), llvm::FunctionLoweringInfo::clear(), llvm::MachineRegisterInfo::constrainRegClass(), CurDAG, llvm::TargetOpcode::DBG_VALUE, llvm::dbgs(), DEBUG, llvm::tgtok::Def, llvm::MachineRegisterInfo::EmitLiveInCopies(), llvm::SmallVectorBase::empty(), llvm::TargetOptions::EnableFastISel, EnableFastISelAbort, EnableFastISelVerbose, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT >::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT >::find(), llvm::MachineRegisterInfo::freezeReservedRegs(), FuncInfo, llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineFunction::getFrameInfo(), llvm::TargetRegisterInfo::getFrameRegister(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::Value::getName(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::TargetMachine::getSubtargetImpl(), llvm::TargetSubtargetInfo::getTargetLowering(), llvm::MachineRegisterInfo::getVRegDef(), GFI, llvm::MachineFrameInfo::hasCalls(), llvm::Function::hasFnAttribute(), llvm::Function::hasGC(), I, llvm::SelectionDAG::init(), llvm::SelectionDAGBuilder::init(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT >::insert(), llvm::MachineBasicBlock::insert(), llvm::MachineBasicBlock::insertAfter(), llvm::MCInstrDesc::isCall(), llvm::MachineInstr::isCopy(), llvm::MachineInstr::isDebugValue(), llvm::MachineOperand::isFI(), llvm::MachineInstr::isIndirectDebugValue(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MCInstrDesc::isReturn(), llvm::TargetRegisterInfo::isVirtualRegister(), LI, LibInfo, llvm::MachineRegisterInfo::livein_begin(), llvm::MachineRegisterInfo::livein_end(), MF, llvm::AArch64CC::MI, llvm::CodeGenOpt::None, llvm::Attribute::OptimizeNone, llvm::TargetMachine::Options, OptLevel, llvm::FunctionLoweringInfo::RegFixups, RegInfo, llvm::MachineRegisterInfo::replaceRegWith(), llvm::TargetMachine::resetTargetOptions(), SDB, llvm::FunctionLoweringInfo::set(), llvm::MachineFrameInfo::setHasCalls(), llvm::MachineFunction::setHasInlineAsm(), llvm::SmallVectorTemplateCommon< T, typename >::size(), SplitCriticalSideEffectEdges(), TII, TM, llvm::MachineRegisterInfo::use_instr_begin(), llvm::MachineRegisterInfo::use_instr_end(), UseMBPI, and llvm::TargetRegisterInfo::virtReg2Index().

virtual SDValue llvm::SelectionDAGISel::RunSDNodeXForm	(	SDValue	V,
		unsigned	XFormNo
	)		`[inline, virtual]`

Definition at line 234 of file SelectionDAGISel.h.

References llvm_unreachable.

Referenced by SelectCodeCommon().

virtual SDNode* llvm::SelectionDAGISel::Select ( SDNode * N ) [pure virtual]

Select - Main hook targets implement to select a node.

SDNode * SelectionDAGISel::SelectCodeCommon	(	SDNode *	NodeToMatch,
		const unsigned char *	MatcherTable,
		unsigned	TableSize
	)

Definition at line 2441 of file SelectionDAGISel.cpp.

virtual bool llvm::SelectionDAGISel::SelectInlineAsmMemoryOperand	(	const SDValue &	Op,
		char	ConstraintCode,
		std::vector< SDValue > &	OutOps
	)		`[inline, virtual]`

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint code. If this does not match or is not implemented, return true. The resultant operands (which will appear in the machine instruction) should be added to the OutOps vector.

Definition at line 86 of file SelectionDAGISel.h.

Referenced by SelectInlineAsmMemoryOperands().

void SelectionDAGISel::SelectInlineAsmMemoryOperands ( std::vector< SDValue > & Ops ) [protected]

SelectInlineAsmMemoryOperands - Calls to this are automatically generated by tblgen. Others should not call it.

Definition at line 1671 of file SelectionDAGISel.cpp.

References CurDAG, llvm::InlineAsm::getFlagWord(), llvm::InlineAsm::getNumOperandRegisters(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::Glue, llvm::MVT::i32, llvm::InlineAsm::isMemKind(), llvm::InlineAsm::Kind_Mem, llvm::InlineAsm::Op_AsmString, llvm::InlineAsm::Op_ExtraInfo, llvm::InlineAsm::Op_FirstOperand, llvm::InlineAsm::Op_InputChain, llvm::InlineAsm::Op_MDNode, llvm::report_fatal_error(), SelectInlineAsmMemoryOperand(), and std::swap().