#include "ARM.h"#include "ARMBaseInstrInfo.h"#include "ARMBaseRegisterInfo.h"#include "ARMConstantPoolValue.h"#include "ARMFeatures.h"#include "ARMHazardRecognizer.h"#include "ARMMachineFunctionInfo.h"#include "MCTargetDesc/ARMAddressingModes.h"#include "llvm/ADT/STLExtras.h"#include "llvm/CodeGen/LiveVariables.h"#include "llvm/CodeGen/MachineConstantPool.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineJumpTableInfo.h"#include "llvm/CodeGen/MachineMemOperand.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/SelectionDAGNodes.h"#include "llvm/IR/Constants.h"#include "llvm/IR/Function.h"#include "llvm/IR/GlobalValue.h"#include "llvm/MC/MCAsmInfo.h"#include "llvm/MC/MCExpr.h"#include "llvm/Support/BranchProbability.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "ARMGenInstrInfo.inc"
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Define Documentation
| #define DEBUG_TYPE "arm-instrinfo" |
Definition at line 43 of file ARMBaseInstrInfo.cpp.
| #define GET_INSTRINFO_CTOR_DTOR |
Definition at line 45 of file ARMBaseInstrInfo.cpp.
Enumeration Type Documentation
| enum ARMExeDomain |
Definition at line 4052 of file ARMBaseInstrInfo.cpp.
Function Documentation
| static int adjustDefLatency | ( | const ARMSubtarget & | Subtarget, |
| const MachineInstr * | DefMI, | ||
| const MCInstrDesc * | DefMCID, | ||
| unsigned | DefAlign | ||
| ) | [static] |
Return the number of cycles to add to (or subtract from) the static itinerary based on the def opcode and alignment. The caller will ensure that adjusted latency is at least one cycle.
Definition at line 3373 of file ARMBaseInstrInfo.cpp.
References llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Op(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getOpcode(), llvm::MachineInstr::getOperand(), llvm::ARMSubtarget::isCortexA7(), llvm::ARMSubtarget::isCortexA8(), llvm::ARMSubtarget::isLikeA9(), llvm::ARMSubtarget::isSwift(), llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, and llvm::ARM_AM::sub.
Referenced by llvm::ARMBaseInstrInfo::getOperandLatency().
| static MachineInstr* canFoldIntoMOVCC | ( | unsigned | Reg, |
| const MachineRegisterInfo & | MRI, | ||
| const TargetInstrInfo * | TII | ||
| ) | [static] |
Identify instructions that can be folded into a MOVCC instruction, and return the defining instruction.
Definition at line 1740 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MachineOperand::isCPI(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isJTI(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineInstr::isPredicable(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isSafeToMove(), llvm::MachineOperand::isTied(), llvm::TargetRegisterInfo::isVirtualRegister(), and llvm::AArch64CC::MI.
Referenced by llvm::ARMBaseInstrInfo::optimizeSelect().
| static unsigned duplicateCPV | ( | MachineFunction & | MF, |
| unsigned & | CPI | ||
| ) | [static] |
Create a copy of a const pool value. Update CPI to the new index and return the label UID.
Definition at line 1303 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCP::CPBlockAddress, llvm::ARMCP::CPLSDA, llvm::ARMCP::CPValue, llvm::ARMConstantPoolConstant::Create(), llvm::ARMFunctionInfo::createPICLabelUId(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::MachineConstantPool::getConstants(), llvm::Function::getContext(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), and llvm_unreachable.
Referenced by llvm::ARMBaseInstrInfo::duplicate(), and llvm::ARMBaseInstrInfo::reMaterialize().
| static const MachineInstr* getBundledDefMI | ( | const TargetRegisterInfo * | TRI, |
| const MachineInstr * | MI, | ||
| unsigned | Reg, | ||
| unsigned & | DefIdx, | ||
| unsigned & | Dist | ||
| ) | [static] |
Definition at line 3318 of file ARMBaseInstrInfo.cpp.
References I, and llvm::AArch64CC::MI.
Referenced by llvm::ARMBaseInstrInfo::getOperandLatency().
| static const MachineInstr* getBundledUseMI | ( | const TargetRegisterInfo * | TRI, |
| const MachineInstr * | MI, | ||
| unsigned | Reg, | ||
| unsigned & | UseIdx, | ||
| unsigned & | Dist | ||
| ) | [static] |
Definition at line 3341 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::instr_end(), and llvm::AArch64CC::MI.
Referenced by llvm::ARMBaseInstrInfo::getOperandLatency().
| static unsigned getCorrespondingDRegAndLane | ( | const TargetRegisterInfo * | TRI, |
| unsigned | SReg, | ||
| unsigned & | Lane | ||
| ) | [static] |
Definition at line 4092 of file ARMBaseInstrInfo.cpp.
References llvm::TargetRegisterInfo::getMatchingSuperReg().
Referenced by llvm::ARMBaseInstrInfo::setExecutionDomain().
| static bool getImplicitSPRUseForDPRUse | ( | const TargetRegisterInfo * | TRI, |
| MachineInstr * | MI, | ||
| unsigned | DReg, | ||
| unsigned | Lane, | ||
| unsigned & | ImplicitSReg | ||
| ) | [static] |
getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane, set ImplicitSReg to a register number that must be marked as implicit-use or zero if no register needs to be defined as implicit-use.
If the function cannot determine if an SPR should be marked implicit use or not, it returns false.
This function handles cases where an instruction is being modified from taking an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other lane of the DPR).
If the other SPR is defined, an implicit-use of it should be added. Else, (including the case where the DPR itself is defined), it should not.
Definition at line 4122 of file ARMBaseInstrInfo.cpp.
References llvm::MachineBasicBlock::computeRegisterLiveness(), llvm::MachineInstr::definesRegister(), llvm::MachineInstr::getParent(), llvm::MCRegisterInfo::getSubReg(), llvm::MachineBasicBlock::LQR_Live, llvm::MachineBasicBlock::LQR_Unknown, and llvm::MachineInstr::readsRegister().
Referenced by llvm::ARMBaseInstrInfo::setExecutionDomain().
| static unsigned getNumJTEntries | ( | const std::vector< MachineJumpTableEntry > & | JT, |
| unsigned | JTI | ||
| ) | [static] |
FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
Definition at line 601 of file ARMBaseInstrInfo.cpp.
Referenced by llvm::ARMBaseInstrInfo::GetInstSizeInBytes().
| static unsigned getNumMicroOpsSwiftLdSt | ( | const InstrItineraryData * | ItinData, |
| const MachineInstr * | MI | ||
| ) | [static] |
Definition at line 2663 of file ARMBaseInstrInfo.cpp.
References llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Op(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::ARM_AM::getAM3Op(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::InstrItineraryData::getNumMicroOps(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MCInstrDesc::getSchedClass(), llvm::ARM_AM::lsl, and llvm::ARM_AM::sub.
Referenced by llvm::ARMBaseInstrInfo::getNumMicroOps().
| static ARMCC::CondCodes getSwappedCondition | ( | ARMCC::CondCodes | CC | ) | [inline, static] |
getSwappedCondition - assume the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a).
Definition at line 2260 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, and llvm::ARMCC::NE.
Referenced by llvm::ARMBaseInstrInfo::optimizeCompareInstr().
| static bool isAnySubRegLive | ( | unsigned | Reg, |
| const TargetRegisterInfo * | TRI, | ||
| MachineInstr * | MI | ||
| ) | [static] |
Definition at line 1933 of file ARMBaseInstrInfo.cpp.
References llvm::MachineBasicBlock::computeRegisterLiveness(), llvm::MachineInstr::getParent(), llvm::MCRegisterInfo::DiffListIterator::isValid(), and llvm::MachineBasicBlock::LQR_Dead.
Referenced by llvm::tryFoldSPUpdateIntoPushPop().
| static bool isCPSRDefined | ( | const MachineInstr * | MI | ) | [static] |
Definition at line 521 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstr::operands().
Referenced by isEligibleForITBlock().
| static bool isEligibleForITBlock | ( | const MachineInstr * | MI | ) | [static] |
Definition at line 528 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and isCPSRDefined().
Referenced by llvm::ARMBaseInstrInfo::isPredicable().
| static bool isRedundantFlagInstr | ( | MachineInstr * | CmpI, |
| unsigned | SrcReg, | ||
| unsigned | SrcReg2, | ||
| int | ImmValue, | ||
| MachineInstr * | OI | ||
| ) | [inline, static] |
isRedundantFlagInstr - check whether the first instruction, whose only purpose is to update flags, can be made redundant. CMPrr can be made redundant by SUBrr if the operands are the same. CMPri can be made redundant by SUBri if the operands are the same. This function can be extended later on.
Definition at line 2281 of file ARMBaseInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
Referenced by llvm::ARMBaseInstrInfo::optimizeCompareInstr().
| static bool isSuitableForMask | ( | MachineInstr *& | MI, |
| unsigned | SrcReg, | ||
| int | CmpMask, | ||
| bool | CommonUse | ||
| ) | [static] |
isSuitableForMask - Identify a suitable 'and' instruction that operates on the given source register and applies the same mask as a 'tst' instruction. Provide a limited look-through for copies. When successful, MI will hold the found instruction.
Definition at line 2232 of file ARMBaseInstrInfo.cpp.
References AND, llvm::TargetOpcode::COPY, llvm::MachineBasicBlock::end(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), and llvm::AArch64CC::MI.
Referenced by llvm::ARMBaseInstrInfo::optimizeCompareInstr().
Variable Documentation
const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] [static] |
{
{ARM::ADDSri, ARM::ADDri},
{ARM::ADDSrr, ARM::ADDrr},
{ARM::ADDSrsi, ARM::ADDrsi},
{ARM::ADDSrsr, ARM::ADDrsr},
{ARM::SUBSri, ARM::SUBri},
{ARM::SUBSrr, ARM::SUBrr},
{ARM::SUBSrsi, ARM::SUBrsi},
{ARM::SUBSrsr, ARM::SUBrsr},
{ARM::RSBSri, ARM::RSBri},
{ARM::RSBSrsi, ARM::RSBrsi},
{ARM::RSBSrsr, ARM::RSBrsr},
{ARM::t2ADDSri, ARM::t2ADDri},
{ARM::t2ADDSrr, ARM::t2ADDrr},
{ARM::t2ADDSrs, ARM::t2ADDrs},
{ARM::t2SUBSri, ARM::t2SUBri},
{ARM::t2SUBSrr, ARM::t2SUBrr},
{ARM::t2SUBSrs, ARM::t2SUBrs},
{ARM::t2RSBSri, ARM::t2RSBri},
{ARM::t2RSBSrs, ARM::t2RSBrs},
}
Definition at line 1863 of file ARMBaseInstrInfo.cpp.
Referenced by llvm::convertAddSubFlagsOpcode().
const ARM_MLxEntry ARM_MLxTable[] [static] |
{
{ ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
{ ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
{ ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
{ ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
{ ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
{ ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
{ ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
{ ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
{ ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
{ ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
{ ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
{ ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
{ ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
{ ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
{ ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
{ ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
}
Definition at line 70 of file ARMBaseInstrInfo.cpp.
Referenced by llvm::ARMBaseInstrInfo::ARMBaseInstrInfo(), and llvm::ARMBaseInstrInfo::isFpMLxInstruction().
cl::opt<bool> EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, cl::desc("Enable ARM 2-addr to 3-addr conv")) [static] |
Referenced by llvm::ARMBaseInstrInfo::convertToThreeAddress().
cl::opt<unsigned> SwiftPartialUpdateClearance("swift-partial-update-clearance", cl::Hidden, cl::init(12), cl::desc("Clearance before partial register updates")) [static] |
Referenced by llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance().
cl::opt<bool> WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true), cl::desc("Widen ARM vmovs to vmovd when possible")) [static] |
Referenced by llvm::ARMBaseInstrInfo::expandPostRAPseudo().
1.7.6.1