SelectionDAGBuilder.cpp File Reference

#include "SelectionDAGBuilder.h"
#include "SDNodeDbgValue.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/Optional.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/BranchProbabilityInfo.h"
#include "llvm/Analysis/ConstantFolding.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/FastISel.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/GCMetadata.h"
#include "llvm/CodeGen/GCStrategy.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugInfo.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalVariable.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/IR/Module.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetSelectionDAGInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include "llvm/IR/Instruction.def"
#include "llvm/CodeGen/SelectionDAGISel.h"

Go to the source code of this file.

Defines
#define	DEBUG_TYPE   "isel"
#define	HANDLE_INST(NUM, OPCODE, CLASS)   case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
Functions
static SDValue	getCopyFromPartsVector (SelectionDAG &DAG, SDLoc DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V)
static SDValue	getCopyFromParts (SelectionDAG &DAG, SDLoc DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, ISD::NodeType AssertOp=ISD::DELETED_NODE)
static void	diagnosePossiblyInvalidConstraint (LLVMContext &Ctx, const Value *V, const Twine &ErrMsg)
static void	getCopyToPartsVector (SelectionDAG &DAG, SDLoc dl, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V)
static void	getCopyToParts (SelectionDAG &DAG, SDLoc DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V, ISD::NodeType ExtendKind=ISD::ANY_EXTEND)
static bool	InBlock (const Value *V, const BasicBlock *BB)
static void	ScaleWeights (uint64_t &NewTrue, uint64_t &NewFalse)
	Scale down both weights to fit into uint32_t.
static bool	areJTsAllowed (const TargetLowering &TLI)
static APInt	ComputeRange (const APInt &First, const APInt &Last)
static bool	isSequentialInRange (const SmallVectorImpl< int > &Mask, unsigned Pos, unsigned Size, int Low)
static SDValue	InsertFenceForAtomic (SDValue Chain, AtomicOrdering Order, SynchronizationScope Scope, bool Before, SDLoc dl, SelectionDAG &DAG, const TargetLowering &TLI)
static SDValue	GetSignificand (SelectionDAG &DAG, SDValue Op, SDLoc dl)
static SDValue	GetExponent (SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, SDLoc dl)
static SDValue	getF32Constant (SelectionDAG &DAG, unsigned Flt)
	getF32Constant - Get 32-bit floating point constant.
static SDValue	expandExp (SDLoc dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI)
static SDValue	expandLog (SDLoc dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI)
static SDValue	expandLog2 (SDLoc dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI)
static SDValue	expandLog10 (SDLoc dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI)
static SDValue	expandExp2 (SDLoc dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI)
static SDValue	expandPow (SDLoc dl, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const TargetLowering &TLI)
static SDValue	ExpandPowI (SDLoc DL, SDValue LHS, SDValue RHS, SelectionDAG &DAG)
	ExpandPowI - Expand a llvm.powi intrinsic.
static unsigned	getTruncatedArgReg (const SDValue &N)
static bool	IsOnlyUsedInZeroEqualityComparison (const Value *V)
static SDValue	getMemCmpLoad (const Value *PtrVal, MVT LoadVT, Type *LoadTy, SelectionDAGBuilder &Builder)
static void	GetRegistersForValue (SelectionDAG &DAG, const TargetLowering &TLI, SDLoc DL, SDISelAsmOperandInfo &OpInfo)
static void	addStackMapLiveVars (const CallInst &CI, unsigned StartIdx, SmallVectorImpl< SDValue > &Ops, SelectionDAGBuilder &Builder)
	Add a stack map intrinsic call's live variable operands to a stackmap or patchpoint target node's operand list.
static AttributeSet	getReturnAttrs (TargetLowering::CallLoweringInfo &CLI)
static bool	isOnlyUsedInEntryBlock (const Argument *A, bool FastISel)
Variables
static unsigned	LimitFloatPrecision
static cl::opt< unsigned, true >	LimitFPPrecision ("limit-float-precision", cl::desc("Generate low-precision inline sequences ""for some float libcalls"), cl::location(LimitFloatPrecision), cl::init(0))
static const unsigned	MaxParallelChains = 64

---

Define Documentation

#define DEBUG_TYPE   "isel"

Definition at line 65 of file SelectionDAGBuilder.cpp.

#define HANDLE_INST	(		NUM,
			OPCODE,
			CLASS
	)		case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;

---

Function Documentation

static void addStackMapLiveVars	(	const CallInst &	CI,
		unsigned	StartIdx,
		SmallVectorImpl< SDValue > &	Ops,
		SelectionDAGBuilder &	Builder
	)		[static]

Add a stack map intrinsic call's live variable operands to a stackmap or patchpoint target node's operand list.

Constants are converted to TargetConstants purely as an optimization to avoid constant materialization and register allocation.

FrameIndex operands are converted to TargetFrameIndex so that ISEL does not generate addess computation nodes, and so ExpandISelPseudo can convert the TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids address materialization and register allocation, but may also be required for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an alloca in the entry block, then the runtime may assume that the alloca's StackMap location can be read immediately after compilation and that the location is valid at any point during execution (this is similar to the assumption made by the llvm.gcroot intrinsic). If the alloca's location were only available in a register, then the runtime would need to trap when execution reaches the StackMap in order to read the alloca's location.

Definition at line 6907 of file SelectionDAGBuilder.cpp.

References llvm::StackMaps::ConstantOp, llvm::SelectionDAGBuilder::DAG, llvm::CallInst::getArgOperand(), llvm::CallInst::getNumArgOperands(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAGBuilder::getValue(), llvm::MVT::i64, and llvm::SmallVectorTemplateBase< T, isPodLike >::push_back().

static bool areJTsAllowed

(

const TargetLowering &

TLI

)

[inline, static]

Definition at line 2232 of file SelectionDAGBuilder.cpp.

References llvm::ISD::BR_JT, llvm::ISD::BRIND, llvm::TargetLoweringBase::isOperationLegalOrCustom(), and llvm::MVT::Other.

static APInt ComputeRange	(	const APInt &	First,
		const APInt &	Last
	)		[static]

Definition at line 2237 of file SelectionDAGBuilder.cpp.

References llvm::APInt::getBitWidth(), and llvm::APInt::sext().

static void diagnosePossiblyInvalidConstraint	(	LLVMContext &	Ctx,
		const Value *	V,
		const Twine &	ErrMsg
	)		[static]

Definition at line 219 of file SelectionDAGBuilder.cpp.

References llvm::LLVMContext::emitError(), and I.

Referenced by getCopyFromPartsVector(), and getCopyToParts().

static SDValue expandExp	(	SDLoc	dl,
		SDValue	Op,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI
	)		[static]

expandExp - Lower an exp intrinsic. Handles the special sequences for limited-precision mode.

Definition at line 3938 of file SelectionDAGBuilder.cpp.

References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::MVT::f32, llvm::ISD::FADD, llvm::ISD::FEXP, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::ISD::FSUB, llvm::SelectionDAG::getConstant(), getF32Constant(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SDValue::getValueType(), llvm::MVT::i32, LimitFloatPrecision, llvm::ISD::SHL, llvm::ISD::SINT_TO_FP, and llvm::X.

static SDValue expandExp2	(	SDLoc	dl,
		SDValue	Op,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI
	)		[static]

expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for limited-precision mode.

Definition at line 4320 of file SelectionDAGBuilder.cpp.

References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::MVT::f32, llvm::ISD::FADD, llvm::ISD::FEXP2, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::ISD::FSUB, llvm::SelectionDAG::getConstant(), getF32Constant(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SDValue::getValueType(), llvm::MVT::i32, LimitFloatPrecision, llvm::ISD::SHL, llvm::ISD::SINT_TO_FP, and llvm::X.

static SDValue expandLog	(	SDLoc	dl,
		SDValue	Op,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI
	)		[static]

expandLog - Lower a log intrinsic. Handles the special sequences for limited-precision mode.

Definition at line 4041 of file SelectionDAGBuilder.cpp.

References llvm::ISD::BITCAST, llvm::MVT::f32, llvm::ISD::FADD, llvm::ISD::FLOG, llvm::ISD::FMUL, llvm::ISD::FSUB, GetExponent(), getF32Constant(), llvm::SelectionDAG::getNode(), GetSignificand(), llvm::SDValue::getValueType(), llvm::MVT::i32, LimitFloatPrecision, and llvm::X.

static SDValue expandLog10	(	SDLoc	dl,
		SDValue	Op,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI
	)		[static]

expandLog10 - Lower a log10 intrinsic. Handles the special sequences for limited-precision mode.

Definition at line 4232 of file SelectionDAGBuilder.cpp.

References llvm::ISD::BITCAST, llvm::MVT::f32, llvm::ISD::FADD, llvm::ISD::FLOG10, llvm::ISD::FMUL, llvm::ISD::FSUB, GetExponent(), getF32Constant(), llvm::SelectionDAG::getNode(), GetSignificand(), llvm::SDValue::getValueType(), llvm::MVT::i32, LimitFloatPrecision, and llvm::X.

static SDValue expandLog2	(	SDLoc	dl,
		SDValue	Op,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI
	)		[static]

expandLog2 - Lower a log2 intrinsic. Handles the special sequences for limited-precision mode.

Definition at line 4137 of file SelectionDAGBuilder.cpp.

References llvm::ISD::BITCAST, llvm::MVT::f32, llvm::ISD::FADD, llvm::ISD::FLOG2, llvm::ISD::FMUL, llvm::ISD::FSUB, GetExponent(), getF32Constant(), llvm::SelectionDAG::getNode(), GetSignificand(), llvm::SDValue::getValueType(), llvm::MVT::i32, LimitFloatPrecision, and llvm::X.

static SDValue expandPow	(	SDLoc	dl,
		SDValue	LHS,
		SDValue	RHS,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI
	)		[static]

visitPow - Lower a pow intrinsic. Handles the special sequences for limited-precision mode with x == 10.0f.

Definition at line 4415 of file SelectionDAGBuilder.cpp.

References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::MVT::f32, llvm::ISD::FADD, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::ISD::FPOW, llvm::ISD::FSUB, llvm::SelectionDAG::getConstant(), getF32Constant(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SDValue::getValueType(), llvm::MVT::i32, LimitFloatPrecision, llvm::ISD::SHL, llvm::ISD::SINT_TO_FP, and llvm::X.

static SDValue ExpandPowI	(	SDLoc	DL,
		SDValue	LHS,
		SDValue	RHS,
		SelectionDAG &	DAG
	)		[static]

ExpandPowI - Expand a llvm.powi intrinsic.

Definition at line 4523 of file SelectionDAGBuilder.cpp.

References llvm::CountPopulation_32(), llvm::ISD::FDIV, llvm::ISD::FMUL, llvm::ISD::FPOWI, llvm::AttributeSet::FunctionIndex, llvm::Function::getAttributes(), llvm::SelectionDAG::getConstantFP(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::AttributeSet::hasAttribute(), llvm::Log2_32(), and llvm::Attribute::OptimizeForSize.

static SDValue getCopyFromParts	(	SelectionDAG &	DAG,
		SDLoc	DL,
		const SDValue *	Parts,
		unsigned	NumParts,
		MVT	PartVT,
		EVT	ValueVT,
		const Value *	V,
		ISD::NodeType	AssertOp = ISD::DELETED_NODE
	)		[static]

getCopyFromParts - Create a value that contains the specified legal parts combined into the value they represent. If the parts combine to a type larger then ValueVT then AssertOp can be used to specify whether the extra bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT (ISD::AssertSext).

Definition at line 103 of file SelectionDAGBuilder.cpp.

References llvm::ISD::ANY_EXTEND, llvm::ISD::BITCAST, llvm::EVT::bitsLT(), llvm::ISD::BUILD_PAIR, llvm::ISD::DELETED_NODE, llvm::MVT::f64, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), getCopyFromPartsVector(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::TargetLoweringBase::hasBigEndianPartOrdering(), llvm::HexagonISD::Hi, llvm::TargetLoweringBase::isBigEndian(), llvm::EVT::isFloatingPoint(), llvm::MVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::MVT::isInteger(), llvm::EVT::isVector(), llvm::MVT::isVector(), llvm_unreachable, llvm::HexagonISD::Lo, llvm::Log2_32(), llvm::ISD::OR, llvm::MVT::ppcf128, llvm::ISD::SHL, std::swap(), llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

Referenced by getCopyFromPartsVector(), and llvm::TargetLowering::LowerCallTo().

static SDValue getCopyFromPartsVector	(	SelectionDAG &	DAG,
		SDLoc	DL,
		const SDValue *	Parts,
		unsigned	NumParts,
		MVT	PartVT,
		EVT	ValueVT,
		const Value *	V
	)		[static]

getCopyFromPartsVector - Create a value that contains the specified legal parts combined into the value they represent. If the parts combine to a type larger then ValueVT then AssertOp can be used to specify whether the extra bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT (ISD::AssertSext).

Definition at line 238 of file SelectionDAGBuilder.cpp.

References llvm::ISD::ANY_EXTEND, llvm::ISD::BITCAST, llvm::EVT::bitsLE(), llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, diagnosePossiblyInvalidConstraint(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), getCopyFromParts(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::TargetLoweringBase::getVectorIdxTy(), llvm::EVT::getVectorNumElements(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), and llvm::ISD::TRUNCATE.

Referenced by getCopyFromParts().

static void getCopyToParts	(	SelectionDAG &	DAG,
		SDLoc	DL,
		SDValue	Val,
		SDValue *	Parts,
		unsigned	NumParts,
		MVT	PartVT,
		const Value *	V,
		ISD::NodeType	ExtendKind = ISD::ANY_EXTEND
	)		[static]

getCopyToParts - Create a series of nodes that contain the specified value split into legal parts. If the parts contain more bits than Val, then, for integers, ExtendKind can be used to specify how to generate the extra bits.

Definition at line 347 of file SelectionDAGBuilder.cpp.

References llvm::ISD::BITCAST, diagnosePossiblyInvalidConstraint(), llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getContext(), getCopyToPartsVector(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::TargetLoweringBase::isBigEndian(), llvm::EVT::isFloatingPoint(), llvm::MVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::MVT::isInteger(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::Log2_32(), llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::MVT::x86mmx.

Referenced by getCopyToPartsVector(), and llvm::TargetLowering::LowerCallTo().

static void getCopyToPartsVector	(	SelectionDAG &	DAG,
		SDLoc	DL,
		SDValue	Val,
		SDValue *	Parts,
		unsigned	NumParts,
		MVT	PartVT,
		const Value *	V
	)		[static]

getCopyToPartsVector - Create a series of nodes that contain the specified value split into legal parts.

Definition at line 470 of file SelectionDAGBuilder.cpp.

References llvm::ISD::ANY_EXTEND, llvm::ISD::BITCAST, llvm::EVT::bitsGE(), llvm::EVT::bitsLE(), llvm::ISD::BUILD_VECTOR, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), getCopyToParts(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorNumElements(), llvm::EVT::isVector(), llvm::MVT::isVector(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and llvm::ISD::TRUNCATE.

Referenced by getCopyToParts().

static SDValue GetExponent	(	SelectionDAG &	DAG,
		SDValue	Op,
		const TargetLowering &	TLI,
		SDLoc	dl
	)		[static]

GetExponent - Get the exponent:

(float)(int)(((Op & 0x7f800000) >> 23) - 127);

where Op is the hexadecimal representation of floating point value.

Definition at line 3918 of file SelectionDAGBuilder.cpp.

References llvm::ISD::AND, llvm::MVT::f32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::MVT::i32, llvm::ISD::SINT_TO_FP, llvm::ISD::SRL, and llvm::ISD::SUB.

Referenced by expandLog(), expandLog10(), and expandLog2().

static SDValue getF32Constant	(	SelectionDAG &	DAG,
		unsigned	Flt
	)		[static]

getF32Constant - Get 32-bit floating point constant.

Definition at line 3931 of file SelectionDAGBuilder.cpp.

References llvm::lltok::APFloat, llvm::MVT::f32, llvm::SelectionDAG::getConstantFP(), and llvm::APFloat::IEEEsingle.

Referenced by expandExp(), expandExp2(), expandLog(), expandLog10(), expandLog2(), and expandPow().

static SDValue getMemCmpLoad	(	const Value *	PtrVal,
		MVT	LoadVT,
		Type *	LoadTy,
		SelectionDAGBuilder &	Builder
	)		[static]

Definition at line 5625 of file SelectionDAGBuilder.cpp.

References llvm::SelectionDAGBuilder::AA, llvm::ConstantFoldLoadFromConstPtr(), llvm::SelectionDAGBuilder::DAG, llvm::SelectionDAGBuilder::DL, llvm::ConstantExpr::getBitCast(), llvm::SelectionDAGBuilder::getCurSDLoc(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getRoot(), llvm::PointerType::getUnqual(), llvm::SDValue::getValue(), llvm::SelectionDAGBuilder::getValue(), llvm::SelectionDAGBuilder::PendingLoads, llvm::AliasAnalysis::pointsToConstantMemory(), and llvm::SmallVectorTemplateBase< T, isPodLike >::push_back().

static void GetRegistersForValue	(	SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		SDLoc	DL,
		SDISelAsmOperandInfo &	OpInfo
	)		[static]

GetRegistersForValue - Assign registers (virtual or physical) for the specified operand. We prefer to assign virtual registers, to allow the register allocator to handle the assignment process. However, if the asm uses features that we can't model on machineinstrs, we have SDISel do the allocation. This produces generally horrible, but correct, code.

OpInfo describes the operand.

Definition at line 6193 of file SelectionDAGBuilder.cpp.

References llvm::TargetRegisterClass::begin(), llvm::ISD::BITCAST, llvm::MachineRegisterInfo::createVirtualRegister(), llvm::TargetRegisterClass::end(), llvm::SelectionDAG::getContext(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getNumRegisters(), llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::MachineFunction::getRegInfo(), llvm::MVT::getSizeInBits(), I, llvm::InlineAsm::isInput, llvm::MVT::isInteger(), llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), and llvm::TargetRegisterClass::vt_begin().

static AttributeSet getReturnAttrs

(

TargetLowering::CallLoweringInfo &

CLI

)

[static]

Returns an AttributeSet representing the attributes applied to the return value of the given call.

Definition at line 7132 of file SelectionDAGBuilder.cpp.

References llvm::Type::getContext(), llvm::Attribute::InReg, llvm::TargetLowering::CallLoweringInfo::IsInReg, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::TargetLowering::CallLoweringInfo::RetSExt, llvm::TargetLowering::CallLoweringInfo::RetTy, llvm::AttributeSet::ReturnIndex, llvm::TargetLowering::CallLoweringInfo::RetZExt, llvm::Attribute::SExt, and llvm::Attribute::ZExt.

Referenced by llvm::TargetLowering::LowerCallTo().

static SDValue GetSignificand	(	SelectionDAG &	DAG,
		SDValue	Op,
		SDLoc	dl
	)		[static]

GetSignificand - Get the significand and build it into a floating-point number with exponent of 1:

Op = (Op & 0x007fffff) | 0x3f800000;

where Op is the hexadecimal representation of floating point value.

Definition at line 3904 of file SelectionDAGBuilder.cpp.

References llvm::ISD::AND, llvm::ISD::BITCAST, llvm::MVT::f32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, and llvm::ISD::OR.

Referenced by expandLog(), expandLog10(), and expandLog2().

static unsigned getTruncatedArgReg

(

const SDValue &

N

)

[static]

Definition at line 4577 of file SelectionDAGBuilder.cpp.

References llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::CopyFromReg, llvm::MipsISD::Ext, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getReg(), and llvm::ISD::TRUNCATE.

static bool InBlock	(	const Value *	V,
		const BasicBlock *	BB
	)		[static]

Definition at line 1367 of file SelectionDAGBuilder.cpp.

References llvm::Instruction::getParent().

Referenced by llvm::SelectionDAGBuilder::FindMergedConditions().

static SDValue InsertFenceForAtomic	(	SDValue	Chain,
		AtomicOrdering	Order,
		SynchronizationScope	Scope,
		bool	Before,
		SDLoc	dl,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI
	)		[static]

Definition at line 3633 of file SelectionDAGBuilder.cpp.

References llvm::Acquire, llvm::AcquireRelease, llvm::ISD::ATOMIC_FENCE, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::Monotonic, llvm::MVT::Other, llvm::Release, llvm::SequentiallyConsistent, and llvm::Unordered.

static bool isOnlyUsedInEntryBlock	(	const Argument *	A,
		bool	FastISel
	)		[static]

isOnlyUsedInEntryBlock - If the specified argument is only used in the entry block, return true. This includes arguments used by switches, since the switch may expand into multiple basic blocks.

Definition at line 7441 of file SelectionDAGBuilder.cpp.

References llvm::Function::begin(), llvm::Argument::getParent(), llvm::Value::use_empty(), and llvm::Value::users().

static bool IsOnlyUsedInZeroEqualityComparison

(

const Value *

V

)

[static]

IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the value is equal or not-equal to zero.

Definition at line 5612 of file SelectionDAGBuilder.cpp.

References llvm::Constant::isNullValue(), and llvm::Value::users().

static bool isSequentialInRange	(	const SmallVectorImpl< int > &	Mask,
		unsigned	Pos,
		unsigned	Size,
		int	Low
	)		[static]

Definition at line 3100 of file SelectionDAGBuilder.cpp.

static void ScaleWeights	(	uint64_t &	NewTrue,
		uint64_t &	NewFalse
	)		[static]

Scale down both weights to fit into uint32_t.

Definition at line 1422 of file SelectionDAGBuilder.cpp.

Referenced by llvm::SelectionDAGBuilder::FindMergedConditions().

---

Variable Documentation

unsigned LimitFloatPrecision [static]

LimitFloatPrecision - Generate low-precision inline sequences for some float libcalls (6, 8 or 12 bits).

Definition at line 69 of file SelectionDAGBuilder.cpp.

Referenced by expandExp(), expandExp2(), expandLog(), expandLog10(), expandLog2(), and expandPow().

cl::opt<unsigned, true> LimitFPPrecision("limit-float-precision", cl::desc("Generate low-precision inline sequences ""for some float libcalls"), cl::location(LimitFloatPrecision), cl::init(0)) [static]

const unsigned MaxParallelChains = 64 [static]

Definition at line 92 of file SelectionDAGBuilder.cpp.