#include <R600ISelLowering.h>
Public Member Functions | |
| R600TargetLowering (TargetMachine &TM) | |
| MachineBasicBlock * | EmitInstrWithCustomInserter (MachineInstr *MI, MachineBasicBlock *BB) const override |
| SDValue | LowerOperation (SDValue Op, SelectionDAG &DAG) const override |
| SDValue | PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const override |
| void | ReplaceNodeResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override |
| SDValue | LowerFormalArguments (SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override |
| EVT | getSetCCResultType (LLVMContext &, EVT VT) const override |
Detailed Description
Definition at line 24 of file R600ISelLowering.h.
Constructor & Destructor Documentation
Definition at line 33 of file R600ISelLowering.cpp.
References llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::TargetLoweringBase::addRegisterClass(), llvm::ISD::BR_CC, llvm::ISD::BRCOND, llvm::TargetLoweringBase::computeRegisterProperties(), llvm::TargetLoweringBase::Custom, llvm::TargetLoweringBase::Expand, llvm::ISD::EXTLOAD, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::ISD::FCOS, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FrameIndex, llvm::ISD::FSIN, llvm::ISD::FSUB, llvm::ISD::GlobalAddress, llvm::AMDGPUSubtarget::hasBFE(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLoweringBase::Legal, llvm::ISD::LOAD, llvm::MVT::Other, llvm::ISD::SDIV, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::TargetLoweringBase::setBooleanContents(), llvm::TargetLoweringBase::setBooleanVectorContents(), llvm::ISD::SETCC, llvm::TargetLoweringBase::setCondCodeAction(), llvm::ISD::SETLE, llvm::TargetLoweringBase::setLoadExtAction(), llvm::ISD::SETLT, llvm::ISD::SETO, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::TargetLoweringBase::setOperationAction(), llvm::TargetLoweringBase::setSchedulingPreference(), llvm::TargetLoweringBase::setTargetDAGCombine(), llvm::TargetLoweringBase::setTruncStoreAction(), llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUO, llvm::ISD::SEXTLOAD, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND_INREG, llvm::Sched::Source, llvm::ISD::SRA_PARTS, llvm::ISD::SREM, llvm::ISD::SRL_PARTS, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::SUBC, llvm::ISD::SUBE, llvm::AMDGPUTargetLowering::Subtarget, llvm::ISD::UDIV, llvm::ISD::UREM, llvm::MVT::v2f32, llvm::MVT::v2i1, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v2i8, llvm::MVT::v4f32, llvm::MVT::v4i1, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i8, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, and llvm::ISD::ZEXTLOAD.
Member Function Documentation
| MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter | ( | MachineInstr * | MI, |
| MachineBasicBlock * | MBB | ||
| ) | const [override, virtual] |
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag. These instructions are special in various ways, which require special support to insert. The specified MachineInstr is created but not inserted into any basic blocks, and this method is called to expand it into a sequence of instructions, potentially also creating new basic blocks and control flow.
Reimplemented from llvm::TargetLowering.
Definition at line 189 of file R600ISelLowering.cpp.
References llvm::R600InstrInfo::addFlag(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::APFloat::bitcastToAPInt(), llvm::R600InstrInfo::buildDefaultInstruction(), llvm::BuildMI(), llvm::R600InstrInfo::buildMovImm(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::MachineBasicBlock::findDebugLoc(), llvm::MachineOperand::getFPImm(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::AMDGPU::getLDSNoRetOp(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::R600InstrInfo::getOperandIdx(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::ConstantFP::getValueAPF(), llvm::MachineRegisterInfo::getVRegDef(), llvm::APInt::getZExtValue(), I, llvm::RegState::Implicit, llvm::R600InstrInfo::isLDSRetInstr(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::RegState::Kill, llvm::R600MachineFunctionInfo::LiveOuts, llvm::AArch64CC::MI, MO_FLAG_ABS, MO_FLAG_CLAMP, MO_FLAG_MASK, MO_FLAG_NEG, MO_FLAG_PUSH, OPCODE_IS_NOT_ZERO, OPCODE_IS_NOT_ZERO_INT, llvm::NVPTXISD::RETURN, llvm::R600InstrInfo::setImmOperand(), llvm::SmallVectorTemplateCommon< T, typename >::size(), T1, TII, and llvm::MachineRegisterInfo::use_empty().
| EVT R600TargetLowering::getSetCCResultType | ( | LLVMContext & | Context, |
| EVT | VT | ||
| ) | const [override, virtual] |
Return the ValueType of the result of SETCC operations. Also used to obtain the target's preferred type for the condition operand of SELECT and BRCOND nodes. In the case of BRCOND the argument passed is MVT::Other since there are no other operands to get a type hint from.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1765 of file R600ISelLowering.cpp.
References llvm::EVT::changeVectorElementTypeToInteger(), llvm::MVT::i32, and llvm::EVT::isVector().
| SDValue R600TargetLowering::LowerFormalArguments | ( | SDValue | Chain, |
| CallingConv::ID | CallConv, | ||
| bool | isVarArg, | ||
| const SmallVectorImpl< ISD::InputArg > & | Ins, | ||
| SDLoc | DL, | ||
| SelectionDAG & | DAG, | ||
| SmallVectorImpl< SDValue > & | InVals | ||
| ) | const [override, virtual] |
XXX Only kernel functions are supported, so we can assume for now that every function is a kernel function, but in the future we should use separate calling conventions for kernel and non-kernel functions.
Reimplemented from llvm::TargetLowering.
Definition at line 1690 of file R600ISelLowering.cpp.
References llvm::AMDGPUTargetLowering::AnalyzeFormalArguments(), ShaderType::COMPUTE, AMDGPUAS::CONSTANT_BUFFER_0, llvm::MipsISD::Ext, llvm::PointerType::get(), llvm::UndefValue::get(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::AMDGPUTargetLowering::getOriginalFunctionArgs(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getTypeForEVT(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorElementType(), llvm::MVT::i32, llvm::tgtok::In, llvm::MipsISD::Ins, llvm::EVT::isVector(), llvm::ISD::NON_EXTLOAD, llvm::ISD::InputArg::OrigArgIndex, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), Register, llvm::ISD::SEXTLOAD, llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::ISD::UNINDEXED, and llvm::ISD::InputArg::VT.
| SDValue R600TargetLowering::LowerOperation | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const [override, virtual] |
This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal. If the target has no operations that require custom lowering, it need not implement this. The default implementation of this aborts.
Reimplemented from llvm::AMDGPUTargetLowering.
Definition at line 573 of file R600ISelLowering.cpp.
References llvm::MachineRegisterInfo::addLiveIn(), llvm::ISD::BRCOND, llvm::ISD::BUILD_VECTOR, llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::AMDGPUISD::DOT4, llvm::AMDGPUISD::EXPORT, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::ISD::FCOS, llvm::ISD::FSIN, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getEntryNode(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MachineFunction::getRegInfo(), llvm::R600InstrInfo::getRegisterInfo(), llvm::AMDGPURegisterInfo::getSubRegFromChannel(), llvm::MachineFunction::getSubtarget(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SDValue::getValueType(), llvm::ISD::GlobalAddress, llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::R600MachineFunctionInfo::LiveOuts, llvm_unreachable, llvm::ISD::LOAD, llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::AMDGPUISD::RSQ_LEGACY, llvm::ISD::SELECT_CC, llvm::ISD::SHL_PARTS, llvm::ISD::SRA_PARTS, llvm::ISD::SRL_PARTS, llvm::ISD::STORE, llvm::AMDGPUISD::TEXTURE_FETCH, TII, llvm::MVT::v2f32, and llvm::MVT::v4f32.
| SDValue R600TargetLowering::PerformDAGCombine | ( | SDNode * | N, |
| DAGCombinerInfo & | DCI | ||
| ) | const [override, virtual] |
This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.
The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.
In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.
Reimplemented from llvm::AMDGPUTargetLowering.
Definition at line 1882 of file R600ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::SmallVectorImpl< T >::append(), llvm::ISD::BITCAST, llvm::EVT::bitsGT(), llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::AMDGPUISD::EXPORT, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FNEG, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSelectCC(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SDNode::getVTList(), llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::TargetLoweringBase::isCondCodeLegal(), llvm::AMDGPUTargetLowering::isHWFalseValue(), llvm::AMDGPUTargetLowering::isHWTrueValue(), llvm::EVT::isInteger(), llvm::TargetLoweringBase::isOperationLegal(), llvm::SDNode::op_begin(), llvm::SDNode::op_end(), llvm::ISD::SELECT_CC, llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::AMDGPUISD::TEXTURE_FETCH, llvm::ISD::TRUNCATE, llvm::ISD::UINT_TO_FP, and llvm::ISD::UNDEF.
| void R600TargetLowering::ReplaceNodeResults | ( | SDNode * | , |
| SmallVectorImpl< SDValue > & | , | ||
| SelectionDAG & | |||
| ) | const [override, virtual] |
This callback is invoked when a node result type is illegal for the target, and the operation was registered to use 'custom' lowering for that result type. The target places new result values for the node in Results (their number and types must exactly match those of the original return values of the node), or leaves Results empty, which indicates that the node is not to be custom lowered after all.
If the target has no operations that require custom lowering, it need not implement this. The default implementation aborts.
Reimplemented from llvm::AMDGPUTargetLowering.
Definition at line 841 of file R600ISelLowering.cpp.
References llvm::ISD::AND, llvm::AMDGPUISD::BFE_U32, llvm::AArch64ISD::BIT, llvm::ISD::BUILD_PAIR, llvm::TargetLowering::expandFP_TO_SINT(), llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getHalfSizedIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSelectCC(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::AMDGPUSubtarget::hasBFE(), llvm::MVT::i1, llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::ISD::OR, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::ISD::SDIV, llvm::ISD::SDIVREM, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SHL, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SUB, llvm::AMDGPUTargetLowering::Subtarget, llvm::ISD::UDIV, llvm::ISD::UDIVREM, and llvm::ISD::UREM.
The documentation for this class was generated from the following files:
1.7.6.1