llvm::SITargetLowering Class Reference

#include <SIISelLowering.h>

Inheritance diagram for llvm::SITargetLowering:

Collaboration diagram for llvm::SITargetLowering:

List of all members.

Public Member Functions
	SITargetLowering (TargetMachine &tm)
bool	isLegalAddressingMode (const AddrMode &AM, Type *Ty) const override
bool	allowsMisalignedMemoryAccesses (EVT VT, unsigned AS, unsigned Align, bool *IsFast) const override
	Determine if the target supports unaligned memory accesses.
EVT	getOptimalMemOpType (uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
TargetLoweringBase::LegalizeTypeAction	getPreferredVectorAction (EVT VT) const override
	Return the preferred vector type legalization action.
bool	shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const override
	Return true if it is beneficial to convert a load of a constant to just the constant itself. On some targets it might be more efficient to use a combination of arithmetic instructions to materialize the constant instead of loading it from a constant pool.
SDValue	LowerFormalArguments (SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
MachineBasicBlock *	EmitInstrWithCustomInserter (MachineInstr *MI, MachineBasicBlock *BB) const override
EVT	getSetCCResultType (LLVMContext &Context, EVT VT) const override
MVT	getScalarShiftAmountTy (EVT VT) const override
bool	isFMAFasterThanFMulAndFAdd (EVT VT) const override
SDValue	LowerOperation (SDValue Op, SelectionDAG &DAG) const override
SDValue	PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const override
SDNode *	PostISelFolding (MachineSDNode *N, SelectionDAG &DAG) const override
	Fold the instructions after selecting them.
void	AdjustInstrPostInstrSelection (MachineInstr *MI, SDNode *Node) const override
	Assign the register class depending on the number of bits set in the writemask.
int32_t	analyzeImmediate (const SDNode *N) const
	Analyze the possible immediate value Op.
SDValue	CreateLiveInRegister (SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const override
	Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.

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Detailed Description

Definition at line 23 of file SIISelLowering.h.

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Constructor & Destructor Documentation

SITargetLowering::SITargetLowering

(

TargetMachine &

tm

)

Definition at line 38 of file SIISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::TargetLoweringBase::AddPromotedToType(), llvm::TargetLoweringBase::addRegisterClass(), llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_STORE, llvm::ISD::ATOMIC_SWAP, llvm::ISD::BITCAST, llvm::ISD::BRCOND, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::TargetLoweringBase::computeRegisterProperties(), llvm::ISD::CONCAT_VECTORS, llvm::TargetLoweringBase::Custom, llvm::TargetLoweringBase::Expand, llvm::ISD::EXTLOAD, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FCEIL, llvm::ISD::FCOS, llvm::ISD::FDIV, llvm::ISD::FFLOOR, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FrameIndex, llvm::ISD::FRINT, llvm::ISD::FSIN, llvm::ISD::FSUB, llvm::ISD::FTRUNC, llvm::AMDGPUSubtarget::getGeneration(), llvm::ISD::GlobalAddress, I, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLoweringBase::Legal, llvm::ISD::LOAD, llvm::MVT::Other, llvm::TargetLoweringBase::Promote, llvm::Sched::RegPressure, llvm::AMDGPUSubtarget::SEA_ISLANDS, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::TargetLoweringBase::setCondCodeAction(), llvm::TargetLoweringBase::setLoadExtAction(), llvm::ISD::SETONE, llvm::TargetLoweringBase::setOperationAction(), llvm::TargetLoweringBase::setSchedulingPreference(), llvm::TargetLoweringBase::setTargetDAGCombine(), llvm::TargetLoweringBase::setTruncStoreAction(), llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::STORE, llvm::ISD::SUBC, llvm::ISD::SUBE, llvm::AMDGPUTargetLowering::Subtarget, llvm::ISD::UDIV, llvm::ISD::UINT_TO_FP, llvm::ISD::UREM, llvm::MVT::v16f32, llvm::MVT::v16i16, llvm::MVT::v16i32, llvm::MVT::v16i8, llvm::MVT::v1f64, llvm::MVT::v2f32, llvm::MVT::v2i1, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v2i8, llvm::MVT::v32i8, llvm::MVT::v4f32, llvm::MVT::v4i1, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i8, llvm::MVT::v64i8, llvm::MVT::v8f32, llvm::MVT::v8f64, llvm::MVT::v8i16, llvm::MVT::v8i32, llvm::ISD::VECTOR_SHUFFLE, and llvm::ISD::ZEXTLOAD.

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Member Function Documentation

void SITargetLowering::AdjustInstrPostInstrSelection	(	MachineInstr *	MI,
		SDNode *	Node
	)		const [override, virtual]

Assign the register class depending on the number of bits set in the writemask.

Reimplemented from llvm::TargetLowering.

Definition at line 1891 of file SIISelLowering.cpp.

References llvm::AMDGPU::getAtomicNoRetOp(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::AMDGPUInstrInfo::getMaskedMIMGOp(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetMachine::getSubtargetImpl(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SDNode::hasAnyUseOfValue(), llvm::SIInstrInfo::isMIMG(), llvm::MachineInstr::RemoveOperand(), llvm::MachineInstr::setDesc(), and llvm::MachineRegisterInfo::setRegClass().

bool SITargetLowering::allowsMisalignedMemoryAccesses	(	EVT	,
		unsigned	AddrSpace,
		unsigned	Align,
		bool *
	)		const [override, virtual]

Determine if the target supports unaligned memory accesses.

This function returns true if the target allows unaligned memory accesses of the specified type in the given address space. If true, it also returns whether the unaligned memory access is "fast" in the last argument by reference. This is used, for example, in situations where an array copy/move/set is converted to a sequence of store operations. Its use helps to ensure that such replacements don't generate code that causes an alignment error (trap) on the target machine.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 305 of file SIISelLowering.cpp.

References llvm::EVT::bitsGT(), llvm::MVT::i32, llvm::EVT::isSimple(), AMDGPUAS::LOCAL_ADDRESS, and llvm::MVT::Other.

int32_t SITargetLowering::analyzeImmediate

(

const SDNode *

N

)

const

Analyze the possible immediate value Op.

Returns -1 if it isn't an immediate, 0 if it's and inline immediate and the immediate value if it's a literal immediate

Definition at line 1485 of file SIISelLowering.cpp.

References F(), llvm::MVT::f32, llvm::SDNode::getValueType(), I, and Node.

SDValue SITargetLowering::CreateLiveInRegister	(	SelectionDAG &	DAG,
		const TargetRegisterClass *	RC,
		unsigned	Reg,
		EVT	VT
	)		const [override, virtual]

Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.

Returns:

a RegisterSDNode representing Reg.

Reimplemented from llvm::AMDGPUTargetLowering.

Definition at line 1974 of file SIISelLowering.cpp.

References llvm::SelectionDAG::getCopyFromReg(), and llvm::SelectionDAG::getEntryNode().

MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter	(	MachineInstr *	MI,
		MachineBasicBlock *	MBB
	)		const [override, virtual]

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag. These instructions are special in various ways, which require special support to insert. The specified MachineInstr is created but not inserted into any basic blocks, and this method is called to expand it into a sequence of instructions, potentially also creating new basic blocks and control flow.

Reimplemented from llvm::TargetLowering.

Definition at line 570 of file SIISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetMachine::getSubtargetImpl(), llvm::TargetLoweringBase::getTargetMachine(), I, llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::AArch64CC::MI, llvm::TargetOpcode::REG_SEQUENCE, llvm::AMDGPU::RSRC_DATA_FORMAT, and TII.

EVT SITargetLowering::getOptimalMemOpType	(	uint64_t	,
		unsigned	,
		unsigned	,
		bool	,
		bool	,
		bool	,
		MachineFunction &
	)		const [override, virtual]

Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering.

If DstAlign is zero that means it's safe to destination alignment can satisfy any constraint. Similarly if SrcAlign is zero it means there isn't a need to check it against alignment requirement, probably because the source does not need to be loaded. If 'IsMemset' is true, that means it's expanding a memset. If 'ZeroMemset' is true, that means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does not need to be loaded. It returns EVT::Other if the type should be determined using generic target-independent logic.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 339 of file SIISelLowering.cpp.

References llvm::MVT::Other, llvm::MVT::v2i32, and llvm::MVT::v4i32.

TargetLoweringBase::LegalizeTypeAction SITargetLowering::getPreferredVectorAction

(

EVT

VT

)

const [override, virtual]

Return the preferred vector type legalization action.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 360 of file SIISelLowering.cpp.

References llvm::EVT::bitsLE(), llvm::EVT::getScalarType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i16, and llvm::TargetLoweringBase::TypeSplitVector.

MVT SITargetLowering::getScalarShiftAmountTy

(

EVT

VT

)

const [override, virtual]

Reimplemented from llvm::TargetLoweringBase.

Definition at line 686 of file SIISelLowering.cpp.

References llvm::MVT::i32.

EVT SITargetLowering::getSetCCResultType	(	LLVMContext &	Context,
		EVT	VT
	)		const [override, virtual]

Return the ValueType of the result of SETCC operations. Also used to obtain the target's preferred type for the condition operand of SELECT and BRCOND nodes. In the case of BRCOND the argument passed is MVT::Other since there are no other operands to get a type hint from.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 679 of file SIISelLowering.cpp.

References llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::MVT::i1, and llvm::EVT::isVector().

bool SITargetLowering::isFMAFasterThanFMulAndFAdd

(

EVT

)

const [override, virtual]

Return true if an FMA operation is faster than a pair of fmul and fadd instructions. fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.

NOTE: This may be called before legalization on types for which FMAs are not legal, but should return true if those types will eventually legalize to types that support FMAs. After legalization, it will only be called on types that support FMAs (via Legal or Custom actions)

Reimplemented from llvm::TargetLoweringBase.

Definition at line 690 of file SIISelLowering.cpp.

References llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and llvm::MVT::SimpleTy.

bool SITargetLowering::isLegalAddressingMode	(	const AddrMode &	AM,
		Type *	Ty
	)		const [override, virtual]

Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

The type may be VoidTy, in which case only return true if the addressing mode is legal for a load/store of any legal type. TODO: Handle pre/postinc as well.

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 273 of file SIISelLowering.cpp.

References llvm::TargetLoweringBase::AddrMode::BaseGV, llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::TargetLoweringBase::AddrMode::HasBaseReg, llvm::isUInt< 16 >(), and llvm::TargetLoweringBase::AddrMode::Scale.

SDValue SITargetLowering::LowerFormalArguments	(	SDValue	,
		CallingConv::ID	,
		bool	,
		const SmallVectorImpl< ISD::InputArg > &	,
		SDLoc	,
		SelectionDAG &	,
		SmallVectorImpl< SDValue > &
	)		const [override, virtual]

This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array, into the specified DAG. The implementation should fill in the InVals array with legal-type argument values, and return the resulting token chain value.

Reimplemented from llvm::TargetLowering.

Definition at line 398 of file SIISelLowering.cpp.

References llvm::MachineFunction::addLiveIn(), llvm::AMDGPUTargetLowering::AnalyzeFormalArguments(), llvm::ISD::AssertZext, llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, ShaderType::COMPUTE, llvm::dyn_cast(), llvm::ISD::InputArg::Flags, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::MachineFunction::getFunction(), llvm::Function::getFunctionType(), llvm::AMDGPUSubtarget::getGeneration(), llvm::MachineFunction::getInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::TargetRegisterInfo::getMinimalPhysRegClass(), llvm::SelectionDAG::getNode(), llvm::AMDGPUTargetLowering::getOriginalFunctionArgs(), llvm::FunctionType::getParamType(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::SelectionDAG::getRoot(), llvm::AMDGPUMachineFunction::getShaderType(), llvm::MVT::getStoreSize(), llvm::TargetMachine::getSubtargetImpl(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::Type::getVectorNumElements(), llvm::MVT::i16, llvm::MVT::i64, llvm::MipsISD::Ins, llvm::ISD::ArgFlagsTy::isByVal(), llvm::ISD::ArgFlagsTy::isInReg(), llvm::CCValAssign::isMemLoc(), llvm::CCValAssign::isRegLoc(), llvm::MVT::isVector(), AMDGPUAS::LOCAL_ADDRESS, llvm::SIMachineFunctionInfo::NumUserSGPRs, llvm::ISD::InputArg::OrigArgIndex, llvm::ISD::InputArg::PartOffset, ShaderType::PIXEL, llvm::SIMachineFunctionInfo::PSInputAddr, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::ISD::ArgFlagsTy::setSplit(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::AMDGPUSubtarget::SOUTHERN_ISLANDS, llvm::AMDGPUTargetLowering::Subtarget, llvm::ISD::InputArg::Used, and llvm::ISD::InputArg::VT.

SDValue SITargetLowering::LowerOperation	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const [override, virtual]

This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal. If the target has no operations that require custom lowering, it need not implement this. The default implementation of this aborts.

Reimplemented from llvm::AMDGPUTargetLowering.

Definition at line 712 of file SIISelLowering.cpp.

References llvm::ISD::BRCOND, llvm::ISD::FCOS, llvm::ISD::FDIV, llvm::ISD::FrameIndex, llvm::ISD::FSIN, llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::ISD::GlobalAddress, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::LOAD, llvm::ISD::SELECT, and llvm::ISD::STORE.

SDValue SITargetLowering::PerformDAGCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const [override, virtual]

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.

The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.

In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.

Reimplemented from llvm::AMDGPUTargetLowering.

Definition at line 1339 of file SIISelLowering.cpp.

References llvm::ARM_PROC::A, llvm::AfterLegalizeDAG, llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_STORE, llvm::ISD::ATOMIC_SWAP, llvm::CallingConv::C, llvm::TargetLowering::DAGCombinerInfo::CommitTargetLoweringOpt(), llvm::AMDGPUISD::CVT_F32_UBYTE0, llvm::AMDGPUISD::CVT_F32_UBYTE1, llvm::AMDGPUISD::CVT_F32_UBYTE2, llvm::AMDGPUISD::CVT_F32_UBYTE3, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::MVT::f32, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FSUB, llvm::MemSDNode::getAddressSpace(), llvm::MemSDNode::getBasePtr(), llvm::APInt::getBitsSet(), llvm::SelectionDAG::getConstant(), llvm::TargetLowering::DAGCombinerInfo::getDAGCombineLevel(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), I, llvm::MVT::i1, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::ISD::LOAD, llvm::AMDGPUISD::MAD, AMDGPUAS::PRIVATE_ADDRESS, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::ISD::SETCC, llvm::ISD::SETNE, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::TargetLowering::SimplifySetCC(), llvm::ISD::STORE, llvm::ISD::UINT_TO_FP, and llvm::SelectionDAG::UpdateNodeOperands().

SDNode * SITargetLowering::PostISelFolding	(	MachineSDNode *	N,
		SelectionDAG &	DAG
	)		const [override, virtual]

Fold the instructions after selecting them.

Reimplemented from llvm::AMDGPUTargetLowering.

Definition at line 1877 of file SIISelLowering.cpp.

References llvm::TargetSubtargetInfo::getInstrInfo(), llvm::SDNode::getMachineOpcode(), llvm::TargetMachine::getSubtargetImpl(), llvm::TargetLoweringBase::getTargetMachine(), and llvm::SIInstrInfo::isMIMG().

bool SITargetLowering::shouldConvertConstantLoadToIntImm	(	const APInt &	Imm,
		Type *	Ty
	)		const [override, virtual]

Return true if it is beneficial to convert a load of a constant to just the constant itself. On some targets it might be more efficient to use a combination of arithmetic instructions to materialize the constant instead of loading it from a constant pool.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 367 of file SIISelLowering.cpp.

References llvm::TargetSubtargetInfo::getInstrInfo(), llvm::TargetMachine::getSubtargetImpl(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SIInstrInfo::isInlineConstant(), and TII.

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The documentation for this class was generated from the following files:

• SIISelLowering.h
• SIISelLowering.cpp